KR20050117971A - Gate driving circuit and display apparatus having the same - Google Patents

Abstract

Disclosed are a gate driving circuit capable of preventing a malfunction and a display device having the same. The gate driving circuit includes a driver and a wiring unit disposed adjacent to the driver. The driver consists of a plurality of stages to output a gate signal. The wiring part is arranged in parallel with each other and is provided between a plurality of signal wires and signal wires which receive a plurality of signals from the outside and provide them to the driver, respectively, and block blocking wires that block interference between signals applied to the signal wires. . Therefore, it is possible to prevent the interference of the signals provided to the signal wires and the corrosion of the signal wires.

Description

Gate driving circuit and display device having same {GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME}

The present invention relates to a gate driving circuit and a display device having the same, and more particularly, to a gate driving circuit capable of preventing a malfunction and a display device having the same.

In general, a liquid crystal display device includes a liquid crystal display panel for displaying an image. The liquid crystal display panel includes a display area for displaying an image and a peripheral area adjacent to the display area. The display area includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel consists of a thin film transistor and a liquid crystal capacitor. The peripheral area includes a gate driving circuit for outputting a gate signal to gate lines and a data driving circuit for outputting a data signal to data lines.

The gate driving circuit is formed in the peripheral region of the liquid crystal display panel at the same time through the same process as the thin film transistor, and the data driving circuit is formed in the chip form and mounted on the peripheral region. The gate driving circuit includes one shift register including a plurality of stages connected to each other, and each stage is connected to a corresponding gate line to output a gate signal. The gate driving circuit further includes signal wirings for providing various signals to the shift register.

Different voltages are applied to the signal lines to drive the shift register, and a potential difference occurs between the signal lines to which the different voltages are applied. The potential difference generated between the signal wires causes interference between the signals applied to the signal wires and causes signal distortion. In addition, a phenomenon in which each of the signal wires is corroded may occur due to the potential difference.

However, as described above, since the gate driving circuit is provided in the peripheral area of the display panel, it is limited to increase the separation distance between the signal wirings. Accordingly, there is a need for a method capable of preventing corrosion of signal wires due to a potential difference while preventing distortion of a signal provided to the signal wires.

Accordingly, it is an object of the present invention to provide a gate driving circuit which can prevent a malfunction.

Further, another object of the present invention is to provide a display device having the above gate driving circuit.

The gate driving circuit according to an aspect of the present invention includes a driver and a wiring unit disposed adjacent to the driver. The driving unit includes a plurality of stages to output a gate signal. The wiring unit is disposed in parallel with each other and is provided between the plurality of signal wires and the signal wires which receive a plurality of signals from the outside and provide the signals to the driver, respectively, to block interference between the signals applied to the signal wires. It consists of blocking wiring.

In addition, the display device according to another aspect of the present invention includes a display panel, a gate driving circuit, and a data driving circuit. The display panel includes a display area in which a plurality of gate lines and a plurality of data lines are formed to display an image, and a peripheral area adjacent to the display area. The gate driving circuit is directly formed in the peripheral area to output a gate signal to the plurality of gate lines, and the data driving circuit outputs a data signal to the plurality of data lines.

The gate driving circuit includes a driver and a wiring unit disposed adjacent to the driver. The driving unit includes a plurality of stages to output a gate signal. The wiring unit is disposed in parallel with each other and is provided between the plurality of signal wires and the signal wires which receive a plurality of signals from the outside and provide the signals to the driver, respectively, to block interference between the signals applied to the signal wires. It consists of blocking wiring.

According to such a gate driving circuit and a display device having the same, a plurality of signal wires are disposed in parallel to each other and receive a plurality of signals from the outside, and a signal generated between the signal wires between the signal wires. Blocking wires are further provided to prevent the interference of the wires and the corrosion of the signal wires, thereby preventing malfunction of the gate driving circuit.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention may include a first substrate 100, a second substrate 200 facing the first substrate 100, and the first substrate 100 and the first substrate 100. The display panel 300 includes a liquid crystal layer (not shown) interposed between the second substrate 200 and the second substrate 200.

The display panel 300 includes a display area DA displaying an image and first and second peripheral areas PA1 and PA2 adjacent to the display area DA.

The display area DA includes first to nth gate lines GL1 to GLn and first to mth data lines DL1 to DLm. The first to nth gate lines GL1 to GLn extend in a first direction D1, and the first to mth data lines DL1 to DLm are orthogonal to the first direction D1. It extends in the direction D2 to cross the first to nth gate lines GL1 to GLn to be insulated from each other. Accordingly, the pixel area of the matrix form is formed in the display area DA by the first to nth gate lines GL1 to GLn and the first to mth data lines DL1 to DLm.

Each pixel area includes a TFT 110 and a pixel including a liquid crystal capacitor Clc connected to the TFT 110. For example, the gate electrode of the TFT 110 is connected to the first gate line GL1, the source electrode is connected to the first data line DL1, and the drain electrode is coupled to the liquid crystal capacitor Clc. .

The first peripheral area PA1 is an area adjacent to one end of the first to n-th gate lines GL1 to GLn, and the first to n-th gate line GL1 is in the first peripheral area PA1. A gate driving circuit 350 for sequentially outputting a gate signal to GLn is formed. The gate driving circuit 350 is formed in the first peripheral area PA1 simultaneously with the TFT 110 through the same process as the TFT 110 formed in the display area DA.

The second peripheral area PA2 is an area adjacent to one end of the first to m-th data lines DL1 to DLm, and the first to m-th data line is in the second peripheral area PA2. A data driving chip 370 for outputting a data signal to DL1 to DLm is mounted.

In addition, one side of the second peripheral area PA2 may include an external device (not shown) for driving the liquid crystal display panel 300 and a flexible printed circuit board for electrically connecting the liquid crystal display panel 300. Hereinafter, the FPC 400 is further attached.

The FPC 400 is electrically connected to the data driving chip 370 to provide a first control signal from the external device to the data driving chip 370. Therefore, the data driving chip 370 outputs the data signal in response to the first control signal. The FPC 400 is connected to the gate driving circuit 350 or directly to the gate driving circuit 350 through the data driving chip 370. The FPC 400 provides a second control signal from the external device to the gate driving circuit 350, and the gate driving circuit 350 outputs the gate signal in response to the second control signal.

FIG. 2 is a diagram illustrating the gate driving circuit shown in FIG. 1 in detail.

Referring to FIG. 2, the gate driving circuit 350 is composed of a plurality of stages SRC1 to SRCn + 1 that are connected to each other, and outputs a gate signal sequentially and various control signals to the driving unit DS. It includes a wiring unit LS for providing. Where n is even.

Each of the plurality of stages SRC1 to SRCn + 1 includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, and an output terminal OUT. And a ground voltage terminal V1.

A first clock CKV is provided to the first clock terminal CK1 of odd-numbered stages SRC1, SRC3, ... SRCn + 1 among the plurality of stages, and even-numbered stages SRC2, ... SRCn A second clock CKVB having a phase inverted with the first clock CKV is provided to the first clock terminal CK2 of the reference signal. The second clock terminal CKVB of the odd stages SRC1, SRC3, ... SRCn + 1 is provided with the second clock CKVB, and the even stages SRC2, SRCn The first clock CKV is provided to the second clock terminal CK2.

The signal output from the output terminal OUT of the previous stage is applied to the first input terminal IN1, and the signal output from the output terminal OUT of the next stage is applied to the second input terminal IN2. do.

In this case, the first input terminal IN1 of the first driving stage SRC1 is provided with a start signal STV, which is not an output signal of the previous stage. In addition, the second input terminal IN2 of the n + 1st stage SRCn + 1 provided to provide an output signal to the second input terminal IN2 of the nth stage SRCn is used instead of the output signal of the next stage. The start signal STV is provided. In addition, the ground voltage VSS is provided to the ground voltage terminals V1 of the plurality of stages SRC1 to SRCn + 1.

The first clock CKV is output from the output terminal OUT of the odd-numbered stages SRC1, SRC3, ... SRCn + 1, and the output terminal of the even-numbered stages SRC2, ... SRCn. At OUT, the second clock CKVB is output. Output terminals OUT of the n stages SRC1 to SRCn are electrically connected to corresponding gate lines among the first to nth gate lines GL1 to GLn provided in the display area DA (refer to FIG. 1). Is connected. Therefore, the driver DS sequentially outputs gate signals to the first to nth gate lines GL1 to GLn.

The wiring part LS is provided adjacent to the driving part DS, and the wiring part LS extends parallel to each other to the start signal wiring SL1, the first clock wiring SL2, and the second clock wiring ( SL3), ground voltage wiring SL4, first blocking wiring RL1, second blocking wiring RL2, and third blocking wiring RL3. The start signal line SL1 is disposed closest to the driver DS, and the second clock line L3 is next to the start signal line SL1.

The start signal STV is provided to the first input terminal IN1 of the first stage SRC1 and the second input terminal IN2 of the last stage SRCn + 1 through the start signal wiring SL1. . The first clock CKV is connected to the first clock terminal CK1 and the even-numbered stages SRC2, of the odd-numbered stages SRC1, SRC3, ... SRCn + 1 through the first clock line SL2. ... is provided to the second clock terminal CK2 of SRCn. The second clock CKVB is connected to the second clock terminal CK2 and the even-numbered stages SRC2, of the odd-numbered stages SRC1, SRC3, ... SRCn + 1 through the second clock line SL3. ... provided to the first clock terminal CK1 of SRCn. In addition, the ground voltage VSS is provided to the ground voltage terminal V1 of the plurality of stages SRC1 to SRCn + 1 through the ground voltage line SL4.

The first blocking wiring RL1 is interposed between the start signal wiring SL1 and the second clock wiring SL3 to between the start signal wiring SL1 and the second clock wiring SL3. It serves to prevent signal interference from occurring.

In this case, the first blocking line RL1 is electrically connected to the second clock line SL3. For example, the second clock CKVB provided to the second clock wire SL3 swings between 20V and -12V, and one cycle of the second clock CKVB is 16.7 ms. The start signal STV provided to the start signal wiring SL1 swings between 20 and -12 V, and one period of the start signal STV is equal to a frame period, but the start signal for most of the time is-. Maintain 12V. Therefore, a potential difference occurs between the second clock wiring SL3 and the start signal wiring SL1.

As such, since the first blocking wiring RL1 is electrically connected to the second clock wiring SL3, the second clock CKVB is provided to the first blocking wiring RL1. As a result, since the first blocking wiring RL1 having the same potential is provided adjacent to the second clock wiring SL3, the second clock wiring SL3 due to the potential difference from the start signal wiring SL1. This can prevent corrosion.

The second blocking wiring RL2 is interposed between the second clock wiring SL3 and the first clock wiring SL2, so that the second clock wiring SL3 and the first clock wiring SL2 are interposed between the second clock wiring SL3 and the first clock wiring SL2. Signal interference occurring between and can be prevented. At this time, the second blocking wiring RL2 is maintained in a floating state.

The first and second clocks CKV and CKVB applied to the first clock line SL2 and the second clock line SL3 respectively have inverted phases. For example, the first clock CKV provided to the first clock wire SL2 swings between 20V and -12V, and one cycle of the first clock CKV is 16.7 ms. In addition, the second clock CKVB provided to the second clock wire SL3 swings between −12 V and 20 V, and one cycle of the second clock CKVB is 16.7 ms.

Accordingly, a potential difference of −32 V occurs between the first clock line SL2 and the second clock line SL3 for half a period, and the first clock line SL2 and the second clock line for the other half period. A potential difference of + 32V occurs between the clock wiring SL3. As a result, the potential difference generated between the first and second clock wirings SL2 and SL3 for one period becomes 0V. Thus, corrosion of the wiring due to the potential difference does not occur between the first clock wiring SL2 and the second clock wiring SL3.

In addition, the third blocking wiring RL3 is interposed between the first clock wiring SL2 and the ground voltage wiring SL4, so that the first clock wiring SL2 and the ground voltage wiring SL4 are interposed between the first clock wiring SL2 and the ground voltage wiring SL4. Signal interference occurring between and can be prevented.

In this case, the third blocking line RL3 is electrically connected to the first clock line SL2. For example, the first clock CKV provided to the first clock wire SL2 swings between 20V and -12V, and one cycle of the first clock CKV is 16.7 ms. Therefore, a potential difference occurs between the ground voltage line SL4 and the first clock line SL2. In this case, since the third blocking wiring RL3 is electrically connected to the first clock wiring SL2, the first clock CKV is provided to the third blocking wiring RL3. As a result, since the third blocking wiring RL3 having the same potential is provided adjacent to the first clock wiring SL2, the first clock wiring SL2 due to the potential difference from the ground voltage wiring SL4. This can prevent corrosion.

Accordingly, signal interference occurring between the signal wires through the first to third blocking wires RL1 to RL3 can be prevented, thereby preventing malfunction of the gate driving circuit 350. In addition, it is possible to prevent corrosion of the signal wires due to the potential difference by reducing the potential difference generated between the signal wires.

3 is an enlarged layout view of part A of FIG. 2, and FIG. 4 is a cross-sectional view taken along the cutting line B-B ′ of FIG.

Referring to FIG. 3, the wiring unit LS includes a start signal wiring SL1, a first clock wiring SL2, a second clock wiring SL3, and a ground voltage wiring SL4. In addition, the wiring part LS includes a first connection line CL1 and a first clock wire SL2 for connecting the ground voltage line SL4 to each stage of the driving unit DS (shown in FIG. 2). A second connection line CL2 for connecting to each stage and a third connection line CL3 for connecting the second clock line SL3 to each stage are further provided.

Since the first to third connection lines CL1 to CL3 extend from the signal lines SL2 to SL4 toward the driving unit DS, the first to third connection lines CL1 to CL3 may cross the signal lines SL1 to SL4. Therefore, the first to third connection lines CL1 to CL3 are provided on different layers from the signal lines SL1 to SL4.

As shown in FIG. 4, on the first substrate 100, a start signal line SL1, a first clock line SL2, a second clock line SL3, and a ground voltage line SL4 formed of a first metal film. Is formed. The gate insulating film 120 is formed thereon. The gate insulating layer 120 exposes portions of the ground voltage line SL4 and the first and second clock lines SL2 and SL3 in the first, second and third contact regions C1, C2, and C3. . First to third connection wires CL1 to CL3 (shown in FIG. 3) formed of the second metal film are formed on the gate insulating layer 120. The passivation layer 130 is formed thereon, and the passivation layer 130 is disposed on the ground voltage line SL4, the first and second clock lines SL2 and SL3 in the first to third contact regions C1 to C3. Expose a portion of the. Although not illustrated, the passivation layer 130 exposes a portion of the first to third connection lines CL1 to CL3 in the first to third contact regions C1 to C3.

As such, since the first to third connection lines CL1 to CL3 are provided on different layers from the signal lines SL1 to SL4, the first connection line CL1 is disposed on the first contact region C1. Is electrically connected to the ground voltage line SL4 through the first metal electrode E1. In addition, the second connection line CL2 is electrically connected to the first clock line SL2 through the second metal electrode E2 in the second contact region C2 and the third connection line CL3. Is electrically connected to the second clock line CL3 through the third metal electrode E3 in the third contact region C3. The first to third metal electrodes E1 to E3 are made of a transparent conductive material. For example, the first to third metal electrodes E1 to E3 are indium tin oxide (hereinafter, ITO). ) Or Indium Zinc Oxide (hereinafter referred to as IZO).

3 and 4, the first blocking line RL1 is electrically connected to the third metal electrode E3 in the third contact region C1, and is connected to the third metal electrode E3. It is made of the same material and is disposed between the second clock wiring SL3 and the start signal wiring SL1. The second blocking wiring RL2 is made of the same material as the first blocking wiring RL1 and interposed between the first clock wiring SL2 and the second clock wiring SL3. The third blocking wiring RL3 is electrically connected to the second metal electrode E2 in the second contact region C2, and is made of the same material as the second metal electrode E2. ) Is interposed between the ground voltage line SL4 and the ground voltage line SL4.

As described above, since the first to third blocking wires RL1 to RL3 are made of ITO or IZO, which is resistant to oxidation, oxidation of the first to third blocking wires RL1 to RL3 due to a potential difference can be prevented.

The first to third blocking wires RL1 to RL3 may not cross the first to third connection wires CL1 to CL3. Accordingly, the first to third blocking wires RL1 to RL3 are formed only in a space between the first to third connection wires CL1 to CL3. Incision is made in position.

5 is a view illustrating the gate driving circuit shown in FIG. 1 in detail. However, among the components shown in FIG. 5, the same reference numerals are given to the same elements as those shown in FIG. 2, and detailed description thereof will be omitted.

Referring to FIG. 5, the gate driving circuit 350 may include a driving unit DS and a wiring unit LS, and the wiring unit LS may include a start signal line SL1, a first clock line SL2, and a first line. In addition to the two clock lines SL3 and the ground voltage line SL4, the first, second, and third blocking lines RL1, RL2, and RL3 are further included.

The first blocking wiring RL1 is interposed between the start signal wiring SL1 and the second clock wiring SL3, and the second blocking wiring RL2 is connected to the second clock wiring SL3. It is interposed between the first clock wiring SL2. In addition, the third blocking line RL3 is interposed between the first clock line SL2 and the ground voltage line SL4.

Unlike the exemplary embodiment of FIG. 2, the first blocking line RL1 and the third blocking line RL3 are connected to the second clock line SL3 and the first clock line SL2. And are electrically isolated from each other. Therefore, the first to third blocking wirings RL1 to RL3 are floating lines in which no signal is applied.

The first blocking wiring RL1 in the floating state prevents signal interference occurring between the second clock wiring SL3 and the start signal wiring SL1. In addition, the second blocking wiring RL2 in the floating state prevents signal interference occurring between the first clock wiring SL2 and the second clock wiring SL3. Finally, the third blocking wiring RL3 in the floating state prevents signal interference occurring between the first clock wiring SL2 and the ground voltage wiring SL4. As such, by preventing signal interference occurring between the signal wires through the first to third blocking wires RL1 to RL3, malfunction of the gate driving circuit 350 may be prevented. In addition, it is possible to prevent corrosion of the signal wires due to the potential difference by reducing the potential difference generated between the signal wires.

6 is an enlarged layout view of part C of FIG. 4, and FIG. 7 is a cross-sectional view taken along the cutting line D-D ′ of FIG. 6.

6 and 7, the wiring unit LS includes a start signal wiring SL1, a first clock wiring SL2, a second clock wiring SL3, and a ground voltage wiring SL4. In addition, the wiring part LS may further include a first connection wire CL1, a second connection wire CL2, and a third connection wire CL3.

The first connection line CL1 is provided on a different layer from the ground voltage line SL4 and electrically connected to the ground voltage line SL4 through the first metal electrode E1 in the first contact region C1. Is connected. In addition, the second connection line CL2 is electrically connected to the first clock line SL2 in the second contact region C2 through the second metal electrode E2. The third connection line CL3 is electrically connected to the second clock line CL3 through the third metal electrode E3 in the third contact region C3. The first to third metal electrodes E1 to E3 are made of a transparent conductive material. For example, the first to third metal electrodes E1 to E3 include ITO or IZO.

The first blocking wiring RL1 of the wiring unit LS is made of the same material as the third metal electrode E3 and is disposed between the second clock wiring SL3 and the start signal wiring SL1. Is placed. The second blocking wiring RL2 is made of the same material as the first blocking wiring RL1 and interposed between the first clock wiring SL2 and the second clock wiring SL3. The third blocking line RL3 is made of the same material as the second metal electrode E2 and interposed between the first clock line SL2 and the ground voltage line SL4.

As described above, since the first to third blocking wires RL1 to RL3 are made of ITO or IZO, which is resistant to oxidation, oxidation of the first to third blocking wires RL1 to RL3 due to a potential difference can be prevented.

According to such a gate driving circuit and a display device having the same, a plurality of signal wires are disposed in parallel with each other and receive a plurality of signals from the outside, and blocking wires are provided between the signal wires.

Therefore, interference of signals generated between signal wires provided with different signals can be prevented, and corrosion of signal wires due to potential differences generated between the signal wires can be prevented. As a result, malfunction of the gate driving circuit can be prevented.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating the gate driving circuit shown in FIG. 1 in detail.

3 is an enlarged layout view of part A of FIG. 2.

4 is a cross-sectional view taken along the cutting line BB ′ shown in FIG. 3.

5 is a diagram illustrating a gate driving circuit according to another exemplary embodiment.

FIG. 6 is an enlarged layout view of a portion C shown in FIG. 4.

FIG. 7 is a cross-sectional view taken along the cutting line D-D ′ of FIG. 6.

* Description of the symbols for the main parts of the drawings *

100: first substrate 110: TFT

200: second substrate 300: display panel

350: gate driving circuit 370: data driving chip

400: flexible circuit board 500: display device

Claims (8)

A driver comprising a plurality of stages to output a gate signal; And Blocking wires arranged in parallel to each other and provided between the signal wires and the signal wires provided to the driver to receive a plurality of signals from the outside, respectively, to block the interference between signals applied to the signal wires. A gate driving circuit comprising a wiring portion made. The method of claim 1, wherein the plurality of signal wires, A start signal wiring for providing a start signal to a first stage of the plurality of stages; A first clock wire providing the first clock to odd-numbered stages; A second clock wiring disposed between the start signal wiring and the first clock wiring and providing a second clock having an inverted phase with the first clock to even-numbered stages of the plurality of stages; And And a ground voltage line adjacent to the first clock line and providing a ground voltage to the plurality of stages. The method of claim 2, wherein the blocking wiring, A first blocking wiring interposed between the start signal wiring and the second clock wiring; A second blocking wiring interposed between the first clock wiring and the second clock wiring; And And a third blocking wiring interposed between the first clock wiring and the ground voltage wiring. The method of claim 3, wherein the first blocking wire is electrically connected to the second clock wire to apply the second clock. The second blocking wiring is maintained in a floating state, And the third blocking wiring is electrically connected to the first clock wiring so that the first clock is applied. 4. The gate driving circuit according to claim 3, wherein the first to third blocking wirings are maintained in a floating state. A display panel having a plurality of gate lines and a plurality of data lines formed thereon to display an image and a peripheral area adjacent to the display area; A gate driving circuit formed directly in the peripheral region and outputting a gate signal to the plurality of gate lines; And A data driver circuit for outputting data signals to the plurality of data lines; The gate driving circuit, A driver configured to include a plurality of stages to output the gate signal; And Blocking wiring arranged in parallel to each other and provided between the plurality of signal wirings receiving the plurality of signals from the outside and provided to the driver and the signal wirings to block the interference between the signals applied to the signal wirings. Display device comprising a wiring portion made of. The method of claim 6, wherein the plurality of signal wiring, A start signal wiring for providing a start signal to a first stage of the plurality of stages; A first clock wire providing the first clock to odd-numbered stages; A second clock wiring disposed between the start signal wiring and the first clock wiring and providing a second clock having a phase inverted with the first clock to even-numbered stages of the plurality of stages; And And a ground voltage line adjacent to the first clock line and providing a ground voltage to the plurality of stages. The method of claim 7, wherein the blocking wiring, A first blocking wiring interposed between the start signal wiring and the second clock wiring, the first blocking wiring electrically connected to the second clock wiring and applied with the second clock; A second blocking wiring interposed between the first clock wiring and the second clock wiring and maintaining a floating state; And And a third blocking line interposed between the first clock line and the ground voltage line and electrically connected to the first clock line and to which the first clock is applied.