KR20050115269A - Digital pll circuit - Google Patents

Abstract

A frequency comparator compares the frequency of a reference clock with that of an output clock and outputs a frequency comparison signal. A variable frequency circuit is composed of a delay circuit having inverting circuits connected in series and a first selection circuit. The first selection circuit selects one of odd output signals outputted from odd inverting circuits according to the frequency comparison signal and feeds it back to the input of the delay circuit as a feedback signal. A phase comparator compares the phase of the reference clock with that of the output clock and outputs a phase comparison signal. A second selection circuit selects one of odd output signals according to the phase comparison signal and outputs the selected signal as an output clock. The variable frequency circuit adjusts the number of connected stages of the inverting circuits constituting a feedback loop and thereby functions as a variable oscillator for varying the frequency of the output clock. The delay circuit is used for both frequency and phase adjustments of the output clock. Thus, the circuit scale can be reduced.

Description

DIGITAL PLL CIRCUIT

The present invention relates to a digital phase locked loop (PLL) circuit used in a frequency synthesizer, an FM demodulator, and the like.

In the case of reproducing digital data recorded on a recording medium such as a magnetic tape or a magneto-optical disc, a reproduction clock is required in order to extract the reproduction data from information read from the recording medium. For example, a PLL circuit is used to generate a clock synchronized with this read information.

When the PLL circuit is formed as an analog circuit, there is a problem that it does not operate stably against variations in manufacturing of semiconductor elements and variations in operating conditions (temperature, voltage, etc.). In addition, since the analog circuit is larger than the digital circuit, the circuit scale of the PLL circuit is increased. For this reason, PLL circuits have recently been formed as digital circuits. A digital PLL circuit of this type is disclosed, for example, in Japanese Patent Laid-Open No. 8-274629.

1 shows a digital PLL circuit described in Japanese Patent Laid-Open No. 8-274629.

The digital PLL circuit 9 includes a phase comparator 1, a decoder 2, an output clock select circuit 3, an oscillator 4, a clock generator circuit 5, a variable divider 6, a loop filter 7 And a frequency comparator 8.

The frequency comparator 8 detects a frequency error between the reference clock Sin and the output clock Sout and outputs a frequency error signal. The loop filter 7 integrates the frequency error signal in order to prevent it from following the minute fluctuation of the frequency, and outputs a control signal for the variable divider 6. The variable divider 6 divides the master clock output by the oscillator 4 with the division ratio according to the control signal and outputs the divided master clock. The clock generation circuit 5 outputs a plurality of clocks that are out of phase with each other based on the divided master clock. The phase comparator 1 detects a phase error between the reference clock Sin and the output clock Sout and outputs a phase error signal. The decoder 2 decodes the phase error signal and outputs an output clock selection signal. The output clock selection circuit 3 selects an optimal clock among a plurality of clocks output by the clock generation circuit 5 so that the phase error between the reference clock Sin and the output clock Sout is minimized according to the output clock selection signal. It selects and outputs as an output clock Sout.

By the above configuration, the frequency and phase of the output clock Sout are adjusted to approach the frequency and phase of the reference clock Sin, respectively.

In the digital PLL circuit 9, the output clock Sout is generated by appropriately dividing the master clock generated by the oscillator 4. For this reason, the oscillator 4 must generate a master clock of a sufficiently high frequency in accordance with the frequency of the output clock Sout. In the digital PLL circuit 9, since the variable divider 6 for changing the frequency of the oscillator 4 and the master clock output from the oscillator 4 is formed separately, the circuit scale is increased.

Hereinafter, the prior art document related to this invention is opened.

Patent Document 1: Japanese Patent Application Laid-Open No. 8-274629 (FIGS. 1 to 3 and paragraphs [0015] to [0025])

1 is a block diagram showing a conventional digital PLL circuit.

Fig. 2 is a block diagram showing the first embodiment of the digital PLL circuit of the present invention.

3 is a block diagram showing in detail the frequency comparator and the first control circuit in the first embodiment.

4 is a block diagram showing in detail the phase comparator and the second control circuit according to the first embodiment.

FIG. 5 is a block diagram showing an example of first and second selection circuits in the first embodiment. FIG.

Fig. 6 is a block diagram showing a second embodiment of the digital PLL circuit of the invention.

Fig. 7 is a block diagram showing details of the frequency comparator and the first control circuit in the second embodiment.

8 is a block diagram showing a third embodiment of the digital PLL circuit of the invention.

Fig. 9 is a block diagram showing the fourth embodiment of the digital PLL circuit of the invention.

Fig. 10 is a block diagram showing the fifth embodiment of the digital PLL circuit of the invention.

Fig. 11 is a block diagram showing the sixth embodiment of the digital PLL circuit of the invention.

Fig. 12 is a block diagram showing details of the frequency comparator in the sixth embodiment.

Fig. 13 is a block diagram showing details of the phase comparator and the second control circuit in the sixth embodiment.

Fig. 14 is a block diagram showing the seventh embodiment of the digital PLL circuit of the invention.

Fig. 15 is a block diagram showing details of the frequency comparator in the seventh embodiment.

Fig. 16 is a block diagram showing an eighth embodiment of the digital PLL circuit of the invention.

Fig. 17 is a block diagram showing details of the frequency comparator in the eighth embodiment.

Fig. 18 is a block diagram showing the ninth embodiment of the digital PLL circuit of the invention.

Fig. 19 is a block diagram showing details of the frequency comparator in the ninth embodiment.

20 is a block diagram showing a tenth embodiment of the digital PLL circuit of the invention.

Fig. 21 is a block diagram showing the eleventh embodiment of the digital PLL circuit of the invention.

Fig. 22 is a block diagram showing a twelfth embodiment of the digital PLL circuit of the invention.

It is an object of the present invention to provide a digital PLL circuit having a small size and low jitter characteristic.

Another object of the present invention is to match the frequency and phase of the output clock of the digital PLL circuit with the frequency and phase of the reference clock in a short time, respectively.

Another object of the present invention is to independently and easily adjust the frequency and phase of the output clock of the digital PLL circuit.

Another object of the present invention is to prevent a disturbance or the like from occurring in an output clock of a digital PLL circuit.

Another object of the present invention is to easily divide or multiply the output clock of the digital PLL circuit.

In one form of the digital PLL circuit of the present invention, the frequency comparator compares the frequencies of the reference clock and the output clock generated in accordance with the reference clock to output a frequency comparison signal indicating the comparison result. The frequency variable circuit has a delay circuit and a first selection circuit. The delay circuit has a plurality of inverting circuits connected in series. The first selection circuit selects any of the odd output signals output from the odd-numbered inverting circuit in accordance with the frequency comparison signal and returns the feedback signal to the input of the delay circuit. For this reason, the frequency of a feedback signal can be changed according to the comparison result of a frequency comparator. The phase comparator compares the phases of the reference clock and the output clock and outputs a phase comparison signal indicating the comparison result. The second selection circuit selects any of the odd output signals in accordance with the phase comparison signal and outputs the output clock. For this reason, the phase of an output clock can be changed according to the comparison result of a phase comparator.

The frequency variable circuit functions as a variable oscillator for changing the frequency of the output clock by adjusting the number of stages of the inverting circuits forming the feedback loop. For this reason, it is unnecessary to separately form a circuit for changing the frequency of the oscillator and the clock output from the oscillator, and the circuit scale can be reduced. Furthermore, since the delay circuit is commonly used for both frequency adjustment and phase adjustment of the output clock, the circuit scale can be reduced.

In another aspect of the digital PLL circuit of the present invention, the frequency comparator outputs a frequency coincidence signal by determining that the frequencies of both clocks match when the frequency difference between the reference clock and the output clock is within a predetermined range. The phase comparator compares the phases of the reference clock and the output clock during the output of the frequency coincidence signal.

The phase of the output clock is adjusted after the frequency of the output clock matches the frequency of the reference clock. Since the frequency and phase of the output clock are adjusted independently of each other, one adjustment does not affect the other. For this reason, the frequency and phase of an output clock can be adjusted stably, respectively. As a result, the frequency and phase of the output clock can be easily matched to the frequency and phase of the reference clock, respectively, in a short time.

In another aspect of the digital PLL circuit of the present invention, the first reference divider divides the reference clock at a predetermined division ratio and outputs it as the first division reference clock. The frequency comparator has a first counter, a second counter and a case comparator. The first counter counts the reference clock and outputs the counted value as the first counter value signal. The second counter counts the output clock and outputs the counted value as the second counter value signal. The first and second counters are reset in response to the first divided reference clock. The magnitude comparator compares the first counter value of the first counter indicated by the first counter value signal and the second counter value of the second counter indicated by the second counter value signal, and outputs the comparison result as a frequency comparison signal.

To this end, the frequency difference between the reference clock and the output clock can be easily detected by simply counting the number of clocks of the reference clock and the output clock and comparing the counted values.

In another aspect of the digital PLL circuit of the present invention, the magnitude comparator outputs a frequency coincidence signal when the first and second counter values coincide. The phase comparator compares the phases of the reference clock and the output clock during the output of the frequency coincidence signal.

The phase of the output clock is adjusted after the frequency of the output clock matches the frequency of the reference clock. Since the frequency and phase of the output clock are adjusted independently of each other, one adjustment does not affect the other. For this reason, the frequency and phase of an output clock can be adjusted stably, respectively. As a result, the frequency and phase of the output clock can be easily matched to the frequency and phase of the reference clock, respectively, in a short time.

In another form of the digital PLL circuit of the present invention, the magnitude comparator outputs a frequency coincidence signal whenever the first and second counter values coincide. The first reference divider divides the reference clock at a predetermined division ratio and outputs it as the first division reference clock. The first reference divider operates as a variable divider which sequentially increases the period of the first divided reference clock in response to the frequency coincidence signal.

For this reason, each time the first and second counter values coincide, the period in which the first and second counters are reset becomes large. Since the increment of the first and second counter values increases each time the first and second counter values coincide, the accuracy of frequency comparison can be improved. By changing the period (count period) for comparing the frequencies of the reference clock and the output clock sequentially from short to long periods of time, the accuracy of frequency comparison can be improved step by step. As a result, the frequency of the output clock can be matched to the frequency of the reference clock in a short time as compared with the case where the precision of the frequency comparison is not changed.

In another aspect of the digital PLL circuit of the present invention, the first control circuit has a first up-down counter. The first up-down counter, in synchronization with the first divided reference clock, outputs a value counted up or down in accordance with the frequency comparison signal output from the magnitude comparator as a first selection signal. The first selection signal represents an inverting circuit that outputs an odd output signal selected by the first selection circuit. The first selection circuit receives the first selection signal as a frequency comparison signal.

The counter value of the first up-down counter represents an inverting circuit that outputs an odd output signal selected by the first selection circuit. For this reason, since the 1st up-down counter counts according to the comparison result of the magnitude comparator, the frequency of an output clock can be adjusted easily.

In another aspect of the digital PLL circuit of the present invention, the first up-down counter is set to a counter value indicating the inverting circuit on the rear end of the odd-numbered inverting circuits before the frequency comparator starts comparing the frequency of the reference clock and the output clock. do.

For this reason, before the frequency comparator starts the frequency comparison, the feedback loop of the frequency variable circuit becomes relatively long, and the frequency of the output clock becomes the frequency of the lower side among the frequencies capable of oscillation. In addition, when the delay time of the connected stage of the inverting circuit changed by the frequency adjustment is larger than the half period of the output clock before frequency adjustment, when the odd output signal selected by the first selection circuit is switched, a glitch ( glitch is likely to occur. For this reason, by making the period of the output clock before frequency adjustment large, the possibility of glitches in an output clock according to frequency adjustment can be made low.

In another form of the digital PLL circuit of the present invention, the frequency comparator has a first adder. The first adder adds a predetermined value to the second counter value and outputs the addition result as an addition value signal. The magnitude comparator receives the addition value signal as the second counter value signal.

The second counter value recognized by the magnitude comparator is larger than the second counter value actually output from the second counter. For this reason, when the magnitude comparator determines that the first and second counter values match, the frequency of the output clock is lower than the frequency of the reference clock. As a result, when the period of the reference clock does not just divide by the delay time per stage of the inverting circuit in the delay circuit, it is possible to prevent the frequency of the output clock from vibrating along the frequency of the reference clock by adjusting the frequency. Can be. In other words, the jitter of the output clock due to the adjustment of the frequency can be reduced.

In another aspect of the digital PLL circuit of the present invention, the second reference divider divides the reference clock at a predetermined division ratio and outputs it as the second division reference clock. The phase comparator has first and second dividers. The first divider divides the reference clock at a predetermined division ratio and outputs it as the first division clock. The second divider divides the output clock at the same division ratio as the first divider and outputs the second divided clock. The phase comparator compares phases of the first and second divided clocks and outputs a comparison result as a phase comparison signal. The second control circuit has a down counter. The down counter synchronizes with the second division reference clock and outputs the counted down count value according to the phase comparison signal as a second selection signal. The second selection signal represents an inverting circuit that outputs an odd output signal selected by the second selection circuit. The down counter is set to a counter value indicating the inverting circuit on the rear end of the odd-numbered inverting circuits before the phase comparator starts the phase comparison between the reference clock and the output clock. The second selection circuit receives the second selection signal as a phase comparison signal.

The phase comparator may lower the frequency of phase comparison to compare the phases of the first and second divided clocks. For this reason, jitter of the output clock according to phase adjustment can be reduced. In addition, the counter value of the down counter represents the inversion circuit which outputs the odd output signal which the 2nd selection circuit selects. For this reason, the phase of the output clock can be easily adjusted by counting down the count according to the comparison result of the phase comparator.

In addition, by making the period of the output clock larger than the period of the reference clock, after the phase of the output clock coincides with the phase of the reference clock, the phase of the output clock always shifts in the delay direction from the phase of the reference clock. For this reason, in the phase adjustment of the output clock, the phase of the output clock can be advanced to match the phase of the reference clock. Since the adjustment to slow the phase of the output clock is not necessary, the phase of the output clock can be adjusted using a simple down counter that advances the phase. As a result, the circuit scale can be reduced.

In another form of the digital PLL circuit of the present invention, the frequency comparator has a first subtractor. The first subtractor subtracts a predetermined value from the first counter value, and outputs the subtraction result as a subtracted value signal. The magnitude comparator receives the subtracted value signal as a first counter value signal.

The first counter value recognized by the magnitude comparator is smaller than the first counter value actually output from the first counter. For this reason, when the magnitude comparator determines that the first and second counter values match, the frequency of the output clock is lower than the frequency of the reference clock. As a result, when the period of the reference clock does not just divide by the delay time per stage of the inverting circuit in the delay circuit, it is possible to prevent the frequency of the output clock from vibrating along the frequency of the reference clock by adjusting the frequency. Can be. In other words, the jitter of the output clock due to the adjustment of the frequency can be reduced.

In another aspect of the digital PLL circuit of the present invention, the first reference divider divides the reference clock at a predetermined division ratio and outputs it as the first division reference clock. The frequency comparator has a first counter, a second counter, and a second subtractor. The first counter counts the reference clock and outputs the counted value as the first counter value signal. The second counter counts the output clock and outputs the counted value as the second counter value signal. The first and second counters are reset in response to the first divided reference clock. The second subtractor outputs a value obtained by obtaining the difference between the first counter value of the first counter indicated by the first counter value signal and the second counter value of the second counter indicated by the second counter value signal as a frequency comparison signal.

Therefore, the frequency difference between the reference clock and the output clock can be easily detected by simply counting the number of clocks of the reference clock and the output clock and calculating the difference between the counted values.

In another aspect of the digital PLL circuit of the present invention, the second subtractor outputs a frequency coincidence signal when the first and second counter values coincide. The phase comparator compares the phases of the reference clock and the output clock during the output of the frequency coincidence signal.

The phase of the output clock is adjusted after the frequency of the output clock matches the frequency of the reference clock. Since the frequency and phase of the output clock are adjusted independently of each other, one adjustment does not affect the other. For this reason, the frequency and phase of an output clock can be adjusted stably, respectively. As a result, the frequency and phase of the output clock can be easily matched to the frequency and phase of the reference clock, respectively, in a short time.

In another aspect of the digital PLL circuit of the present invention, the second subtractor outputs a frequency coincidence signal whenever the first and second counter values coincide. The first reference divider divides the reference clock at a predetermined division ratio and outputs it as the first division reference clock. The first reference divider operates as a variable divider which sequentially increases the period of the first divided reference clock in response to the frequency coincidence signal.

For this reason, each time the first and second counter values coincide, the period in which the first and second counters are reset becomes large. Since the increment of the first and second counter values increases each time the first and second counter values coincide, the accuracy of frequency comparison can be improved. By changing the period (count period) for comparing the frequencies of the reference clock and the output clock sequentially from short to long periods of time, the accuracy of frequency comparison can be improved step by step. As a result, the frequency of the output clock can be matched to the frequency of the reference clock in a short time as compared with the case where the precision of the frequency comparison is not changed.

In another form of the digital PLL circuit of the present invention, the first control circuit has a second adder and a memory circuit. The second adder receives the frequency comparison signal and the first selection signal output from the second subtractor, adds the value indicated by the frequency comparison signal and the value indicated by the first selection signal, and outputs the addition result as an update value signal. The memory circuit receives the update value signal in synchronization with the first division reference clock and outputs the received value as the first selection signal. The first selection signal represents an inverting circuit that outputs an odd output signal selected by the first selection circuit. The first selection circuit receives the first selection signal as a frequency comparison signal.

The value of the memory circuit represents an inverting circuit that outputs an odd output signal selected by the first selection circuit. For this reason, the value of a memory circuit is updated, and the frequency of an output clock can be adjusted easily. In addition, since the value of the memory circuit is updated to the value obtained by adding the difference between the first and second counter values to the value of the memory circuit, the odd output signal selected by the first selection circuit is changed not by one stage but by several stages at a time. Can be. As a result, the frequency of the output clock can be matched to the frequency of the reference clock in a short time.

In one aspect of the digital PLL circuit of the present invention, the memory circuit is set to a value representing the inverting circuit on the rear end of the odd-numbered inverting circuits before the frequency comparator starts frequency comparison between the reference clock and the output clock.

For this reason, before the frequency comparator starts the frequency comparison, the feedback loop of the frequency variable circuit becomes relatively long, and the frequency of the output clock becomes the frequency of the lower side among the frequencies capable of oscillation. In addition, when the delay time of the connected stage of the inverting circuit changed by the frequency adjustment is larger than the half period of the output clock before frequency adjustment, when the odd output signal selected by the first selection circuit is switched, a glitch appears in the output clock. Easy to occur For this reason, by making the period of the output clock before frequency adjustment large, the possibility of glitches in an output clock according to frequency adjustment can be made low.

In one form of the digital PLL circuit of the invention, the frequency comparator has a first adder. The first adder adds a predetermined value to the second counter value and outputs the addition result as an addition value signal. The second subtractor receives the addition value signal as the second counter value signal.

The second counter value recognized by the second subtractor is larger than the second counter value actually output from the second counter. For this reason, when the second subtractor determines that the first and second counter values match, the frequency of the output clock is lower than the frequency of the reference clock. As a result, when the period of the reference clock does not drop just as much as the delay time per stage of the inverting circuit in the delay circuit, the frequency of the output clock is prevented from vibrating along the frequency of the reference clock by adjusting the frequency. can do. In other words, the jitter of the output clock due to the adjustment of the frequency can be reduced.

In one form of the digital PLL circuit of the invention, the frequency comparator has a first subtractor. The first subtractor subtracts a predetermined value from the first counter value and outputs the subtraction result as a subtracted value signal. The second subtractor receives the subtracted value signal as a first counter value signal.

The first counter value recognized by the second subtractor is smaller than the first counter value actually output from the first counter. For this reason, when the second subtractor determines that the first and second counter values match, the frequency of the output clock is lower than the frequency of the reference clock. As a result, when the period of the reference clock does not just divide by the delay time per stage of the inverting circuit in the delay circuit, it is possible to prevent the frequency of the output clock from vibrating along the frequency of the reference clock by adjusting the frequency. Can be. In other words, the jitter of the output clock due to the adjustment of the frequency can be reduced.

In one aspect of the digital PLL circuit of the present invention, the second reference divider divides the reference clock at a predetermined division ratio and outputs it as the second division reference clock. The second control circuit has a second updown counter. The second up-down counter outputs, as a second selection signal, a value counted up or down in accordance with the phase comparison signal in synchronization with the second division reference clock. The second selection signal represents an inverting circuit that outputs an odd output signal selected by the second selection circuit. The second selection circuit receives the second selection signal as a phase comparison signal.

The counter value of the second up-down counter represents an inverting circuit that outputs an odd output signal selected by the second selection circuit. For this reason, the phase of the output clock can be easily adjusted by counting the second up-down counter according to the comparison result of the phase comparator.

In one form of the digital PLL circuit of the present invention, the third control circuit may have changed from the minimum value to the maximum value when the counter value of the second up-down counter indicated by the second selection signal is changed from the maximum value to the minimum value by the count operation. Outputs a third selection signal whose logic level is reversed. The third selection circuit alternately outputs an inverted output clock and an output clock in which the output clock is inverted in response to the transition edge of the third selection signal. The frequency comparator and the phase comparator receive the clock output from the third selection circuit as the output clock.

The phase of the output clock is inverted in response to the transition edge of the third select signal. Therefore, by inverting the phase of the output clock when the counter value of the second up-down counter changes from the maximum value to the minimum value, the phase of the output clock can be delayed later than the phase corresponding to the maximum value of the counter value of the second up-down counter. . In addition, when the counter value of the second up-down counter is changed from the minimum value to the maximum value, the phase of the output clock can be reversed to advance the phase of the output clock more than the phase corresponding to the minimum value of the counter value of the second up-down counter. As a result, the phase of the output clock can be adjusted more extensively.

In one aspect of the digital PLL circuit of the present invention, the first control circuit outputs a first selection signal composed of a plurality of bits representing an inverting circuit which outputs an odd output signal selected by the first selection circuit in accordance with the frequency comparison signal. The second control circuit outputs a second selection signal composed of a plurality of bits representing an inverting circuit which outputs an odd output signal selected by the second selection circuit in accordance with the phase comparison signal. The first transition detector outputs the first transition signal during the transition of the first selection signal. The second transition detector outputs a second transition signal during the transition of the second selection signal. The first prohibition circuit is disposed between the output of the first selection circuit and the input of the delay circuit to prohibit the output of the first selection circuit from propagating to the delay circuit during the output of the first transition signal. The second inhibiting circuit is disposed between the output of the second selecting circuit and the inputs of the frequency comparator and the phase comparator to prevent the output of the second selecting circuit from propagating to the frequency comparator and the phase comparator during the output of the second transition signal. The first selection circuit receives the first selection signal as a frequency comparison signal. The second selection circuit receives the second selection signal as a phase comparison signal.

Since the first prohibition circuit prohibits the output of the first selection circuit from propagating to the delay circuit during the transition of the first selection signal, it is possible to prevent the output clock from occurring due to the transition of the first selection signal. Since the second prohibition circuit prohibits the output of the second selection circuit from propagating to the frequency comparator and the phase comparator during the transition of the second selection signal, it is possible to prevent the output clock from being disturbed by the transition of the second selection signal. Can be.

In one aspect of the digital PLL circuit of the present invention, the third reference divider divides the reference clock at a predetermined division ratio and outputs it as the third division reference clock. The first output divider divides the output clock output from the second selection circuit at a predetermined division ratio and outputs it as the first division output clock. The frequency comparator and the phase comparator receive the third divided reference clock as a reference clock and the first divided output clock as an output clock.

For example, if the division ratios of the third reference divider and the first output divider are 1 / K and 1 / L, respectively, the output clock can be divided to an arbitrary value when L <K is satisfied. If L> K holds, the output clock can be multiplied to any value. In addition, when L = K, even when the frequency of the reference clock is higher than the upper limit of the comparable frequencies of the frequency comparator and the phase comparator, the frequency and phase of the output clock can be matched to the frequency and phase of the reference clock, respectively. .

In one aspect of the digital PLL circuit of the present invention, the second output divider divides the output clock output from the second selection circuit at a predetermined division ratio and outputs it as the second division output clock. The third output divider divides the second divided output clock at a predetermined division ratio and outputs it as an output clock. The first output divider receives the second divided output clock as an output clock.

As a result, since the frequency divider for adjusting the frequency of the output clock increases, for example, when the division ratios of the second and third output dividers are 1 / M and 1 / N, respectively, L · M <K · N If so, the output clock can be divided with higher precision. When L · M> K · N holds, the output clock can be multiplied with higher precision. Also, when L · M = K · N holds, even when the frequency of the reference clock is higher than the upper limit of the comparable frequencies of the frequency comparator and the phase comparator, the frequency and phase of the output clock are respectively set to the frequency and phase of the reference clock. Can match.

In one form of the digital PLL circuit of the present invention, the frequency comparator compares the frequencies of the reference clock and the output clock generated in accordance with the reference clock to output a frequency comparison signal indicating the comparison result. The frequency variable circuit has a delay circuit and a first selection circuit. The delay circuit has a plurality of inverting circuits connected in series. The first selection circuit selects any of the odd output signals output from the odd-numbered inverting circuit in accordance with the frequency comparison signal and feeds them back to the input of the delay circuit as a feedback signal. For this reason, the frequency of a feedback signal can be changed according to the comparison result of a frequency comparator. The phase comparator compares the phases of the reference clock and the output clock and outputs a phase comparison signal indicating the comparison result. The second up-down counter, in synchronization with the reference clock, outputs a value counted up or down in accordance with the phase comparison signal as a second selection signal. The third control circuit receives a third selection signal in which the logic level is inverted when the counter value of the second up-down counter indicated by the second selection signal is changed from the maximum value to the minimum value by the counting operation and from the minimum value to the maximum value. Output The fourth selection circuit receives the even output signal and the odd output signal output from the even-numbered inverting circuit, and selects any of the odd output signals in accordance with the second selection signal during the period when the third selection signal is at the first logic level. The output signal is output as an output clock, and during the period when the third select signal is the second logic level, any of the even output signals is selected according to the second select signal and output as the output clock. For this reason, the phase of an output clock can be changed according to the comparison result of a phase comparator.

The frequency variable circuit functions as a variable oscillator for changing the frequency of the output clock by adjusting the number of stages of the inverting circuits forming the feedback loop. For this reason, it is not necessary to separately form a circuit for changing the frequency of the oscillator and the clock output from the oscillator, and the circuit scale can be reduced. Furthermore, since the delay circuit is commonly used for both frequency adjustment and phase adjustment of the output clock, the circuit scale can be reduced.

The phase of the output clock is inverted in response to the transition edge of the third select signal. Therefore, by inverting the phase of the output clock when the counter value of the second up-down counter changes from the maximum value to the minimum value, the phase of the output clock can be delayed later than the phase corresponding to the maximum value of the counter value of the second up-down counter. . In addition, when the counter value of the second up-down counter is changed from the minimum value to the maximum value, the phase of the output clock can be reversed to advance the phase of the output clock more than the phase corresponding to the minimum value of the counter value of the second up-down counter. As a result, the phase of the output clock can be adjusted more extensively.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described using drawing. In the figure, the signal shown by the thick line consists of several bits.

2 shows a first embodiment of the digital PLL circuit of the present invention.

The digital PLL circuit 100 includes a frequency comparator 110, a first control circuit 112, a ring oscillator 114 (frequency variable circuit), a phase comparator 120, a second control circuit 122, and a second selection circuit. And a first reference divider 150 and a second reference divider 152.

The frequency comparator 110 compares the frequency of the output clock CKO output from the second selection circuit 128 in synchronization with the first divided reference clock CKDB1 in accordance with the reference clock CKB and the reference clock CKB. To output the frequency comparison signals UP1 and DN1 indicating the comparison result. The frequency comparator 110 determines that the frequencies of both clocks match when the frequency difference between the reference clock CKB and the output clock CKO is within a predetermined range, and outputs a frequency coincidence signal MATCH.

The first control circuit 112 outputs a plurality of bits of the first selection signal SEL1 in synchronization with the first division reference clock CKDB1 in accordance with the frequency comparison signals UP1 and DN1. The first selection signal SEL1 indicates a buffer BUF (BUF0 to BUFn) for outputting the odd output signal ODD (ODD0 to ODMDn) selected by the first selection circuit 118. Details of the frequency comparator 110 and the first control circuit 112 will be described with reference to FIG. 3.

The ring oscillator 114 has a delay circuit 116 and a first selection circuit 118. The delay circuit 116 is configured by connecting the inverter INVF (inverting circuit) and the buffers BUF (BUF0 to BUFn) in series. Each buffer BUF is configured by connecting two inverters in series. The first selection circuit 118 selects any of the odd output signals ODD (ODD0 to ODMDn) output from the buffer BUF in accordance with the first selection signal SEL1, and serves as a delay signal RT as a feedback signal RT. It returns to the input of the inverter INVF which is the input of 116). The feedback loop is always configured by an odd number of inverter rows. As a result, the ring oscillator 114 operates as a variable oscillator for changing the frequency of the output clock CKO by adjusting the number of stages of the connection of the buffer BUF constituting the feedback loop. For this reason, it is not necessary to separately form a circuit for changing the frequency of the oscillator and the clock output from the oscillator, and the circuit scale is reduced.

The phase comparator 120 compares the phases of the reference clock CKB and the output clock CKO during the output of the frequency match signal MATCH, and outputs phase comparison signals UP2 and DN2 indicating the comparison result.

The second control circuit 122 outputs a plurality of bits of the second selection signal SEL2 in synchronization with the second division reference clock CKDB2 in accordance with the phase comparison signals UP2 and DN2. The second selection signal SEL2 represents a buffer BUF (BUF0 to BUFn) for outputting the odd output signal ODD (ODD0 to ODMDn) selected by the second selection circuit 128. Details of the phase comparator 120 and the second control circuit 122 will be described with reference to FIG. 4.

The second selection circuit 128 selects any of the odd output signals ODD (ODD0 to ODMDn) in accordance with the second selection signal SEL2 and outputs the output clock CKO. Details of the first selection circuit 118 and the second selection circuit 128 will be described with reference to FIG. 5.

The first reference divider 150 divides the reference clock CKB at a predetermined division ratio and outputs it as the first division reference clock CKDB1.

The second reference divider 152 divides the reference clock CKB at a predetermined division ratio and outputs it as the second division reference clock CKDB2.

3 shows the details of the frequency comparator 110 and the first control circuit 112 in the first embodiment.

The frequency comparator 110 has a first counter C1, a second counter C2, a reset generator RSTG, and a magnitude comparator MC.

The first counter C1 counts the number of clocks of the reference clock CKB and outputs the counted value as a plurality of first counter value signals CNT1.

The second counter C2 counts the number of clocks of the output clock CKO and outputs the counted value as a plurality of bits of the second counter value signal CNT2.

The reset generator RSTG detects the rising edge of the first divided reference clock CKDB1 and outputs a reset signal RST which is a pulse signal. The first counter C1 and the second counter C2 are reset in response to the reset signal RST. For example, the first counter C1 and the second counter C2 reset all bits to "0" in response to the reset signal RST.

The comparator MC has a first counter value of the first counter C1 indicated by the first counter value signal CNT1 and a second counter value of the second counter C2 indicated by the second counter value signal CNT2. Are compared and the comparison results are output as the frequency comparison signals UP1 and DN1. For example, when the first counter value is smaller than the second counter value, the frequency comparison signals UP1 and DN1 are fixed to "logic 1" and "logic 0", respectively. When the first counter value is larger than the second counter value, the frequency comparison signals UP1 and DN1 are fixed to "logic 0" and "logic 1", respectively. When the first and second counter values coincide, the frequency comparison signals UP1 and DN1 are fixed to "logic 0" together.

The magnitude comparator MC outputs a frequency coincidence signal MATCH when the first and second counter values coincide. The frequency coincidence signal MATCH is generated by synchronizing a negative signal of the logical sum of the frequency comparison signals UP1 and DN1 with, for example, the rising edge of the first divided reference clock CKDB1. The frequency match signal MATCH is fixed to " logic 1 " when the first and second counter values match. The frequency match signal MATCH is fixed at " logic 0 " when the first and second counter values do not match.

The first control circuit 112 has a first up-down counter UDC1. The first up-down counter UDC1 outputs a value counted up or down counted according to the frequency comparison signals UP1 and DN1 in synchronization with the first division reference clock CKDB1 as the first selection signal SEL1. . For example, when the frequency comparison signal UP1 is "logical 1," the first up-down counter UDC1 counts up in synchronization with the rising edge of the first division reference clock CKDB1. The first up-down counter UDC1 counts down in synchronization with the rising edge of the first divided reference clock CKDB1 when the frequency comparison signal DN1 is "logical 1". The first up-down counter UDC1 does not count when the frequency comparison signals UP1 and DN1 are "logical 0" together.

Accordingly, the first selection circuit 118 switches the odd output signal ODM selected by one stage in accordance with the comparison result of the frequency comparator 110. Specifically, when the frequency of the output clock CKO is higher than the frequency of the reference clock CKB, the first up-down counter UDC1 counts up. Accordingly, the value indicated by the first selection signal SEL1 increases by one. That is, the first selection circuit 118 switches the odd-numbered output signal ODD to be selected one step in the rear-end direction (the left direction of the delay circuit 116 in FIG. 2). When the frequency of the output clock CKO is lower than the frequency of the reference clock CKB, the first up-down counter UDC1 counts down. As a result, the value indicated by the first selection signal SEL1 decreases by one. That is, the first selection circuit 118 switches the odd output signal ODM selected by one step in the front end direction.

In addition, the first up-down counter UDC1 may be configured before the frequency comparator 110 starts comparing the frequency of the reference clock CKB and the output clock CKO (eg, when the digital PLL circuit 100 is powered on). It is set to a value corresponding to the buffer BUFn of the last stage shown in 2, and outputs in advance the first selection signal SEL1 indicating the buffer BUFn. That is, the first selection circuit 118 preselects the odd output signal ODNn. For this reason, the frequency of the output clock CKO is set in advance at the lowest frequency among the oscillable frequencies.

4 shows the details of the phase comparator 120 and the second control circuit 122 in the first embodiment.

The phase comparator 120 has a first divider DV1, a second divider DV2, and a phase comparison circuit PC.

The first divider DV1 divides the reference clock CKB at a predetermined division ratio and outputs it as the first division clock CKD1.

The second divider DV2 divides the output clock CKO at the same division ratio as the first divider DV1 and outputs it as the second divider clock CKD2.

The phase comparison circuit PC of the first divided clock CKD1 and the second divided clock CKD2 during the output of the frequency match signal MATCH (for example, when the frequency match signal MATCH is "logical 1"). The phases are compared and the comparison results are output as the phase comparison signals UP2 and DN2. For example, when the phase of the second divided clock CKD2 is earlier than the phase of the first divided clock CKD1, the phase comparison signals UP2 and DN2 are fixed to "logic 1" and "logic 0", respectively. When the phase of the second divided clock CKD2 is slower than the phase of the first divided clock CKD1, the phase comparison signals UP2 and DN2 are fixed to "logic 0" and "logic 1", respectively. When the phases of the first divided clock CKD1 and the second divided clock CKD2 coincide, the phase comparison signals UP2 and DN2 are fixed to "logic 0" together. Since the phase comparison circuit PC compares the phases of the first divided clock and the second divided clock, the frequency of the phase comparison decreases. For this reason, the jitter of the output clock CKO according to the phase adjustment is reduced. In addition, as the frequency of phase comparison decreases, the power consumption of the semiconductor integrated circuit on which the digital PLL circuit 100 is mounted is reduced.

The second control circuit 122 has a second up-down counter UDC2. The second up-down counter UDC2 outputs, as the second selection signal SEL2, a value that is counted up or down in accordance with the phase comparison signals UP2 and DN2 in synchronization with the second division reference clock CKDB2. . For example, when the phase comparison signal UP2 is "logic 1", the second up-down counter UDC2 counts up in synchronization with the rising edge of the second division reference clock CKDB2. The second up-down counter UDC2 counts down in synchronization with the rising edge of the second division reference clock CKDB2 when the phase comparison signal DN2 is "logical 1". The second up-down counter UDC2 does not count when the phase comparison signals UP2 and DN2 are both "logical 0".

Accordingly, the second selection circuit 128 switches the odd output signal ODM selected by one stage in accordance with the comparison result of the phase comparator 120. Specifically, when the phase of the output clock CKO is earlier than the phase of the reference clock CKB, the second up-down counter UDC2 up counts. Accordingly, the value indicated by the second selection signal SEL2 increases by one. That is, the second selection circuit 128 switches the odd output signal ODD to be selected one step in the rearward direction. When the phase of the output clock CKO is slower than the phase of the reference clock CKB, the second up-down counter UDC2 counts down. As a result, the value indicated by the second selection signal SEL2 decreases by one. That is, the second selection circuit 128 switches the selected odd output signal OMD one step in the front end direction.

5 shows an example of the first selection circuit 118 and the second selection circuit 128 in the first embodiment.

The first selection circuit 118 includes a first decoder DEC1, an AND circuit ANDF (ANDF0 to ANDFn), and an OR circuit ORF.

The first decoder DEC1 decodes the first select signal SEL1 output from the first control circuit 112 shown in FIG. 2 and outputs n-bit decode signals FD (FD0 to FDn). For example, in the decode signal FD, the bit corresponding to the value indicated by the first selection signal SEL1 is fixed to " logic 1 ". In the decode signal FD, bits other than the bits corresponding to the values indicated by the first selection signal SEL1 are fixed to " logical 0 ".

Each AND circuit ANDF outputs an operation result by performing an AND operation on each bit corresponding to the decode signal FD and the odd output signal ODM. The OR circuit ORF performs an OR on each of the AND products output from the AND circuit ANDF, and outputs an operation result as a feedback signal RT. Accordingly, the first selection circuit 118 switches the odd output signal ODM selected in accordance with the first selection signal SEL1. For this reason, the number of stages of the buffer BUF included in the feedback loop in the ring oscillator 114 is controlled in accordance with the first selection signal SEL1. That is, the frequency of the feedback signal RT is adjusted according to the comparison result of the frequency comparator 110.

The second selection circuit 128 has a second decoder DEC2, an AND circuit ANDP0 to ANDPn, and an OR circuit ORP.

The second decoder DEC2 decodes the second select signal SEL2 output from the second control circuit 122 and outputs n-bit decode signals PD (PD0 to PDn). For example, in the decode signal PD, the bit corresponding to the value indicated by the second selection signal SEL2 is fixed to "logic 1". In the decode signal PD, bits other than the bit corresponding to the value indicated by the second selection signal SEL2 are fixed to "logic 0".

Each AND circuit ANDP outputs an operation result by performing an AND operation on each corresponding bit of the decode signal PD and the odd output signal ODM. The OR circuit ORP performs an OR on each of the AND products output from the AND circuit ANDP, and outputs an operation result as the output clock CKO. Accordingly, the second selection circuit 128 switches the odd output signal ODM selected in accordance with the second selection signal SEL2. For this reason, the number of stages of the buffer BUF included in the path from the output of the first selection circuit 118 to the input of the second selection circuit 128 is controlled in accordance with the second selection signal SEL2. That is, the phase of the output clock CKO is adjusted according to the comparison result of the phase comparator 120. In addition, since the buffer BUF not included in the feedback loop in the ring oscillator 114 is also used to adjust the phase of the output clock CKO, the buffer BUF in the delay circuit 116 can be effectively used. It is available.

With the above configuration, since the delay circuit 116 is commonly used for both the frequency adjustment and the phase adjustment of the output clock CKO, the circuit scale of the digital PLL circuit 100 is reduced.

Here, the operation of the first embodiment will be described using specific examples.

For example, the frequencies of the reference clock CKB and the output clock CKO are 100 MHz (period: 10 ns) and 50 MHz (period: 20 ns), respectively. The division ratio of the first reference frequency divider 150 is set to 1/16. That is, the period in which the frequencies of the reference clock CKB and the output clock CKO are compared is 160 ns. The division ratios of the second reference divider 152, the first divider DV1, and the second divider DV2 are set to 1/16 together. That is, the period in which the phases of the reference clock CKB and the output clock CKO are compared is 160 ns. The delay time per stage of the buffer BUF is set to 0.1 ns. It is assumed that the first selection circuit 118 selects the x-th odd output signal ODDx. It is assumed that the second selection circuit 128 selects the y-th odd output signal ODY.

First, in order to match the frequency of the output clock CKO with the frequency of the reference clock CKB, the frequency adjustment of the output clock CKO is performed.

In the frequency comparator 110, the first counter C1 and the second counter C2 reset all bits to " 0 " in response to the reset signal RST. After that, the first counter C1 counts the reference clock CKB 16 times until it is reset again. For this reason, the first counter value is counted up to "16". In addition, the second counter C2 counts the output clock CKO eight times until it is reset again. The second counter value is counted up to " 8. " At this time, the magnitude comparator MC determines that the first counter value is larger than the second counter value, and fixes the frequency output signals UP1 and DN1 to "logic 0" and "logic 1", respectively. In addition, since the first and second counter values do not coincide, the frequency coincidence signal MATCH is fixed to " logic 0 ".

Since the frequency comparison signal DN1 is " logic 1 ", the first up-down counter UDC1 counts down in synchronization with the rising edge of the first division reference clock CKDB1. For this reason, the counter value of the 1st up-down counter UDC1 changes from x to x-1. That is, the value indicated by the first selection signal SEL1 is changed from x to x-1.

The first selection circuit 118 converts the selected odd output signal ODD from the odd output signal ODDx0 to the odd output signal ODDx-1, whereby the period of the output clock CKO is reduced to 19.8 ns. In other words, the frequency of the output clock CKO is increased to about 50.51 MHz.

Since the periodic difference (frequency difference) between the reference clock CKB and the output clock CKO is 10 ns, the above-described frequency adjustment is performed 50 times, so that the first and second counter values coincide. For this reason, the frequency of the output clock CKO matches the frequency of the reference clock CKB. In other words, the frequency of the output clock CKO is locked. At this time, the frequency coincidence signal MATCH is fixed to " logic 1 ".

After the frequency of the output clock CKO coincides with the frequency of the reference clock CKB, the phase adjustment of the output clock CKO is performed to match the phase of the output clock CKO with the phase of the reference clock CKB. do. In addition, it is assumed here that the phase of the output clock CKO is later than the phase of the reference clock CKB when the frequency of the output clock CKO coincides with the frequency of the reference clock CKB.

In the phase comparator 120, the phase comparator circuit PC determines that the phase of the second divided clock CKD2 is later than the phase of the first divided clock CKD1, and respectively supplies the phase comparison signals UP2 and DN2. Fix to "Logic 0" and "Logic 1".

The second up-down counter UDC2 counts down in synchronization with the rising edge of the second division reference clock CKDB2 because the phase comparison signal DN2 is " logic ". For this reason, the counter value of the second up-down counter UDC2 is changed from y to y-1. That is, the value indicated by the second selection signal SEL2 is changed from y to y-1.

The second selection circuit 128 converts the selected odd output signal ODD from the odd output signal ODDy to the odd output signal ODDy-1. As a result, the phase of the output clock CKO becomes 0.1 ns faster. As the phase of the output clock CKO advances by 0.1 ns, the phase difference between the reference clock CKB and the output clock CKO becomes 0.1 ns smaller.

Since the frequency of the reference clock CKB is 100 MHz, the phase difference between the reference clock CKB and the output clock CKO is 10 ns (one period) at most. For this reason, even if the above phase adjustment is performed at most 100 times, the phase of the output clock CKO coincides with the phase of the reference clock CKB.

On the other hand, frequency adjustment is continued even after the frequency of the output clock CKO matches the frequency of the reference clock CKB (including during phase adjustment). For this reason, when the frequency of the output clock CKO is different from the frequency of the reference clock CKB, the frequency adjustment of the output clock CKO as described above is performed again. At this time, the frequency coincidence signal MATCH changes from " logic 1 " to " logical 0 " In addition, phase adjustment is continued even after the phase of the output clock CKO matches the phase of the reference clock CKB. For this reason, when the phase of the output clock CKO is displaced with respect to the phase of the reference clock CKB, the phase adjustment of the output clock CKO as described above is performed again.

As described above, in the first embodiment, the following effects can be obtained.

The ring oscillator 114 functions as a variable oscillator for changing the frequency of the output clock CKO by adjusting the number of stages of the buffer BUF forming the feedback loop. The delay circuit 116 is commonly used for both frequency adjustment and phase adjustment of the output clock CKO. For this reason, the circuit scale can be reduced.

The phase of the output clock CKO is adjusted after the frequency of the output clock CKO matches the frequency of the reference clock CKB. Since the frequency and phase of the output clock CKO are adjusted independently of each other, one adjustment does not affect the other adjustment. For this reason, the frequency and phase of the output clock CKO can be adjusted stably, respectively. As a result, the frequency and phase of the output clock CKO can be easily matched to the frequency and phase of the reference clock CKB in a short time, respectively.

Since the frequency of the output clock CKO is preset to the lowest frequency among the oscillable frequencies, the period of the output clock CKO before the frequency adjustment can be increased. In addition, when the delay time of the connection stage of the buffer BUF changed by the frequency adjustment is larger than the half period of the output clock CKO before the frequency adjustment, the odd output signal ODM selected by the first selection circuit 118 is selected. When is switched, glitches are likely to occur in the output clock CKO. For this reason, by making the period of the output clock CKO before frequency adjustment large, the possibility of glitches in the output clock CKO according to frequency adjustment can be made low.

Since the phase comparator 120 compares the phases of the first divided clock CKD1 and the second divided clock CKD2, the frequency of the phase comparison may be lowered. For this reason, the jitter of the output clock CKO which arises by adjusting a phase can be reduced. In addition, as the frequency of phase comparison decreases, the power consumption of the semiconductor integrated circuit on which the digital PLL circuit 100 is mounted can be reduced.

Fig. 6 shows a second embodiment of the digital PLL circuit of the present invention. The same elements as those described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The digital PLL circuit 200 has a frequency comparator 210 and a first control circuit 212 instead of the frequency comparator 110 and the first control circuit 112 of the first embodiment. The rest of the configuration is the same as in the first embodiment.

The frequency comparator 210 compares the frequency of the output clock CKO output from the second selection circuit 128 in synchronization with the first divided reference clock CKDB1 according to the reference clock CKB and the reference clock CKB. A frequency comparison signal DIFF of a plurality of bits indicating the comparison result is output. The frequency comparator 210 determines that the frequencies of both clocks match when the frequency difference between the reference clock CKB and the output clock CKO is within a predetermined range, and outputs a frequency match signal MATCH.

The first control circuit 212 outputs a plurality of bits of the first selection signal SEL1 in synchronization with the first division reference clock CKDB1 in accordance with the frequency comparison signal DIFF.

7 shows the details of the frequency comparator 210 and the first control circuit 212 in the second embodiment.

The frequency comparator 210 has a second subtractor S2 instead of the magnitude comparator MC of the first embodiment. The rest of the configuration is the same as in the first embodiment.

The second subtractor S2 obtains the difference between the first and second counter values, and outputs the obtained value as the frequency comparison signal DIFF.

The second subtractor S2 outputs a frequency match signal MATCH when the first and second counter values match. The frequency match signal MATCH is generated by synchronizing a negative signal of the logical sum of all bits of the frequency comparison signal DIFF with, for example, the rising edge of the first divided reference clock CKDB1. As in the first embodiment, the frequency coincidence signal MATCH is fixed to "logic 1" when the first and second counter values coincide. The frequency match signal MATCH is fixed to " logic 0 " when the first and second counter values do not match.

The first control circuit 212 has a second adder A2 and a register REG (memory circuit).

The second adder A2 receives the frequency comparison signal DIFF and the first selection signal SEL1, adds the value indicated by the frequency comparison signal DIFF to the value indicated by the first selection signal SEL1, and adds the result. Is output as the update value signal RN.

The register REG receives the update value signal RN and outputs the received value as the first selection signal SEL1 in synchronization with the first division reference clock CKDB1. Accordingly, in the first selection circuit 118 shown in FIG. 5, the odd output signal ODD to be selected is switched several times at a time according to the comparison result of the frequency comparator 210.

In addition, the register REG is set to a value corresponding to the buffer BUFn of the last stage before the frequency comparator 210 starts frequency comparison between the reference clock CKB and the output clock CKO, and thus the buffer BUFn. The first selection signal SEL1 indicating) is output in advance. That is, the first selection circuit 118 preselects the odd output signal ODNn. For this reason, the frequency of the output clock CKO is preset to the lowest frequency among the oscillable frequencies.

Here, the operation of the second embodiment will be briefly described using specific examples.

For example, the frequencies of the reference clock CKB and the output clock CKO are 100 MHz (period: 10 ns) and 50 MHz (period: 20 ns), respectively. The division ratio of the first reference frequency divider 150 is set to 1/16. That is, the period in which the frequencies of the reference clock CKB and the output clock CKO are compared is 160 ns. The delay time per stage of the buffer BUF is set to 0.1 ns. It is assumed that the first selection circuit 118 selects the x-th odd output signal ODDx.

First, in order to match the frequency of the output clock CKO with the frequency of the reference clock CKB, the frequency adjustment of the output clock CKO is performed.

Similar to the first embodiment, in the frequency comparator 210, the first counter C1 and the second counter C2 are reset to all bits in response to the reset signal RST. After that, the first counter C1 counts the reference clock CKB 16 times until it is reset again. For this reason, the first counter value is counted up to "16". In addition, the second counter C2 counts the output clock CKO eight times until it is reset again. For this reason, the second counter value is counted up to " 8. " At this time, the second subtractor S2 subtracts the first counter value from the second counter value, and outputs a frequency comparison signal DIFF corresponding to the subtraction result (-8). In addition, since the first and second counter values do not coincide, the frequency coincidence signal MATCH is fixed to " logic 0 ".

In the first control circuit 212, the second adder A2 adds the value -8 indicated by the frequency comparison signal DIFF to the value x indicated by the first selection signal SEL1, and adds the result. The update value signal RN corresponding to (x-8) is output. The register REG receives the update value signal RN in synchronization with the first divided reference clock CKDB1. That is, the value indicated by the first selection signal SEL1 is changed from x to x-8.

The first selection circuit 118 converts the selected odd output signal ODD from the odd output signal ODDx to the odd output signal ODDx-8. As a result, the period of the output clock CKO is reduced to 18.4 ns. In other words, the frequency of the output clock CKO is increased to about 54.35 MHz.

By repeating the above-described frequency adjustment, the first and second counter values coincide. For this reason, the frequency of the output clock CKO matches the frequency of the reference clock CKB. In other words, the frequency of the output clock CKO is locked. At this time, the frequency coincidence signal MATCH is fixed to " logic 1 ".

After the frequency of the output clock CKO coincides with the frequency of the reference clock CKB, in order to match the phase of the output clock CKO with the phase of the reference clock CKB, the output clock CKO is similar to that of the first embodiment. Phase adjustment is performed.

On the other hand, similarly to the first embodiment, the frequency adjustment is continuously performed even after the frequency of the output clock CKO coincides with the frequency of the reference clock CKB (including phase adjustment). For this reason, when the frequency of the output clock CKO is different from the frequency of the reference clock CKB, the frequency adjustment of the output clock CKO as described above is performed again. At this time, the frequency coincidence signal MTACH is changed from "logic 1" to "logic 0".

As described above, also in the second embodiment, the same effects as in the first embodiment can be obtained. In addition, since the value of the register REG is updated to a value obtained by adding a difference between the first and second counter values to the value of the register REG, the odd output signal ODD selected by the first selection circuit 118. You can change the number of steps at once instead of just one. As a result, the frequency of the output clock CKO can be matched for a short time by the frequency of the reference clock CKB.

Fig. 8 shows a third embodiment of the digital PLL circuit of the present invention. The same elements as those described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The digital PLL circuit 300 has a variable divider 350 (first reference divider) instead of the first reference divider 150 of the first embodiment. The rest of the configuration is the same as in the first embodiment.

Similar to the first reference divider 150 of the first embodiment, the variable divider 350 divides the reference clock CKB at a predetermined division ratio and outputs it as the first division reference clock CKDB1. In addition, the variable divider 350 sequentially increases the period of the first divided reference clock CKDB1 for each reception of the frequency match signal MATCH (high level). For example, the variable frequency divider 350 synchronizes the rising edges of the frequency coincidence signal MATCH with the division ratios of 1/4, 1/8, 1/16,... To change sequentially.

In the initial stage of frequency adjustment of the output clock CKO, since the frequency difference between the reference clock CKB and the output clock CKO is large, the discrepancy between the first and second counter values in the frequency comparator 110 is short ( A small number of clocks can be detected. On the other hand, when the frequency difference between the reference clock CKB and the output clock CKO decreases due to frequency adjustment, it takes a long time (a large number of clocks) to detect a mismatch between the first and second counter values. For this reason, the accuracy of frequency comparison is improved step by step by sequentially changing the period (count period) for comparing the frequencies of the reference clock CKB and the output clock CKO from short to long periods. By lowering the precision of the frequency comparison in the initial stage, the frequency of the output clock CKO coincides with the frequency of the reference clock CKB in a short time as compared with the case where the precision of the frequency comparison is not changed as in the first embodiment. do.

As described above, also in the third embodiment, the same effects as in the first embodiment can be obtained. In addition, by changing the period for comparing the frequencies of the reference clock CKB and the output clock CKO sequentially from short to long periods of time, the accuracy of frequency comparison can be improved step by step. For this reason, the frequency of the output clock CKO can match the frequency of the reference clock CKB in a short time.

Fig. 9 shows a fourth embodiment of the digital PLL circuit of the invention. The same elements as those described in the first, second and third embodiments are designated by the same reference numerals and detailed description thereof will be omitted.

The digital PLL circuit 400 has a variable divider 350 (first reference divider) instead of the first reference divider 150 of the second embodiment. The rest of the configuration is the same as in the second embodiment.

As mentioned above, also in 4th Embodiment, the effect similar to 1st, 2nd and 3rd Embodiment can be acquired.

Fig. 10 shows a fifth embodiment of the digital PLL circuit of the invention. The same elements as those described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The digital PLL circuit 500 is configured by adding an inverter INVP, a third control circuit 532, and a third selection circuit 538 to the first embodiment. The rest of the configuration is the same as in the first embodiment.

The third control circuit 532 is configured when the counter value of the second up-down counter UDC2 (FIG. 4) indicated by the second selection signal SEL2 is changed from the maximum value to the minimum value by the count operation and from the minimum value to the maximum value. When changed, the third select signal SEL3 whose logic level is inverted is output. For example, the maximum value and minimum value of the counter value of the second up-down counter UDC2 are "n" and "0", respectively. For example, the third select signal SEL3 is fixed to "logic 0" in advance.

The third selection circuit 538 alternately outputs the inverted output clock / CKBO and the reference output clock CKBO in response to the transition edges (rising edge and falling edge) of the third selection signal SEL3. Output as The inverted output clock / CKBO is generated by inverting the reference output clock CKBO output from the second selection circuit 128 by the inverter INVP. For example, when the third select signal SEL3 is "logic 1", the third select circuit 538 outputs the reference output clock CKBO as the output clock CKO. The third selection circuit 538 outputs the inverted output clock / CKBO as the output clock CKO when the third selection signal SEL3 is "logical 0". Accordingly, the phase of the output clock CKO is inverted in synchronization with the transition edge of the third selection signal SEL3.

In the fifth embodiment, the phase of the output clock CKO is reversed by inverting the phase of the output clock CKO when the counter value of the second up-down counter UDC2 changes from the maximum value to the minimum value. Can be later than the phase corresponding to the maximum value of the counter value. In addition, when the counter value of the second up-down counter UDC2 changes from the minimum value to the maximum value, the phase of the output clock CKO is inverted so that the phase of the output clock CKO is changed to the counter value of the second up-down counter UDC2. It is faster than the phase corresponding to the minimum value of.

As described above, in the fifth embodiment, the same effects as in the first embodiment can be obtained. In addition, the phase of the output clock CKO is inverted in response to the transition edge of the third selection signal SEL3, whereby the phase of the output clock CKO can be adjusted in a wider range.

 Fig. 11 shows a sixth embodiment of the digital PLL circuit of the invention. The same elements as those described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The digital PLL circuit 600 has a frequency comparator 610 and a second control circuit 622 instead of the frequency comparator 110 and the second control circuit 122 of the first embodiment. The rest of the configuration is the same as in the first embodiment.

 12 shows the details of the frequency comparator 610 in the sixth embodiment.

The frequency comparator 610 is configured by adding a first adder A1 to the frequency comparator 110 of the first embodiment. The rest of the configuration is the same as in the first embodiment.

The first adder A1 adds a predetermined value (for example, "1") to the second counter value of the second counter C2, and outputs the addition result as a multi-bit addition value signal ADD.

The magnitude comparator MC receives the addition value signal ADD instead of the second counter value signal CNT2 indicating the second counter value. Accordingly, when the magnitude comparator MC determines that the first and second counter values match, the frequency of the output clock CKO is lower than the frequency of the reference clock CKB. Therefore, when the frequency of the output clock CKO is locked, the frequency of the output clock CKO does not become higher than the frequency of the reference clock CKB. This prevents the frequency of the output clock CKO from vibrating along the frequency of the reference clock CKB when the period of the reference clock CKB is not divided by the delay time per stage of the buffer BUF. do. As a result, the jitter of the output clock CKO due to the adjustment of the frequency is reduced.

13 shows details of the phase comparator 120 and the second control circuit 622 in the sixth embodiment.

The 2nd control circuit 622 has the down counter DC instead of the 2nd up-down counter UDC2 of 1st Embodiment. The rest of the configuration is the same as in the first embodiment.

The down counter DC outputs a value which is counted down in accordance with the phase comparison signal DN2 and counted as the second selection signal SEL2 in synchronization with the second division reference clock CKDB2. For example, when the phase comparison signal DN2 is "logic 1", the down counter DC down counts in synchronization with the rising edge of the second division reference clock CKDB2. The down counter DC does not count when the phase comparison signal DN2 is "logical 0". Accordingly, the second selection circuit 128 switches the odd-numbered output signal ODD to the front end side by one stage according to the comparison result of the phase comparator 120.

The down counter DC is the last stage before the phase comparator 120 begins to compare the phase of the reference clock CKB and the output clock CKO (eg, when the frequency match signal MATCH is "logical 0"). Is set to a value corresponding to the buffer BUFn, and the second selection signal SEL2 indicating the buffer BUFn is output in advance. That is, the second selection circuit 128 preselects the odd output signal ODNn. For this reason, the phase of the output clock CKO is preset to the slowest phase of the adjustable phases.

In the digital PLL circuit 600 having the above configuration, when the frequency of the output clock CKO is locked, the cycle of the output clock CKO is necessarily larger than the cycle of the reference clock CKB. In other words, when the frequency of the output clock CKO is locked, the phase of the output clock CKO gradually slows down for each clock period. For this reason, after the phase of the output clock CKO coincides with the phase of the reference clock CKB once, the phase of the output clock CKO is always shifted in the delay direction from the phase of the reference clock CKB. As a result, only the adjustment for advancing the phase of the output clock CKO can match the phase of the output clock CKO with the phase of the reference clock CKB. Therefore, compared with the 2nd up-down counter UDC2 (FIG. 4) of 1st Embodiment, the phase of the output clock CKO can be adjusted using the small down counter DC.

As described above, also in the sixth embodiment, the same effects as in the first embodiment can be obtained. Further, by detecting the coincidence of the frequencies while the frequency of the output clock CKO is higher than the frequency of the reference clock CKB, the jitter of the output clock CKO generated by the frequency adjustment can be reduced. In addition, when the frequency of the output clock CKO is locked, the period of the output clock CKO is necessarily larger than the period of the reference clock CKB, so that only the adjustment for advancing the phase of the output clock CKO is performed. CKO) can be matched to the phase of the reference clock CKB. For this reason, the phase of the output clock CKO can be adjusted using a smaller down counter DC. As a result, the circuit scale can be reduced.

 Fig. 14 shows a seventh embodiment of the digital PLL circuit of the invention. The same elements as those described in the first and sixth embodiments are denoted by the same reference numerals and detailed description thereof will be omitted.

The digital PLL circuit 700 has a frequency comparator 710 and a second control circuit 622 of the sixth embodiment instead of the frequency comparator 110 and the second control circuit 122 of the first embodiment. The rest of the configuration is the same as in the first embodiment.

15 shows the details of the frequency comparator 710 in the seventh embodiment.

 The frequency comparator 710 is configured by adding a first subtractor S1 to the frequency comparator 110 of the first embodiment. The rest of the configuration is the same as in the first embodiment.

 The first subtractor S1 subtracts a predetermined value (for example, "1") from the first counter value of the first counter C1, and outputs the subtraction result as a plurality of subtraction value signals SUB.

The magnitude comparator MC receives the subtraction value signal SUB instead of the first counter value signal CNT1 indicating the first counter value. Thereby, similarly to 6th Embodiment, when the magnitude comparator MC determines that the 1st and 2nd counter values match, the frequency of the output clock CKO is lower than the frequency of the reference clock CKB. Therefore, when the frequency of the output clock CKO is locked, the frequency of the output clock CKO does not become higher than the frequency of the reference clock CKB. This prevents the frequency of the output clock CKO from vibrating along the frequency of the reference clock CKB when the period of the reference clock CKB is not divided by the delay time per stage of the buffer BUF. do. As a result, the jitter of the output clock CKO due to the adjustment of the frequency is reduced.

 As described above, also in the seventh embodiment, the same effects as in the first and sixth embodiments can be obtained.

Fig. 16 shows an eighth embodiment of the digital PLL circuit of the invention. The same elements as those described in the first, second and sixth embodiments are denoted by the same reference numerals and detailed description thereof will be omitted.

The digital PLL circuit 800 has a frequency comparator 810 and a second control circuit 622 of the sixth embodiment instead of the frequency comparator 210 and the second control circuit 122 of the second embodiment. The rest of the configuration is the same as in the second embodiment.

17 shows the details of the frequency comparator 810 in the eighth embodiment.

The frequency comparator 810 is configured by adding a first adder A1 to the frequency comparator 210 of the second embodiment. The rest of the configuration is the same as in the second embodiment.

The first adder A1 adds a predetermined value (for example, "1") to the second counter value of the second counter C2 and outputs the addition result as a multi-bit addition value signal ADD.

The second subtractor S2 receives the addition value signal ADD instead of the second counter value signal CNT2 indicating the second counter value. Accordingly, when the second subtractor S2 determines that the first and second counter values match, the frequency of the output clock CKO is lower than the frequency of the reference clock CKB. Therefore, when the frequency of the output clock CKO is locked, the frequency of the output clock CKO does not become higher than the frequency of the reference clock CKB. This prevents the frequency of the output clock CKO from vibrating along the frequency of the reference clock CKB when the period of the reference clock CKB is not divided by the delay time per stage of the buffer BUF. do. As a result, the jitter of the output clock CKO due to the adjustment of the frequency is reduced.

As described above, also in the eighth embodiment, the same effects as in the first, second, and sixth embodiments can be obtained.

Fig. 18 shows a ninth embodiment of the digital PLL circuit of the invention. The same elements as those described in the first, second and sixth embodiments are denoted by the same reference numerals and detailed description thereof will be omitted.

The digital PLL circuit 900 has a frequency comparator 910 and a second control circuit 622 of the sixth embodiment instead of the frequency comparator 210 and the second control circuit 122 of the second embodiment. The rest of the configuration is the same as in the second embodiment.

19 shows the details of the frequency comparator 910 in the ninth embodiment. The frequency comparator 910 is configured by adding a first subtractor S1 to the frequency comparator 210 of the second embodiment. The rest of the configuration is the same as in the second embodiment.

 The first subtractor S1 subtracts a predetermined value (for example, "1") from the first counter value of the first counter C1, and outputs the subtraction result as a plurality of subtraction value signals SUB.

The second subtractor S2 receives the subtracted value signal SUB instead of the first counter value signal CNT1 indicating the first counter value. Accordingly, as in the eighth embodiment, when the second subtractor S2 determines that the first and second counter values match, the frequency of the output clock CKO is lower than the frequency of the reference clock CKB. Therefore, when the frequency of the output clock CKO is locked, the frequency of the output clock CKO does not become higher than the frequency of the reference clock CKB. This prevents the frequency of the output clock CKO from vibrating along the frequency of the reference clock CKB when the period of the reference clock CKB is not divided by the delay time per stage of the buffer BUF. do. As a result, jitter in the output clock due to the adjustment of the frequency is reduced.

As mentioned above, also in 9th Embodiment, the effect similar to 1st, 2nd and 6th embodiment can be acquired.

20 shows a tenth embodiment of the digital PLL circuit of the present invention. The same elements as those described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The digital PLL circuit A00 is configured by adding a first transition detector A60, a second transition detector A62, a first prohibition circuit A70, and a second prohibition circuit A72 to the first embodiment. . The rest of the configuration is the same as in the first embodiment.

The first transition detector A60 outputs the first transition signal TR1 during the transition of the first selection signal SEL1. For example, the first transition signal TR1 detects the transition edge of each bit of the first selection signal SEL1 by the frequency adjustment, so as to " logic 1 " during the transition period of the first selection signal SEL1. It is fixed. The first transition signal TR1 is fixed at " logical 0 " in a period where the first selection signal SEL1 is determined.

The second transition detector A62 outputs the second transition signal TR2 during the transition of the second selection signal SEL2. For example, the second transition signal TR2 detects the transition edge of each bit of the second selection signal SEL2 by the phase adjustment, and the " logic 1 " during the transition period of the second selection signal SEL2. It is fixed. The second transition signal TR2 is fixed at " logical 0 " in the period in which the second selection signal SEL2 is determined.

The first prohibition circuit A70 is disposed between the output of the first selection circuit 118 and the input of the delay circuit 116, so that the output of the first transition signal TR1 (the first transition signal TR1 is " The reference feedback signal (RTB) output from the first selection circuit 118 in the period of logic 1 " is prohibited from propagating to the delay circuit 116. For example, the first prohibition circuit A70 is a through latch that latches the reference feedback signal RTB in synchronization with the rising edge of the first transition signal TR1 and outputs the feedback signal RT. Specifically, the first prohibition circuit A70 outputs the reference feedback signal RTB as the feedback signal RT in a period in which the first transition signal TR1 is "logical 0". The first prohibition circuit A70 returns the logic level of the reference feedback signal RTB latched in synchronization with the rising edge of the first transition signal TR1 during the period in which the first transition signal is "logic 1". Continue the output as Accordingly, even if a disturbance or the like occurs in the reference feedback signal RTB due to the transition of the first selection signal SEL1, it is not propagated to the feedback signal RT. As a result, trouble or the like is prevented from occurring in the output clock CKO.

The second prohibition circuit A72 is disposed between the output of the second selection circuit 128 and the inputs of the frequency comparator 110 and the phase comparator 120 to output the second transition signal TR2 (the second transition). The reference output clock CKBO output from the selection circuit 128 to the frequency comparator 110 and the phase comparator 120 is prohibited in the period where the signal TR2 is " logical ". For example, the second prohibition circuit A72 is a through latch for latching the reference output clock CKBO in synchronization with the rising edge of the second transition signal TR2 and outputting the output clock CKO. Specifically, the second prohibition circuit A72 outputs the reference output clock CKBO as the output clock CKO in the period when the second transition signal TR2 is "logical 0". The second prohibition circuit A72 outputs the logic level of the reference output clock CKBO latched in synchronization with the rising edge of the second transition signal TR2 during the period when the second transition signal is "logic 1". Continue printing as). As a result, even if a disturbance or the like occurs in the reference output clock CKBO due to the transition of the second selection signal SEL2, it is not propagated to the output clock CKO. As a result, trouble or the like is prevented from occurring in the output clock CKO.

As described above, also in the tenth embodiment, the same effects as in the first embodiment can be obtained. Furthermore, since the first prohibition circuit A70 prohibits the output of the first selection circuit 118 from propagating to the delay circuit 116 during the transition of the first selection signal SEL1, the first selection signal SEL1. The occurrence of an obstacle or the like in the output clock CKO can be prevented by the transition of. Since the second prohibition circuit A72 prohibits the output of the second selection circuit 128 from propagating to the frequency comparator 110 and the phase comparator 120 during the transition of the second selection signal SEL2, the second selection is selected. It is possible to prevent an error or the like from occurring in the output clock CKO due to the transition of the signal SEL2.

Fig. 21 shows an eleventh embodiment of the digital PLL circuit of the invention. The same elements as those described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The digital PLL circuit B00 adds a third reference divider B50, a first output divider B52, a second output divider B54, and a third output divider B56 to the first embodiment. Consists of. The rest of the configuration is the same as in the first embodiment.

 The third reference divider B50 divides the reference clock CKB at a predetermined division ratio (for example, 1 / K) and outputs it as the third division reference clock CKDB3.

The second output divider B54 divides the reference output clock CKBO output from the second selection circuit 128 at a predetermined division ratio (for example, 1 / M) and outputs it as the second division output clock CKDO2. do.

The first output divider B52 divides the second divided output clock CKDO2 at a predetermined division ratio (for example, 1 / L) and outputs it as the first divided output clock CKDO1.

 The third output divider B56 divides the second divided output clock CKDO2 at a predetermined division ratio (for example, 1 / N) and outputs it as the output clock CKO.

The frequency comparator 110, the phase comparator 120, the first reference divider 150, and the second reference divider 152 replace the reference clock CKB of the first embodiment with the third reference clock CKDB3. ). The frequency comparator 110 and the phase comparator 120 receive the first output clock CKDO1 instead of the output clock CKO of the first embodiment.

For example, the frequency of the reference clock CKB is f. In the state where the frequency of the output clock CKO is locked (when the frequency coincidence signal MATCH is "logic 1"), the frequencies of the third divided reference clock CKDB3 and the first divided output clock CKDO1 are together f. / K At this time, the reference output clock CKBO, the second output divided clock CKDO2 and the output clock CKO are respectively f · L / K, f · (L · M) / K, f · (L · M) / (K · N). For this reason, when L * M <K * N holds, the output clock CKO is divided. When L · M> K · N holds, the output clock CKO is multiplied.

As described above, also in the eleventh embodiment, the same effects as in the first embodiment can be obtained. The reference clock is formed by forming a third reference divider B50, a first output divider B52, a second output divider B54, and a third output divider B56 in the digital PLL circuit B00. The output clock CKO of a predetermined division ratio or multiplication ratio can be easily generated with respect to (CKB). Further, even when the frequency of the reference clock CKB is higher than the upper limit of the comparable frequencies of the frequency comparator 110 and the phase comparator 120, the third reference divider B50 is such that L · M = K · N holds. By configuring the first output divider B52, the second output divider B54, and the third output divider B56, the frequency and the phase of the output clock CKO are respectively determined by the frequency of the reference clock CKB and Can match the phase.

Fig. 22 shows a twelfth embodiment of the digital PLL circuit of the invention. The same elements as those described in the first and fifth embodiments are designated by the same reference numerals, and detailed description thereof will be omitted.

The digital PLL circuit C00 is configured by adding the third control circuit 532 of the fifth embodiment to the first embodiment, and instead of the second selection circuit 128 of the first embodiment, the fourth selection circuit ( C48). The rest of the configuration is the same as in the first embodiment. 22, the inverters INVE (INVE0 to INVEn) and INVO (INVO0 to INVOn) of the delay circuit 116 correspond to the buffers BUF (BUF0 to BUFn) of the first embodiment.

The fourth selection circuit C48 receives the even output signals EVEN (EVEN0 to EVENn) and the odd output signals ODD (ODD0 to ODDn) output from the even-numbered inverter INVE. The fourth selection circuit C48 is configured according to the second selection signal SEL2 in response to the second selection signal SEL2 during the period when the third selection signal SEL3 is the first logic level (for example, "logic 1"). It selects and outputs as an output clock CKO. The fourth selection circuit C48 is configured according to the second selection signal SEL2 to any of the even output signals EVEN during the period when the third selection signal SEL3 is at the second logic level (for example, "logic 0"). It selects and outputs as an output clock CKO. Accordingly, the phase of the output clock CKO is inverted in synchronization with the transition edge of the third selection signal SEL3.

 In the twelfth embodiment, the phase of the output clock CKO is inverted when the counter value of the second up-down counter UDC2 (FIG. 4) in the second control circuit 122 changes from the maximum value to the minimum value. The phase of the output clock CKO may be later than the phase corresponding to the maximum value of the counter value of the second up-down counter UDC2. Specifically, when the counter value of the second up-down counter is changed from the maximum value to the minimum value by the count operation, the fourth selection circuit C48 selects the signal for selecting the even output signal EVEN0 from the odd output signal ODNn. Low (corresponding to falling edge of third select signal SEL3) or even output signal EVENn to odd output signal ODD0 (corresponding to rising edge of third select signal SEL3).

In the twelfth embodiment, the output clock CKO is inverted by inverting the phase of the output clock CKO when the counter value of the second up-down counter UDC2 in the second control circuit 122 changes from the minimum value to the maximum value. The phase of CKO can be made earlier than the phase corresponding to the minimum value of the counter value of the second up-down counter UDC2. Specifically, when the counter value of the second up-down counter is changed from the minimum value to the maximum value by the count operation, the fourth selection circuit C48 selects the signal to select from the odd output signal ODD0 to the even output signal Even. Low (corresponding to the falling edge of the third selection signal SEL3) or even output signal EVEN0 to the odd output signal ODNn (corresponding to the rising edge of the third selection signal SEL3).

As described above, also in the twelfth embodiment, the same effects as in the first and fifth embodiments can be obtained. In addition, the fourth selection circuit C48 may output the even output signal EVEN output from the even-numbered inverter INVE as the output clock CKO. For this reason, the phase of the output clock CKO can be reversed with a simple circuit structure compared with 5th Embodiment. As a result, the circuit scale can be reduced.

In the tenth embodiment described above, an example in which the first transition detector A60 generates the first transition signal TR1 has been described. The present invention is not limited to this embodiment. For example, when the first selection signal SEL1 is pulsed, the pulsed signal may be used instead of the first transition signal TR1.

In the above-described tenth embodiment, an example in which the second transition detector A62 generates the second transition signal TR2 has been described. The present invention is not limited to this embodiment. For example, when the second selection signal SEL2 is pulsed, the pulsed signal may be used instead of the second transition signal TR2.

In the above embodiment, an example in which the first control circuit is formed separately from the first selection circuit has been described. The present invention is not limited to this embodiment. For example, the first control circuit may be formed in the first selection circuit.

 In the above embodiment, an example in which the second control circuit is formed separately from the second selection circuit has been described. The present invention is not limited to this embodiment. For example, the second control circuit may be formed in the second selection circuit.

As mentioned above, although this invention was demonstrated in detail, embodiment mentioned above and its modification are only an example of invention, and this invention is not limited to this. It is apparent that modifications can be made without departing from the invention.

In the digital PLL circuit of the present invention, the frequency variable circuit functions as a variable oscillator for changing the frequency of the output clock by adjusting the number of stages of the inverting circuit constituting the feedback loop. In addition, the delay circuit is commonly used for both frequency adjustment and phase adjustment of the output clock. For this reason, the circuit scale can be reduced.

In the digital PLL circuit of the present invention, the phase of the output clock is adjusted after the frequency of the output clock matches the frequency of the reference clock. Since the frequency and phase of the output clock are adjusted independently of each other, one adjustment does not affect the other. For this reason, the frequency and phase of an output clock can be adjusted stably, respectively. As a result, the frequency and phase of the output clock can be easily matched to the frequency and phase of the reference clock, respectively, in a short time.

In the digital PLL circuit of the present invention, before the frequency comparator starts frequency comparison, the frequency of the output clock becomes the frequency of the lower side of the oscillable frequency. In addition, when the delay time of the connected stage of the inverting circuit changed by frequency adjustment is larger than the half period of the output clock before frequency adjustment, a glitch occurs in the output clock when the odd output signal selected by the first selection circuit is switched. easy to do. For this reason, by making the period of the output clock before frequency adjustment large, the possibility of glitches in an output clock according to frequency adjustment can be made low.

In the digital PLL circuit of the present invention, since the phase comparator compares the phases of the first and second divided clocks, the frequency of phase comparison can be reduced. For this reason, the jitter of the output clock which arises by adjusting a phase can be reduced. In addition, as the frequency of phase comparison decreases, the power consumption of the semiconductor integrated circuit on which the digital PLL circuit of the present invention is mounted can be reduced.

In the digital PLL circuit of the present invention, since the value of the memory circuit is updated to the value obtained by adding the difference between the first and second counter values to the value of the memory circuit, the odd output signal selected by the first selection circuit is changed by one stage. Instead, you can change more than one step at a time. As a result, the frequency of the output clock can be matched to the frequency of the reference clock in a short time.

In the digital PLL circuit of the present invention, the accuracy of frequency comparison can be improved step by step by sequentially changing the period for comparing the frequencies of the reference clock and the output clock from short to long periods. For this reason, the frequency of the output clock can be matched to the frequency of the reference clock in a short time.

In the digital PLL circuit of the present invention, the phase of the output clock is inverted in response to the transition edge of the third selection signal, whereby the phase of the output clock can be adjusted in a wider range.

In the digital PLL circuit of the present invention, the jitter of the output clock generated by the frequency adjustment can be reduced by detecting the coincidence of the frequency while the frequency of the output clock is higher than the frequency of the reference clock. In addition, when the frequency of the output clock is locked, the cycle of the output clock is necessarily larger than the cycle of the reference clock, so that only the adjustment for advancing the phase of the output clock can match the phase of the output clock to the phase of the reference clock. For this reason, the phase of the output clock can be adjusted using a smaller down counter. As a result, the circuit scale can be reduced.

In the digital PLL circuit of the present invention, since the first prohibition circuit prohibits the output of the first selection circuit from propagating to the delay circuit during the transition of the first selection signal, the output clock is interrupted by the transition of the first selection signal. This can be prevented from occurring. Since the second prohibition circuit prohibits the output of the second selection circuit from propagating to the frequency comparator and the phase comparator during the transition of the second selection signal, it is possible to prevent the output clock from being disturbed by the transition of the second selection signal. Can be.

In the digital PLL circuit of the present invention, by forming a third reference divider, a first output divider, a second output divider, and a third output divider, an output clock having a predetermined division ratio or multiplication ratio with respect to the reference clock is provided. It can be produced easily. Further, even when the frequency of the reference clock is higher than the upper limit of comparable frequencies of the frequency comparator and the phase comparator, the frequency and phase of the output clock can be matched to the frequency and phase of the reference clock, respectively.

Claims (27)

A frequency comparator for comparing a frequency of a reference clock and an output clock generated according to the reference clock to output a frequency comparison signal indicating a comparison result; Any one of a delay circuit having a plurality of inverting circuits connected in series and an odd output signal output from an odd number inverting circuit among the inverting circuits is selected according to the frequency comparison signal and fed back to the input of the delay circuit as a feedback signal. A frequency variable circuit having a first selection circuit;  A phase comparator for comparing phases of the reference clock and the output clock to output a phase comparison signal indicating a comparison result;  And a second selection circuit for selecting any of the odd output signals in accordance with the phase comparison signal and outputting the output clock as the output clock. The method of claim 1, The frequency comparator determines that the frequencies of the reference clock and the output clock match when the frequency difference between the reference clock and the output clock is within a predetermined range, and outputs a frequency coincidence signal,  And said phase comparator compares phases of said reference clock and said output clock during the output of said frequency coincidence signal. The method of claim 1, A first reference divider which divides the reference clock at a predetermined division ratio and outputs it as a first division reference clock, The frequency comparator, A first counter that counts the reference clock and outputs the counted value as a first counter value signal and is reset in response to the first divided reference clock; A second counter that counts the output clock and outputs the counted value as a second counter value signal and is reset in response to the first divided reference clock; A magnitude for comparing the first counter value of the first counter indicated by the first counter value signal with the second counter value of the second counter indicated by the second counter value signal and outputting a comparison result as the frequency comparison signal. A digital PLL circuit comprising a comparator. The method of claim 3, The magnitude comparator outputs a frequency coincidence signal when the first and second counter values coincide, And said phase comparator compares phases of said reference clock and said output clock during the output of said frequency coincidence signal. The method of claim 3, The magnitude comparator outputs a frequency coincidence signal whenever the first and second counter values match;  And the first reference divider is a variable divider which sequentially increases the period of the first divided reference clock in response to the frequency coincidence signal. The method of claim 3, A first control circuit for outputting a first selection signal indicating an inversion circuit for outputting the odd output signal selected by the first selection circuit among the inversion circuits in accordance with the frequency comparison signal, The first control circuit includes a first up-down counter in synchronization with the first division reference clock and outputs a value counted up or down according to the frequency comparison signal as the first selection signal,  And the first selection circuit receives the first selection signal as the frequency comparison signal. The method of claim 6, And wherein the first up-down counter is set to a counter value representing an inverting circuit on a rear side of an odd number of inverting circuits before the frequency comparator starts comparing the frequency of the reference clock and the output clock. . The method of claim 3, The frequency comparator includes a first adder that adds a predetermined value to the second counter value and outputs an addition result as an added value signal,  And the magnitude comparator receives the addition value signal as the second counter value signal. The method of claim 8, A second reference divider for dividing the reference clock at a predetermined division ratio and outputting it as a second division reference clock and an odd output signal selected by the second selection circuit among the inverting circuits according to the phase comparison signal; A second control circuit for outputting a second selection signal indicative of an inverting circuit; The second selection circuit receives the second selection signal as the phase comparison signal, The phase comparator divides the reference clock at a predetermined division ratio and outputs it as a first division clock, and divides the output clock at the same division ratio as the first division period and outputs it as a second division clock. Contains 2 dividers, The phase comparator compares phases of the first and second divided clocks and outputs a comparison result as the phase comparison signal;  The second control circuit includes a down counter which outputs a counted down count value according to the phase comparison signal as the second selection signal in synchronization with the second divided reference clock;  Before the down counter and the phase comparator start phase comparison between the reference clock and the output clock, the digital PLL circuit is set to a counter value representing an inverting circuit on a rear end of an odd number of inverting circuits. The method of claim 3, The frequency comparator includes a first subtractor which subtracts a predetermined value from the first counter value and outputs a subtraction result as a subtracted value signal,  And the magnitude comparator receives the subtraction value signal as the first counter value signal. The method of claim 10, A second reference divider for dividing the reference clock at a predetermined division ratio and outputting it as a second division reference clock and an odd output signal selected by the second selection circuit among the inverting circuits according to the phase comparison signal; A second control circuit for outputting a second selection signal indicative of an inverting circuit; The second selection circuit receives the second selection signal as the phase comparison signal, The phase comparator divides the reference clock at a predetermined division ratio and outputs it as a first division clock, and divides the output clock at the same division ratio as the first division period and outputs it as a second division clock. Contains 2 dividers, The phase comparator compares phases of the first and second divided clocks and outputs a comparison result as the phase comparison signal; The second control circuit includes a down counter in synchronization with the second division reference clock and outputs a counted down count value according to the phase comparison signal as the second selection signal,  And the down counter is set to a counter value representing an inverting circuit on a rear side of an odd number of inverting circuits before the phase comparator starts to compare the phases of the reference clock and the output clock. The method of claim 1, A first reference divider which divides the reference clock at a predetermined division ratio and outputs it as a first division reference clock, The frequency comparator, A first counter that counts the reference clock and outputs the counted value as a first counter value signal and is reset in response to the first divided reference clock; A second counter that counts the output clock and outputs the counted value as a second counter value signal and is reset in response to the first divided reference clock; The difference between the first counter value of the first counter indicated by the first counter value signal and the second counter value of the second counter indicated by the second counter value signal is obtained, and the calculated value is output as the frequency comparison signal. And a second subtractor. The method of claim 12, The second subtractor outputs a frequency coincidence signal when the first and second counter values coincide, And said phase comparator compares phases of said reference clock and said output clock during the output of said frequency coincidence signal. The method of claim 12, The second subtractor outputs a frequency coincidence signal whenever the first and second counter values coincide with each other. And the first reference divider is a variable divider which sequentially increases the period of the first divided reference clock in response to the frequency coincidence signal. The method of claim 12, A first control circuit for outputting a first selection signal indicating an inversion circuit for outputting the odd output signal selected by the first selection circuit among the inversion circuits in accordance with the frequency comparison signal, The first control circuit receives the frequency comparison signal and the first selection signal, adds a value indicated by the frequency comparison signal and a value indicated by the first selection signal, and outputs an addition result as an update value signal. A second adder and a memory circuit for receiving the update value signal in synchronization with the first division reference clock and outputting the received value as the first selection signal, And the first selection circuit receives the first selection signal as the frequency comparison signal. The method of claim 15, And the memory circuit is set to a value representing an inverting circuit on a rear side of an odd number of inverting circuits before the frequency comparator starts to compare frequencies of the reference clock and the output clock. The method of claim 12, The frequency comparator includes a first adder that adds a predetermined value to the second counter value and outputs an addition result as an added value signal, And the second subtractor receives the addition value signal as the second counter value signal. The method of claim 17, A second reference divider for dividing the reference clock at a predetermined division ratio and outputting it as a second division reference clock and an odd output signal selected by the second selection circuit among the inverting circuits according to the phase comparison signal; A second control circuit for outputting a second selection signal indicative of an inverting circuit; The second selection circuit receives the second selection signal as the phase comparison signal, The phase comparator divides the reference clock at a predetermined division ratio and outputs it as a first division clock, and divides the output clock at the same division ratio as the first division period and outputs it as a second division clock. Contains 2 dividers, The phase comparator compares phases of the first and second divided clocks and outputs a comparison result as the phase comparison signal; The second control circuit includes a down counter that outputs a counted down count value according to the phase comparison signal as the second selection signal in synchronization with the second division reference clock, And the down counter is set to a counter value representing an inverting circuit on a rear side of an odd number of inverting circuits before the phase comparator starts to compare the phases of the reference clock and the output clock. The method of claim 12, The frequency comparator includes a first subtractor which subtracts a predetermined value from the first counter value and outputs a subtraction result as a subtracted value signal, And the second subtractor receives the subtracted value signal as the first counter value signal. The method of claim 19, A second reference divider for dividing the reference clock at a predetermined division ratio and outputting it as a second division reference clock and an odd output signal selected by the second selection circuit among the inverting circuits according to the phase comparison signal; A second control circuit for outputting a second selection signal indicative of an inverting circuit; The second selection circuit receives the second selection signal as the phase comparison signal, The phase comparator divides the reference clock at a predetermined division ratio and outputs it as a first division clock, and divides the output clock at the same division ratio as the first division period and outputs it as a second division clock. Contains 2 dividers, The phase comparator compares phases of the divided reference clock and the divided output clock and outputs a comparison result as the phase comparison signal, The second control circuit includes a down counter in synchronization with the second division reference clock and outputs a counted down count value according to the phase comparison signal as the second selection signal, And the down counter is set to a counter value representing an inverting circuit on a rear side of an odd number of inverting circuits before the phase comparator starts to compare the phases of the reference clock and the output clock. The method of claim 1, The phase comparator divides the reference clock at a predetermined division ratio and outputs it as a first division clock, and divides the output clock at the same division ratio as the first division period and outputs it as a second division clock. Contains 2 dividers, And the phase comparator compares phases of the first and second divided clocks and outputs a comparison result as the phase comparison signal. The method of claim 21, A second reference divider which divides the reference clock at a predetermined division ratio and outputs it as a second division reference clock; A second control circuit for outputting a second selection signal indicating an inversion circuit for outputting the odd output signal selected by the second selection circuit among the inversion circuits in accordance with the phase comparison signal; The second control circuit includes a second up-down counter in synchronization with the second division reference clock and outputs a value counted up or down according to the phase comparison signal as the second selection signal, And the second selection circuit receives the second selection signal as the phase comparison signal. The method of claim 22, Outputting a third selection signal in which the logic level is inverted when the counter value of the second up-down counter indicated by the second selection signal is changed from the maximum value to the minimum value by the count operation and from the minimum value to the maximum value; With 3 control circuits, A third selection circuit for alternately outputting the inverted output clock and the output clock inverted in response to the transition edge of the third selection signal, And the frequency comparator and the phase comparator receive a clock output from the third selection circuit as the output clock. The method of claim 1, A first control circuit for outputting a first selection signal composed of a plurality of bits representing an inversion circuit for outputting the odd output signal selected by the first selection circuit among the inversion circuits in accordance with the frequency comparison signal; A second control circuit for outputting a second selection signal composed of a plurality of bits representing an inversion circuit for outputting the odd output signal selected by the second selection circuit among the inversion circuits in accordance with the phase comparison signal; A first transition detector for outputting a first transition signal during the transition of the first selection signal; A second transition detector for outputting a second transition signal during the transition of the second selection signal; A first inhibiting circuit disposed between an output of the first selection circuit and an input of the delay circuit, the first inhibiting circuit prohibiting propagation of the output of the first selection circuit to the delay circuit during the output of the first transition signal; Disposed between the output of the second selection circuit and the inputs of the frequency comparator and the phase comparator to prohibit the output of the second selection circuit from propagating to the frequency comparator and the phase comparator during the output of the second transition signal. Including a second prohibition circuit, The first selection circuit receives the first selection signal as the frequency comparison signal, And the second selection circuit receives the second selection signal as the phase comparison signal. The method of claim 1, A third reference divider which divides the reference clock at a predetermined division ratio and outputs it as a third division reference clock; A first output divider for dividing the output clock output from the second selection circuit at a predetermined division ratio and outputting the first divided output clock as a first division output clock, And the frequency comparator and the phase comparator receive the third divided reference clock as the reference clock and the first divided output clock as the output clock. The method of claim 25, A second output divider which divides the output clock output from the second selection circuit at a predetermined division ratio and outputs it as a second division output clock; A third output divider for dividing the second divided output clock at a predetermined division ratio and outputting the second divided output clock as the output clock; And the first output divider receives the second divided output clock as the output clock.  A frequency comparator for comparing a frequency of a reference clock and an output clock generated according to the reference clock to output a frequency comparison signal indicating a comparison result; Any one of a delay circuit having a plurality of inverting circuits connected in series and an odd output signal output from an odd number inverting circuit among the inverting circuits is selected according to the frequency comparison signal and fed back to the input of the delay circuit as a feedback signal. A frequency variable circuit having a first selection circuit; A phase comparator for comparing phases of the reference clock and the output clock to output a phase comparison signal indicating a comparison result; A second up-down counter in synchronization with the reference clock and outputting a value counted up or down according to the phase comparison signal as a second selection signal; Outputting a third selection signal in which the logic level is inverted when the counter value of the second up-down counter indicated by the second selection signal is changed from the maximum value to the minimum value by the count operation and from the minimum value to the maximum value; 3 control circuits; Receives an even output signal and an odd output signal output from an even inverting circuit of the inverting circuits, and selects any of the odd output signals during the period when the third selection signal is at a first logic level. A fourth selection which selects in accordance with the second selection signal and selects any of the even output signals according to the second selection signal in a period during which the third selection signal is a second logic level. A digital PLL circuit comprising a circuit.