KR20050112396A - Semiconductor device having metal-insulator-metal capacitor and fabrication method for the same - Google Patents

Abstract

Provided are a semiconductor device including a capacitor having a MIM (metal-insulator-metal) structure, and a method of manufacturing the same. A method of manufacturing a semiconductor device including a capacitor having a MIM structure includes providing a substrate having a lower wiring pattern formed thereon, sequentially forming a lower wiring protective film and an interlayer insulating film on the substrate, and patterning the interlayer insulating film to form a wiring. Forming openings in which vias and MIM capacitors are to be formed, patterning the interlayer insulating film to form a damascene wiring region in which wiring to be connected to the via is formed, thereby completing the dual damascene region, and the dual damascene region and Removing the lower wiring protection film under the opening, forming a conductive film in the dual damascene region and the opening, and removing the conductive film formed on the interlayer insulating film by a planarization process to remove the dual damascene wiring and the MIM capacitor lower electrode. And a dielectric film and an upper portion on the lower electrode. Forming an electrode to be characterized in that it comprises the step of completing a MIM capacitor.

Description

Semiconductor device having capacitor of MIM structure and manufacturing method therefor {Semiconductor device having metal-insulator-metal capacitor and fabrication method for the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor having a MIM (metal-insulator-metal) structure and a method of manufacturing the same.

Semiconductor devices in BIPOLAR, BICMOS and CMOS technologies require integrated capacitors with high voltage linearity, capacitance values that can be set accurately, and low parasitic capacitance. However, the conventional MOS capacitors used up to now have problems of low voltage linearity and many parasitic capacitances due to the space charge zone for voltage induction.

Due to these problems, semiconductor devices including so-called MIM (metal-insulator-metal) structure capacitors have been introduced. In particular, these MIM structure capacitors are mainly used to store electric charges in various semiconductor devices such as mixed signal products and analog products. do.

1A to 1I are cross-sectional views illustrating a manufacturing process of a semiconductor device including a capacitor having a conventional MIM structure.

First, as shown in FIG. 1A, a lower electrode pattern 101 made of Cu is formed on the semiconductor substrate 100.

Next, as shown in FIG. 1B, a dielectric film 102 made of SiN is deposited on the semiconductor substrate 100 on which the bottom electrode pattern 101 is formed, and an upper electrode 103 made of TaN is formed on the dielectric film 102. E).

Thereafter, as illustrated in FIG. 1C, a SiN film 104 serving as a hard mask during the etching process is formed on the upper electrode 103, and a photoresist pattern is formed on the SiN film 104. 105).

Thereafter, as shown in FIG. 1D, dry etching is performed by the plasma 106 to etch the SiN / TaN / SiN film in the portion where the photoresist pattern 105 is not formed, thereby removing the photoresist. As a result, a capacitor 108 having a MIM structure having a step 107 as shown in FIG. 1E is formed.

Next, as shown in FIG. 1F, a capping nitride layer made of SiN for preventing diffusion of the lower electrode 101 on the semiconductor substrate 100 having the step 107 and the Cu lower electrode pattern 101 formed thereon. (Capping Nitride) 109, a lower intermetal dielectric (110) of floating silicate glass (FSG) on the capping nitride film 109, and a SiN film 111 as an etch stopper. ), The upper interlayer insulating film 112 is formed in order.

Thereafter, a dual damascene process is used to form a dual damascene region 113 for wiring as shown in FIG. 1G.

Thereafter, as shown in FIG. 1H, a barrier metal film 114 is formed to prevent diffusion of the lower electrode made of Cu, and a Cu seed layer 115 is formed on the barrier metal film 114. The Cu 116 is filled in the via contact hole by electrochemical plating on the seed layer 115.

Subsequently, when the surface planarization process is performed by chemical mechanical polishing (CMP), as shown in FIG. 1I, a capacitor having a flattened MIM structure in which wiring is completed is formed.

However, as described above, when the MIM capacitor is made by the above-described method, the photo-etching process is excessively complicated and the process is complicated.

In particular, in the actual process, after forming the lower electrode 101 and the dielectric film 102 of FIGS. 1A and 1B, a photo for securing an alignment key to be used when forming the photoresist pattern 105 for patterning the upper electrode is formed. An additional etching process is required, which may damage other cell patterns irrelevant to the MIM.

In addition, when the Cu wiring process is performed through the dual damascene process for wiring in the state where there is a step 107 as shown in FIG. 1E, a large amount of CMP is required for a long time to eliminate the step of the MIM. The thickness spread becomes large.

Accordingly, in order to solve the above problem, US Pat. No. 6,329,234 first forms a dielectric film and an interlayer insulating film, and then forms vias through a photo-etching or damascene process, and the barrier metal film, Cu seed, and electrical Although a method of forming Cu and CMP by chemical plating has been attempted, this method requires an additional MIM photoetching process in order to make a MIM portion, and after forming a dielectric film, performing dielectric photo-etching for vias. The film quality is liable to be damaged or contaminated by plasma, and the overall film quality is degraded.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device including a MIM structure capacitor capable of forming a MIM capacitor having no step, reducing the number of photo-etching processes, and obtaining a dielectric film having excellent film quality. .

Another technical problem to be solved by the present invention is to provide a semiconductor device including a MIM capacitor having no step and good characteristics.

The objects of the present invention are not limited to the above-mentioned objects, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: providing a substrate having a lower wiring pattern formed thereon, sequentially forming a lower wiring protection film and an interlayer insulating film on the substrate; Patterning the interlayer insulating film to form openings in which the vias and MIM capacitors of the wiring are to be formed; patterning the interlayer insulating film to form a damascene wiring region in which wiring to be connected to the via is formed, thereby completing the dual damascene region; Removing the lower wiring protection layer under the dual damascene region and the opening, forming a conductive layer in the dual damascene region and the opening, and removing the conductive layer formed on the interlayer insulating layer by a planarization process to perform dual damascene. Completing wiring and the MIM capacitor lower electrode and the lower electrode Forming a dielectric film and an upper electrode on the characterized in that it comprises the step of completing a MIM capacitor.

In accordance with another aspect of the present invention, a semiconductor device includes first and second lower interconnections formed on a semiconductor substrate, an interlayer insulation layer formed on the lower interconnections, and an interlayer insulation layer formed in the interlayer insulation layer. 1 is a MIM capacitor having a dual damascene interconnect electrically connected to a lower interconnection and an opening for exposing the second lower interconnection through the interlayer insulating layer and having a lower electrode, a dielectric layer, and an upper electrode sequentially stacked; And the MIM capacitor stacked on the dielectric layer so as to be uniformly stacked along the step of the opening and the upper electrode is completely filled with the opening.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings in order to describe the present invention in more detail.

However, this embodiment is provided so that the disclosure of the present invention is complete, and to those skilled in the art to completely inform the scope of the invention, the present invention is defined by the scope of the claims It will be. Also, like reference numerals refer to like elements throughout.

2 is a flowchart illustrating a method of manufacturing a semiconductor device including a capacitor having a MIM structure according to an embodiment of the present invention, and FIGS. 3A to 3H are cross-sectional views of intermediate structures in each process step of FIG. 2.

First, a lower wiring pattern is formed on a semiconductor substrate (S30).

Specifically, the lower wiring pattern 401 is formed on the semiconductor substrate 400 as illustrated in FIG. 3A.

At this time, it is preferable to use Cu as the material of the lower wiring 401. However, when Cu is used as the material of the lower wiring 401, Cu is difficult to dry etch when forming the Cu wiring pattern. Is formed by.

Subsequently, a lower wiring protection film and an interlayer insulating film are formed in sequence (S31).

Specifically, as shown in FIG. 3B, a lower wiring protection layer 402 and an inter metal dielectric 403 are sequentially deposited on the semiconductor substrate 400 on which the lower wiring pattern 401 is formed.

At this time, the lower wiring protection film 402 is formed to prevent the lower wiring 401 from being damaged when the damascene region (see 406 of FIG. 3D) is formed, and it is preferably made of SiN, which is chemical vapor deposition (CVD). By deposition. In addition, the interlayer insulating film 403 is formed for intermetal insulation inside the semiconductor device, and is preferably made of fluoride silicate glass (FSG), and is formed by chemical vapor deposition.

Subsequently, an opening in which the via and the MIM capacitor of the wiring are to be formed is formed in the interlayer insulating film (S32).

Specifically, as illustrated in FIG. 3C, an opening 405 in which the via 404 and the MIM capacitor are to be formed is formed in the interlayer insulating layer 403.

In this case, the via 404 is formed later for contact between the lower wiring and the upper wiring to be formed later, and the MIM opening 405 is formed at the same time as the via 404 as a portion where the MIM is formed later.

Next, a damascene wiring region is formed to complete the dual damascene region (S33).

Specifically, as shown in FIG. 3D, the interlayer insulating layer 403 is patterned to form a damascene wiring region 406 in which an upper wiring is formed, thereby forming a dual damascene region 407.

At this time, the lower wiring protection film 402 prevents the lower wiring 401 from being damaged by etching. Therefore, the end point of the process for forming the damascene wiring region 406 is set to the point where the via wiring 401 and the lower wiring protection film 402 under the opening 405 are completely removed to expose the lower wiring 401.

Next, a conductive film is formed in the dual damascene region and the opening (S34).

Specifically, as illustrated in FIG. 3E, the conductive film is deposited by sequentially depositing the first barrier metal film 409 and the Cu seed layer 410, and electrochemical plating the Cu layer 411. Form.

In this case, the first barrier metal film 409 is usually formed by applying a physical vapor deposition (PVD) method. As the material of the first barrier metal film 409, Ti, TiN, Ta, TaN, W, or the like may be used. It is preferable to use Ta or TaN. The reason for depositing the first barrier metal film 409 is not only to effectively block Cu diffusion, but also to improve adhesion between the dielectric film and copper and to suppress delamination and electron transfer that may occur during the heat treatment process. .

The Cu seed layer 410 is a process which is the basis of a subsequent electrochemical plating process, and is formed to provide a nucleation site for forming a bulk copper film by electrochemical plating and PVD To form.

Through the electrochemical plating process, the dual damascene region 407 is gap-filled with Cu and the MIM opening 405 is uniformly plated along the step. Despite the same electrochemical plating process, the dual damascene region 407 has a gap peeling phenomenon and the MIM opening 405 has a consistent plating phenomenon instead of gap peeling. This is due to the properties of the accelerator, suppressor and leveler, which are chemical additives. 4 and 5, the accelerator 50 is made of Mercapto Propane Sulfonic Acid (MPSA), which proceeds with a gap fill, and the suppressor 51 is a gap fill on the surface of the membrane. It is made of Poly Ethylene Glycol (PEG) or Poly Vinyl Pyrrolidone (PVP) to prevent the progression, and the leveler 52 allows the deposition of the flat portion at the surface and the boundary of the gap evenly. Polyimine or Polyamide.

5 is a cross-sectional view showing the extent to which the gap filling occurs according to the size of the wiring width.

As shown in FIG. 5, when the wiring width is 0.3 μm or less, the accelerator 50 acts to cause a gap filling phenomenon. When the wiring width is 0.5 μm or more, the accelerator 50 does not work and the leveler 52 does not work. Since it only works, the gap filling phenomenon is not seen and the deposition is performed consistently.

Therefore, in general, the dual damascene region 407 having a wiring width of 0.3 μm or less causes gap filling by electrochemical plating, and in the case of a MIM opening having a wiring width of 10 μm × 5 μm or more, the gap filling does not fill the gap instead of the gap filling phenomenon. It is not consistently deposited along the steps.

Next, the dual damascene wiring and the lower electrode are completed by the planarization process (S35).

Specifically, as shown in FIG. 3F, the first CMP process is performed to remove the Cu 411, the seed layer 410, and the first barrier metal film 409 on the interlayer insulating film 403, thereby removing the dual die. The drank wiring 411a and the lower electrode 411b are formed.

Finally, the dielectric film and the upper electrode are formed to complete the MIM capacitor (S36).

Specifically, as shown in FIG. 3G, a dielectric film 412, a second barrier metal film 413, and a Cu seed layer 414 are sequentially deposited on the structure where the first CMP is completed, as shown in FIG. 3G, and MIM. The part is gap-filled 415 with Cu by electrochemical plating.

At this time, the dielectric film 412 serves as an insulator of the MIM structure and is preferably made of SiN and is deposited by chemical vapor deposition.

The second barrier metal film 413 and the Cu seed layer 414 have the same role and forming method as the first barrier metal film 409 and the Cu seed layer 410, respectively.

In the electrochemical plating process of this step, a gap filling phenomenon occurs because a part of the MIM opening is already filled with the lower electrodes 409, 410, and 411.

Next, as shown in FIG. 3H, when the second CMP is performed, manufacture of the device is completed on the peninsula including the capacitor of the completed MIM structure.

Referring to the cross-sectional structure of the semiconductor device including the MIM capacitor manufactured by the above process as shown in FIG. 3H, first and second lower interconnections 401 are formed on the semiconductor substrate 400. An interlayer insulating film 403 is formed on the lower wirings 401, and a dual damascene wiring 411a and the interlayer insulating film electrically connected to the first lower wiring 401 in the interlayer insulating film 403. An opening 405 is formed through the 403 to expose the second lower wiring 401, and the lower electrode 411b, the dielectric layer 412, and the upper electrode 414b are formed in the opening 405. The MIM capacitor structure is sequentially stacked, wherein the lower electrode 411b and the dielectric film 412 are stacked and aligned along the step of the opening 405, and the upper electrode 414b is the opening 405. ) To fully reclaim The dielectric film 412 is stacked on the structure.

Unlike the conventional semiconductor device manufactured as described above, since the dielectric layer 412 is not exposed to a plasma etching process or the like, it is possible to form a capacitor having a MIM structure having excellent characteristics. In addition, there is no step in the cross-sectional structure of the manufacturing process does not require an excessive planarization process and there is an advantage that can reduce the number of photo-etching process.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in various forms, and a person of ordinary skill in the art to which the present invention belongs. It will be appreciated that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the semiconductor device including the MIM structured capacitor according to the present invention and a method of manufacturing the same, the number of photo-etching processes can be reduced by forming a MIM capacitor without a step, and a dielectric film having excellent film quality can be obtained. It is possible to manufacture a semiconductor device including a capacitor of the MIM structure.

1A to 1I are cross-sectional views illustrating a manufacturing process of a semiconductor device including a capacitor having a conventional MIM structure.

2 is a process flowchart for explaining a method of manufacturing a semiconductor device including a capacitor of the MIM structure according to the present invention.

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device including a capacitor having a MIM structure according to the present invention.

4 is a cross-sectional view illustrating a gap filling process in an electrochemical plating process.

5 is a cross-sectional view showing the extent to which the gap filling occurs according to the size of the wiring width.

Claims (4)

Providing a substrate having a lower wiring pattern formed thereon; Sequentially forming a lower wiring protection film and an interlayer insulating film on the substrate; Patterning the interlayer insulating film to form openings in which vias and MIM capacitors of a wiring are to be formed; Patterning the interlayer insulating film to form a damascene wiring region in which wiring to be connected to the via is formed, thereby completing a dual damascene region, and removing the dual damascene region and the lower wiring protection layer under the opening; Forming a conductive film in the dual damascene region and the opening; Removing the conductive film formed on the interlayer insulating film by a planarization process to complete the dual damascene wiring and the MIM capacitor lower electrode; And Forming a dielectric film and an upper electrode on said lower electrode to complete a MIM capacitor. The method of claim 1, In the forming of the conductive film, the dual damascene region is completely filled and the openings are uniformly formed along a step, Comprising the lower electrode is a step of forming a lower electrode conformally formed in the opening along the step of the opening, The forming of the dielectric film and the upper electrode may include forming a dielectric film on the lower electrode in the opening; Forming an upper conductive film filling the opening on the dielectric film; And removing the dielectric film and the upper conductive film over the interlayer insulating film by a planarization process to complete the upper electrode and the dielectric film of the capacitor. The method of claim 2, Forming the conductive film Forming a first barrier metal film on the dual damascene region and the resultant formed product; Forming a seed layer on the first barrier metal film; And forming a conductive film on the seed layer by electrochemical plating to completely fill the dual damascene region and to conformally form a step along the opening. First and second lower interconnections formed on the semiconductor substrate; An interlayer insulating film formed on the lower interconnections; Dual damascene wiring formed in the interlayer insulating film and electrically connected to the first lower wiring; And A MIM capacitor formed in an opening through the interlayer insulating film to expose the second lower wiring, and having a lower electrode, a dielectric film, and an upper electrode sequentially stacked; the lower electrode and the dielectric film are stacked uniformly along a step of the opening; And an upper electrode includes a MIM capacitor stacked on the dielectric film to completely fill the opening.