KR20050108983A - Electrostatic discharge protection device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection element, comprising: a semiconductor substrate, an impurity diffusion well formed in the semiconductor substrate, and an impurity diffusion well formed on the semiconductor substrate and spaced apart from each other in a predetermined region. A first and second gates, drains formed in the impurity diffusion wells on both sides of the first and second gates, and first and second sources, and spaced apart from the first and second sources at predetermined intervals to form the impurity diffusion wells. And a first impurity diffusion region, wherein the first gate, the first source, and the second impurity diffusion region are connected to each other so as to be connected to a ground terminal, and wherein the second gate, the second source, and the first impurity diffusion region are Are connected to each other so as to be connected to the ground terminal, and the drain is connected to an input / output pad. The electrostatic discharge protection device which can improve the property is provided.

Description

Electrostatic discharge protection device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (hereinafter, referred to as "ESD") protection device, and in particular, an ESD protection device suitable for semiconductor circuits using low operating voltage in the future due to low triggering voltage of parasitic bipolar transistors. It is about.

When a semiconductor integrated circuit comes into contact with a charged human body or machine, the static electricity charged in the human body or machine is discharged into the semiconductor through the external pins and input / output pads of the integrated circuit. Can be added. In addition, the static electricity that has been charged inside the semiconductor circuit flows through the machine due to the contact of the machine to damage the circuit. Most semiconductor integrated circuits install an electrostatic (ESD) protection element between the input and output pads and the semiconductor internal circuitry to protect the main circuit from such damage. However, as semiconductor circuits become more integrated, lower operating voltages are required and chip area is reduced, so that the problem of electrostatic discharge becomes more and more serious. Accordingly, high-performance electrostatic protection is needed to protect internal devices during electrostatic discharge without increasing the area. You will need a device.

As such, many electrostatic protection devices having excellent performances have been researched, and among them, many commonly used devices are gate grounded NMOS (GGNMOS) devices of FIG. 1. Fig. 1A is a sectional view of a GGNMOS device, and Fig. 1B is an equivalent circuit diagram.

Referring to FIG. 1A, a gate oxide film 12 and a gate 13 are formed in a predetermined region on a semiconductor substrate 11 on which a p-type impurity diffusion well is formed, and the semiconductor substrate 11 on both sides of the gate 13 is formed. ), The source 14 and the drain 15 are formed by an n-type impurity ion implantation process. The drain 15 is connected to the input / output pad 16 and the gate 13 and the source 14 are connected to the ground terminal Vss. In this way, the npn bipolar transistor 17 is formed between the drain 15, the source 14, and the semiconductor substrate 11. In this case, the gate resistor Rgate maintains a resistance of several tens of kHz.

However, as the chip area becomes smaller in the future, an electrostatic discharge protection device having better performance than a GGNMOS device is required. Alternatively, a GCNMOS device having a large gate resistance in a GCNMOS device or a GGNMOS device shown in FIG. Is being studied. FIG. 2A is a cross-sectional view of the GCNMOS device, and FIG. 2B is an equivalent circuit diagram.

Referring to FIG. 2A, the gate oxide film 22 and the first gate 23 are formed in a predetermined region on the semiconductor substrate 21 on which the p-type impurity diffusion well is formed, and the other on the semiconductor substrate 21. The field oxide film 24 and the second gate 25 are formed in a predetermined region. An n-type impurity ion implantation process is performed to form the first and second drains 206 and 208 and the source 207. The first drain 26 and the second gate 25 are connected to the input / output pad 29, the first gate 203 and the second drain 28 are connected to each other, and the source 27 is connected to the ground terminal. To (Vss). The GCNMOS device induces a voltage drop between the gate and the source by using the gate resistance Rgate as the AC current Igd flowing through the gate overlap capacitor Cgd.

However, the GCNMOS device also has excellent performance as an ESD protection device. However, as shown in FIG. 2, as the area of the GCNMOS device increases and the voltage drop between the gate and the source increases, the temperature increases due to the increase of the substrate surface current. This also leads to reliability issues of ESD protection devices. Therefore, in order to protect internal devices during electrostatic discharge in future, more integrated semiconductor circuits, there is a need for a ESD protection device having a new structure in which the ESD protection device can operate quickly without increasing the area.

An object of the present invention is to provide an ESD protection device having a high operating speed without increasing the area.

Another object of the present invention is to provide an ESD protection device having a low triggering voltage and excellent reliability of parasitic bipolar transistors.

Conventional GCNMOS devices induce a voltage drop between the gate and the source by using the gate resistance (Rgate) as the AC current (Igd) flowing through the gate overlap capacitor (Cgd), but, in the present invention, the area is relatively large other than Igd. The AC current Ij flowing through the large drain and the junction capacitor Cj of the substrate may also be used to allow a voltage drop at the gate resistance Rgate having a low resistance to be applied by the gate threshold voltage. When the voltage drop across the gate resistor (Vgs) is at a threshold voltage, the MOS transistor begins to operate, and electrons passing through the channel easily induce an Avalanche Breakdown between the drain and the substrate. In addition, the voltage drop induced across the gate resistance (Rgate) generates the substrate voltage of the other adjacent transistors and quickly triggers the parasitic npn bipolar transistor operation consisting of drain / substrate / source when electrostatic discharge is applied to the input / output pads, resulting in transients generated on the input / output pads. Current can be quickly drawn from the drain through the substrate and the source to the ground terminal. The increase in the substrate voltage also reduces the temperature generated by the current flowing through the substrate surface, thereby improving reliability.

An ESD protection device according to the present invention includes a semiconductor substrate, first and second gates formed on the semiconductor substrate, and an impurity diffusion well formed in the semiconductor substrate, and spaced apart from each other in a predetermined region above the semiconductor substrate on which the impurity diffusion wells are formed; Drains and first and second sources formed in the impurity diffusion wells on both sides of the first and second gates, and first and second impurity diffusion regions formed in the impurity diffusion wells spaced apart from the first and second sources by a predetermined distance. Include.

The first gate, the first source and the second impurity diffusion region are connected to each other so as to be connected to the ground terminal, and the second gate, the second source and the first impurity diffusion region are connected to each other so as to be connected to the ground terminal. The drain is connected to the input / output pad.

A first parasitic bipolar transistor is configured between the drain, the impurity diffusion well and the first source, and a second parasitic bipolar transistor is configured between the drain, the impurity diffusion well and the second source.

The drain and the first and second sources are formed including an LDD structure.

The first and second impurity diffusion regions are formed at an impurity concentration of about 10 ²⁰ to 10 ²² dopants / cm 3.

The first and second gates each have a resistance that can cause a voltage drop.

The resistance has a resistance of several tens to thousands of kΩ.

The current during the electrostatic discharge introduced through the input / output pad flows from the drain to the first and second impurity diffusion regions by a parasitic capacitor between the drain and the impurity diffusion well, and the first and the second A voltage drop is induced across the two gates, and a potential difference is generated between the first and second impurity diffusion regions and the impurity diffusion well by the voltage drop.

On the other hand, the ESD device according to the present invention is a semiconductor substrate, the impurity diffusion well formed in the semiconductor substrate, the first and second gates are formed to be spaced apart from each other in the predetermined region above the semiconductor substrate in which the impurity diffusion well is formed; Drains and first and second sources formed in the impurity diffusion wells on both sides of the first and second gates, and first and second impurity diffusion regions formed in the impurity diffusion wells spaced apart from the first and second sources by a predetermined distance. And the first gate, the first source, and the second impurity diffusion region are connected to each other so as to be connected to a ground terminal, and the second gate, the second source, and the first impurity diffusion region are connected to each other to the ground terminal. The drain, the impurity diffusion well and the first source by connecting the drain to an input / output pad. A first parasitic bipolar transistor is configured between, and a second parasitic bipolar transistor is configured between the drain, the impurity diffusion well, and the second source.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 (a) and 3 (b) are a sectional view and an equivalent circuit diagram of an ESD protection device according to the present invention.

Referring to FIG. 3A, a p-type impurity diffusion well 302 having an impurity concentration of 10 ¹⁷ to 10 ¹⁹ dopants / cm 3 is formed in the p-type semiconductor substrate 301. The first gate oxide film 303, the first gate 304, the second gate oxide film 305, and the second gate 306 are formed in a predetermined region on the semiconductor substrate 301 on which the impurity diffusion well 302 is formed. . The n-type impurity is injected into the impurity diffusion wells 302 on both sides of the first and second gates 304 and 306 at a concentration of about 10 ²⁰ to 10 ²² dopants / cm 3 to drain 307 and the first and second. Sources 308 and 309 are formed. In this case, the drain 307 and the first and second sources 308 and 309 may be formed in an LDD structure. P-type impurities are injected into the impurity diffusion well 302 at a concentration of about 10 ²⁰ to 10 ²² dopants / cm 3 so as to be spaced apart from the first and second sources 308 and 309 by a predetermined interval. Areas 310 and 311 are formed. The first gate 304, the first source 308, and the second impurity diffusion region 312 are connected to the ground terminal Vss, and the second gate 306, the second source 309, and the first source 304 are connected to the ground terminal Vss. The impurity diffusion region 310 is connected to the ground terminal Vss, and the drain 307 is connected to the input / output pad 312. In this way, a first parasitic npn bipolar transistor 313 is formed between the drain 307, the impurity diffusion well 302 and the first source 308, and the drain 307, the impurity diffusion well 302 and the first source 308 are formed. A second parasitic npn bipolar transistor 314 is configured between the two sources 309. The first and second gates 304 and 306 each have tens to thousands of kilowatts of first and second to induce an IR voltage drop. There are two gate resistors Rgate1 and Rgate2.

In the ESD protection device configured as described above, the current flowing through the input / output pad 313 during the electrostatic discharge is drained by the AC current Ij1 and Ij2 by the junction capacitor Cj between the drain 307 and the impurity diffusion well 302. At 307, flows to the first and second impurity diffusion regions 311 and 312. However, since the first impurity diffusion region 311 is connected to the second gate 306 and the second impurity diffusion region 312 is connected to the first gate 304 and connected to the ground terminal Vss, the first impurity diffusion region 311 is connected to the first gate 304. And the voltage drops Vgs1 and Vgs2 of the second gate resistors Rgate1 and Rgate2. Since the voltage drop at this time is considerably larger than the current Igd flowing through the previous gate overlap capacitor Cgd, a large voltage drop is induced. In addition, the voltage drops Vgs1 and Vgs2 across the first and second gate resistors Rgate1 and Rgate2 may include the first and second impurity diffusion regions 311 and 312 and the impurity diffusion well 302 connected in parallel with the gate source. By inducing the potential difference between the substrate voltage (Vgs1 and Vgs2) is generated. It is possible to induce a voltage drop between the gate and the source more than the threshold voltage of the MOS transistor even if the gate resistance (Rgate) is small, as in the GGNMOS device can lower the operating voltage of the parasitic bipolar transistor. In addition, the substrate voltages Vgs1 and Vgs2 induced in the substrate disperse current flowing from the drain 307 to the first and second sources 308 and 309 to increase the efficiency area in which power is lost, thereby increasing the gate-to-source voltage. As the drop increases, the problem of decreasing the secondary breakdown current It2 by increasing the surface temperature can be improved, thereby improving the reliability of the electrostatic protection device.

Although the gate is connected to the impurity diffusion region of the adjacent transistor in the above, in another embodiment of the present invention, the gate is directly connected to the impurity diffusion region of its transistor. That is, the first gate 304, the first source 308, and the first impurity diffusion region 310 are connected to the ground terminal Vss, and the second gate 306, the second source 309, and the first source 304 are connected to each other. The impurity diffusion region 312 is connected to the ground terminal Vss and the drain 307 is connected to the input / output pad 312.

4 is a result of comparing the conventional GGNMOS device A and the ESD protection device B according to the present invention by connecting two transistors in parallel and comparing the characteristics of the HBM 2000V applied through a simulation. Even when using the same gate resistor (Rgate) than can be seen that a lot of voltage difference between the gate and the source occurs.

FIG. 5 is a graph illustrating generation of a substrate voltage Vsub such as an induced voltage Vgs between an impurity diffusion region and an impurity diffusion well connected in parallel with a gate source in an ESD protection device according to the present invention.

6 is a graph comparing the voltage difference between the drain and the source of the conventional GGNMOS device (A) and the ESD protection device (B) according to the present invention, the voltage difference between the drain and the source of the ESD protection device according to the present invention It can be seen that the operating voltage of the parasitic bipolar transistor is low.

7 is a graph comparing the current flowing from the drain to the source of the conventional GGNMOS device (A) and the ESD protection device (B) according to the present invention, the operating voltage of the parasitic bipolar transistor of the ESD protection device according to the present invention is lowered As a result, the parasitic bipolar transistor can be operated quickly even if the current flowing from the drain to the source is small.

For reference, FIGS. 8 and 9 compare temperature rising effects according to Vgs and Vsub. In a conventional GCNMOS device, as the Vgs increases, the temperature peak increases and the point where the peak occurs near the surface (FIG. 8). ). As such, the surface temperature rise lowers the secondary breakdown current It2 of the electrostatic protection element, and a way to solve this problem is to apply the substrate voltage Vsub (FIG. 9).

As described above, according to the present invention, after the first and second impurity diffusion regions are formed to be spaced apart from the first and second sources formed on both sides of the first and second gates by a predetermined distance, the first gate, the first source, and the first source are formed. The second impurity diffusion regions are connected to each other to be connected to the ground terminal, and the second gate, the second source, and the first impurity diffusion region are connected to each other to be connected to the ground terminal, and the drain is connected to the input / output pad. AC current flowing through the junction capacitor between the drain and the impurity diffusion well increases the voltage drop across the gate, which induces a voltage between the impurity diffusion region and the substrate to trigger the parasitic bipolar transistor's operating voltage associated with the ESD operation. lower the voltage). In addition, the substrate voltage can lower the thermal temperature generated by the current flowing through the parasitic bipolar transistor, thereby improving the performance and reliability of the ESD protection device.

1 (a) and 1 (b) are a sectional view and an equivalent circuit diagram of a GGNMOS device as an embodiment of a conventional electrostatic discharge protection device.

2 (a) and 2 (b) are a sectional view and an equivalent circuit diagram of a GCNMOS device as another embodiment of a conventional electrostatic discharge protection device.

3 (a) and 3 (b) are a sectional view and an equivalent circuit diagram of an electrostatic discharge protection device according to the present invention.

4 is a graph comparing voltage differences between a gate and a source of a conventional GGNMOS device and an ESD protection device according to the present invention;

5 is a graph comparing a substrate voltage Vsub such as a voltage Vgs between a source and an impurity diffusion region connected in parallel with a gate-source of an ESD protection device according to the present invention.

6 is a graph comparing voltage differences between a drain and a source of a conventional GGNMOS device and an ESD protection device according to the present invention;

7 is a graph comparing current flowing from the drain to the source of the ESD protection device according to the present invention GGNMOS device.

8 is a graph comparing the temperature peak value according to the voltage Vgs between the impurity diffusion region and the source of the conventional GGNMOS device and the ESD protection device according to the present invention and the depth from the surface where the temperature peak appears.

9 is a graph showing the substrate voltage (Vsub) effect according to the finger width.

<Explanation of symbols for the main parts of the drawings>

301: semiconductor substrate 302: impurity diffusion well

303 and 305: first and second gate oxide films

304 and 306: first and second gate

307: drain 308 and 309: first and second source

310 and 311: first and second impurity diffusion regions

312 input / output pad

313 and 314: first and second parasitic npn bipolar transistors

Claims (11)

Semiconductor substrates; An impurity diffusion well formed in the semiconductor substrate; First and second gates spaced apart from predetermined regions on the semiconductor substrate on which the impurity diffusion wells are formed; Drains and first and second sources formed in the impurity diffusion wells on both sides of the first and second gates; And And first and second impurity diffusion regions formed in the impurity diffusion well spaced apart from the first and second sources at predetermined intervals. The semiconductor device of claim 1, wherein the first gate, the first source, and the second impurity diffusion region are connected to each other so as to be connected to a ground terminal, and the second gate, the second source, and the first impurity diffusion region are connected to each other to form the And a drain connected to an input / output pad, wherein the drain is connected to a ground terminal. The method of claim 1, wherein the first gate, the first source, and the first impurity diffusion region are connected to each other so as to be connected to a ground terminal, and the second gate, the second source, and the second impurity diffusion region are connected to each other to form the And a drain connected to an input / output pad, wherein the drain is connected to a ground terminal. 2. The electrostatic discharge protection of claim 1 wherein a first parasitic bipolar transistor is configured between the drain, an impurity diffusion well and a first source, and a second parasitic bipolar transistor is configured between the drain, an impurity diffusion well and a second source. device. The device of claim 1, wherein the drain and the first and second sources include an LDD structure. The device of claim 1, wherein the first and second impurity diffusion regions are formed at an impurity concentration of about 10 ²⁰ to 10 ²² dopants / cm 3. The electrostatic discharge protection device of claim 1, wherein the first and second gates each have a resistance that can cause a voltage drop. 8. The electrostatic discharge protection device of claim 7, wherein the resistance has a resistance of several tens to thousands of kohms. 2. The method of claim 1, wherein the current during electrostatic discharge introduced through the input / output pad flows from the drain to the first and second impurity diffusion regions by a parasitic capacitor between the drain and the impurity diffusion well. And a voltage drop is induced across the first and second gates, and a potential difference is generated between the first and second impurity diffusion regions and the impurity diffusion well by the voltage drop. Semiconductor substrates; An impurity diffusion well formed in the semiconductor substrate; First and second gates spaced apart from predetermined regions on the semiconductor substrate on which the impurity diffusion wells are formed; Drains and first and second sources formed in the impurity diffusion wells on both sides of the first and second gates; And A first impurity diffusion region formed in the impurity diffusion well spaced apart from the first and second sources by a predetermined distance, The first gate, the first source and the second impurity diffusion region are connected to each other so as to be connected to the ground terminal, and the second gate, the second source and the first impurity diffusion region are connected to each other so as to be connected to the ground terminal. The first parasitic bipolar transistor is configured between the drain, the impurity diffusion well, and the first source by allowing the drain to be connected to the input / output pad, and the second parasitic bipolar transistor is configured between the drain, the impurity diffusion well, and the second source. Electrostatic discharge protection device. Semiconductor substrates; An impurity diffusion well formed in the semiconductor substrate; First and second gates spaced apart from predetermined regions on the semiconductor substrate on which the impurity diffusion wells are formed; Drains and first and second sources formed in the impurity diffusion wells on both sides of the first and second gates; And A first impurity diffusion region formed in the impurity diffusion well spaced apart from the first and second sources by a predetermined distance, The first gate, the first source and the first impurity diffusion region are connected to each other so as to be connected to the ground terminal, and the second gate, the second source and the second impurity diffusion region are connected to each other so as to be connected to the ground terminal. The first parasitic bipolar transistor is configured between the drain, the impurity diffusion well, and the first source by allowing the drain to be connected to the input / output pad, and the second parasitic bipolar transistor is configured between the drain, the impurity diffusion well, and the second source. Electrostatic discharge protection device.