KR20050108924A - Lcd with color-filter on tft and method of fabricating of the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and a liquid crystal display device having a COT structure in which a color filter is formed on an array substrate.

In particular, the present invention relates to a COT structure liquid crystal display device including a black matrix made of a metal having a repair function and a manufacturing method thereof.

The array substrate for a liquid crystal display device according to the present invention constitutes a black matrix made of a metal material corresponding to the data line, the gate line and the thin film transistor, and the black matrix located above the data line is configured to be in contact with the data line. The black matrix located above the wiring is configured to be in contact with the gate wiring.

In this way, a signal delay caused by using a metal black matrix can be prevented, and when the data line and the gate line are disconnected, it can be used as a repair line.

In addition, there is an advantage that can reduce the cost because it does not need to use a high-cost resin black matrix.

Description

CIO structure liquid crystal display and manufacturing method thereof {LCD with color-filter on TFT and method of fabricating of the same}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a color filter on TFT (COT) structure and a method of manufacturing the same.

In general, a liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the alignment of liquid crystals is changed, and the characteristics of light transmission vary according to the arrangement direction of the changed liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

1 is a view schematically showing a liquid crystal display according to the related art.

As shown, a general color liquid crystal display 11 includes a color filter 7 and a color filter 7 including a black matrix 6 formed between a sub color filter 8 and each sub color filter 8. The upper substrate 5 having the common electrode 18 deposited thereon, the pixel region P, and the pixel electrode 17 and the switching element T formed in the pixel region, and the pixel region P The liquid crystal 14 is filled between the lower substrate 22 and the upper substrate 5 and the lower substrate 22 on which array wiring is formed.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 passing through the plurality of thin film transistors T is crossed. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate line 13 and the data line 15 crossing each other, and a transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

A storage capacitor C _ST connected in parallel with the pixel electrode 17 is formed on the gate wiring 13, and a part of the gate wiring 13 is used as the first electrode of the storage capacitor C _ST . As the second electrode, an island-shaped metal pattern 30 formed of the same material as the source and drain electrodes is used.

In this case, the metal pattern 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

However, as described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, light leakage due to the bonding error between the color filter substrate 5 and the array substrate 22 is poor. There is a very high probability of occurrence.

This will be described below with reference to FIG. 2.

FIG. 2 is a cross-sectional view illustrating a cross-sectional structure of the liquid crystal display of FIG. 1.

As illustrated, the first substrate 22 is defined as a pixel area P including a switching area S and a storage area C. FIG.

The switching region S includes a thin film transistor T including a gate electrode 32, an active layer 34, a source electrode 36, and a drain electrode 38, and a transparent pixel in the pixel region P. The electrode 17 is configured.

In the storage region C, the gate wiring 13 is used as the first electrode, and the metal pattern 30, which is formed in an island shape on the gate wiring 13 and contacts the pixel electrode 17, is formed in the second electrode. The storage capacitor C _{ST used} as an electrode is comprised.

In this case, the storage capacitor C _ST may be configured in various structures and shapes.

On one surface of the second substrate 5 spaced apart from each other with the first substrate 22 and the liquid crystal layer 14 interposed therebetween, the thin film transistor T, the gate wiring, and the data wiring 13 and 15 may correspond to each other. The black matrix 6 is configured, and the color filters 7a, 7b, and 7c are formed on the surface corresponding to the pixel region P. As shown in FIG.

A transparent common electrode 18 is formed on the entire surface of the substrate 22 including the color filters 7a, 7b, and 7c and the black matrix 6.

In general, the first substrate 22 and the second substrate 5 described above are manufactured separately, and the process of adhering is performed when each production is completed.

At this time, when a bonding error occurs, the position of the black matrix 6 is deviated from the originally designed position. As a result, light enters the thin film transistor T to generate a leakage current, and the gate and data lines 13 , In a region corresponding to 15, that is, in a space A spaced apart from the data line 15 and the pixel electrode 17 and in a space B spaced between the gate line 13 and the pixel electrode 17. There is a problem that light leakage occurs.

Therefore, conventionally, in order to solve this problem, in consideration of an error in the bonding process, the additional design margin is added to the initial design.

That is, the size of the black matrix 6 is designed to be larger.

In this way, the above defects do not occur even when a bonding error occurs.

However, since there is a problem of encroaching on the opening area by that much, there is a problem that the luminance and the opening ratio are reduced.

The present invention has been proposed for the purpose of solving the above-mentioned problem, characterized in that the color filter and the black matrix is formed on the lower substrate.

In particular, the black matrix is formed of an opaque metal wiring, which is configured to correspond to the gate wiring and the data wiring, and is in contact with each of the wirings.

By constructing in this way, there is no need to design additional bonding margins when constructing the black matrix, so that the opening ratio is greatly improved.

In this case, when the black matrix is formed on the lower substrate, an insulating black resin is used to prevent signal delay of the wiring. However, as described above, since the black matrix is configured to be in direct contact with the gate and data wiring, it is possible to form a black resin. There is an advantage that the cost can be reduced than using the, and it is possible to use the black matrix as a repair wiring of the gate wiring and data wiring, there is an advantage that does not need to add a separate repair process when disconnection.

According to the present invention for achieving the above object, a C. structure (COT) liquid crystal display device comprising: a first substrate and a second substrate; A gate wiring and a data wiring defining a pixel area by vertically crossing each other on one surface of the first substrate facing the second substrate; A switching element configured at an intersection point of the gate line and the data line; A first black matrix positioned independently of the gate wiring and the data wiring, respectively, and configured to be in contact with the gate wiring or the data wiring below; A color filter configured in the pixel region; A transparent pixel electrode on the color filter and in contact with the switching element; A second black matrix formed on a portion of the second substrate facing the first substrate, the portion corresponding to the switching element; It includes a transparent common electrode configured on the front surface of the second substrate including the second black matrix.

A storage wiring is formed corresponding to the pixel area, and a metal pattern, which is the same layer and the same material as the black matrix, is further formed on the storage wiring while contacting the drain electrode.

The black matrix is formed of an opaque conductive metal.

The black matrix of the second substrate is configured to correspond to the active layer exposed between the source and drain electrodes.

In order to maintain a gap between the first substrate and the second substrate, a columnar spacer configured to correspond to the switching element is further configured.

According to an aspect of the present invention, there is provided a method of manufacturing a C. O structure liquid crystal display device, comprising: preparing a first substrate and a second substrate; Forming gate lines and data lines on one surface of the first substrate facing the second substrate so as to vertically cross each other to define pixel regions; Forming a switching element at an intersection point of the gate line and the data line; Forming a first black matrix positioned independently over the gate wiring and the data wiring, each of which is in contact with a gate wiring or a data wiring below; Forming a color filter in the pixel region; Forming a transparent pixel electrode on the color filter and in contact with the switching element; Forming a second black matrix on one surface of the second substrate facing the first substrate, the portion corresponding to the switching element; Forming a transparent common electrode on an entire surface of the second substrate including the second black matrix.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a C. O structure liquid crystal display device, including: defining a pixel area including a switching area on a substrate; A first mask process step of forming a gate electrode and a gate wiring connected to the gate electrode in the switching region; Forming a gate insulating film over the gate electrode and the gate wiring; A second semiconductor pattern and a source and drain electrode stacked on an upper portion of the gate insulating layer corresponding to the gate electrode, and a second data line formed on the second semiconductor pattern and the second semiconductor pattern connected to the first semiconductor pattern. A mask processing step; A third mask process step of forming a protective film on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed, and exposing a portion of the data wiring and the gate wiring; A fourth mask process step of forming a black matrix independently formed on top of said gate wiring and data wiring, each forming a black matrix in contact with a lower exposed gate wiring and data wiring; A fifth mask process step of forming a color filter corresponding to the pixel region; A sixth mask process step of exposing the drain electrode;

And a seventh mask process step of forming a transparent pixel electrode in contact with the drain electrode and positioned in the pixel region.

Forming a storage line corresponding to a portion of the pixel region in the first mask process step, and forming the same storage material on the storage line as the same material as the black matrix in the fourth mask process step And forming a metal pattern in contact with the drain electrode.

The removing of the passivation layer corresponding to the pixel area may be further performed in the third mask process step.

The second mask process may include stacking a gate insulating film, a pure amorphous silicon layer, an amorphous silicon layer containing an impurity, and a metal layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Forming a photosensitive layer on the metal layer, and placing a mask including a transmissive part, a reflective part, and a transflective part on the substrate on which the photosensitive layer is formed; Irradiating light to the upper portion of the mask, exposing and developing a lower photosensitive layer to form a photosensitive pattern corresponding to one side of the pixel region perpendicular to the switching region and the gate wiring; Removing the metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer exposed to the periphery of the photosensitive pattern; Ashing the photosensitive pattern to completely remove a photosensitive pattern of a portion in which only a part corresponding to the transflective portion of the mask is developed to expose a lower metal layer; Removing the metal layer exposed to the periphery of the photosensitive pattern, and exposing an underlying impurity amorphous silicon layer; Removing the photosensitive pattern to form source and drain electrodes, data wirings, a first semiconductor pattern under the source and drain electrodes, and a second semiconductor pattern under the data wirings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

A feature of the present invention is characterized in that, when forming the black matrix corresponding to the gate wiring and the data wiring, it is formed by using an opaque metal and configured to be in contact with the gate wiring and the data wiring.

3 is an enlarged plan view illustrating an enlarged portion of an array substrate for a COT structure liquid crystal display device according to the present invention.

As shown, the gate wiring 102 extending in one direction on the substrate 100 and including the gate pad 106 at one end thereof, and perpendicularly intersects the gate wiring 102 to the pixel region P. As shown in FIG. And a data line 132 including a data pad 134 at one end thereof.

The thin film transistor T including the gate electrode 104, the active layer 124, the source electrode 128, and the drain electrode 130 is formed at the intersection of the gate wiring 102 and the data wiring 132. .

The semiconductor layer SL, which is the same material as the active layer 124 of the thin film transistor T, extends below the data line and the data pads 132 and 134.

Such a configuration has an advantage that the process can be simplified by allowing the source and drain electrodes and the semiconductor layer to be manufactured in one mask at the same time.

The pixel region P includes a transparent pixel electrode 154 in contact with the drain electrode 130, and a transparent contact with the gate pad 106 on the gate pad and the data pads 106 and 134. A gate pad terminal 156 and a transparent data pad terminal 158 in contact with the data pad 134 are formed.

The active matrix 124 exposed between the source and drain electrodes 128 and 130 of the thin film transistor T and the black matrix 202 and 140a correspond to the gate line 102 and the data line 132. The black matrix 140a configured to correspond to the gate wiring 102 and the data wiring 132 is in contact with the lower gate wiring and the data wiring 102 and 132 at arbitrary positions G1, G2 / H1, and H2.

In this case, the black matrix 202 patterned corresponding to the active layer 124 between the source and drain electrodes 128 and 130 is formed on the upper substrate.

Color filters 142a, 142b, and 142c are formed in the pixel area P.

In addition, a storage wiring 108 is formed in the pixel region P, and an insulating film (gate insulating film, not shown) is interposed between the storage wiring 108 and the same material as that of the black matrix 140a. At the same time, the metal pattern 140b is formed to contact the drain electrode 130.

In this configuration, a storage capacitor C _ST having the storage wiring 108 as a first electrode and the metal pattern 140b as a second electrode is formed.

In the above-described configuration, the characteristic is that the black matrices 140a and 202 are formed of an opaque metal rather than a black resin, and the black matrix 140a corresponding to the data and gate lines 132 and 102 has a lower portion. The gate wiring 102 and the data wiring 132 are configured to be in contact with each other.

4A and 4B, a configuration of a COT structure liquid crystal display device according to the present invention will be schematically described.

FIG. 4A is a cross-sectional view taken along line IV-IV of FIG. 3, and FIG. 4B is a cross-sectional view of a liquid crystal display device taken along line V-V of FIG. 3 and described with reference thereto. FIG. 4A is a pixel including a thin film transistor. 4B is a cross-sectional view of the portion where the black matrix and the data wiring are formed.)

As shown in FIGS. 4A and 4B, the COT structure liquid crystal display according to the present invention includes a first substrate 100 and a second substrate 200 which are spaced apart and bonded.

A pixel area P including a switching area S is defined on the first substrate 100, and a storage area ST is defined corresponding to a portion of the pixel area P. FIG.

In the switching region S, a gate electrode 104, a gate electrode 104, and an active layer 124 and an ohmic contact layer 126 stacked between the gate insulating layer 110 and an ohmic contact layer ( A thin film transistor T including a source electrode 128 and a drain electrode 130 spaced apart from the upper portion 126 is configured.

Color filters 142a and 142b are formed in the pixel region P, and transparent pixel electrodes 154 are formed on the color filters 142a and 142b with the planarization layer 146 interposed therebetween.

The gate wiring 102 is formed on the substrate 100 corresponding to one side of the pixel region P, and the data wiring 132 is formed on the other side of the pixel region P which is perpendicular to the pixel region P. FIG.

In this case, the semiconductor layer SL is positioned under the data line 132.

The black matrix 140a is formed of an opaque metal on the upper portion corresponding to the data line 132 and the gate line 102, but the black matrix 140a corresponding to the gate line 102 and the data line 132 is formed. Is configured to contact lower gates and data lines 102 and 132.

As described above, the first substrate 100 may be configured, and a black matrix 202 is formed on one surface of the second substrate 200 facing the first substrate 100 to correspond to the active layer. A transparent common electrode 204 is formed on the entire surface of the substrate 200 on which the black matrix 202 is formed.

In this case, in order to maintain a gap between the two substrates between the first substrate and the second substrates 100 and 200, a columnar spacer 300 is formed to correspond to the active layer 124.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device having a COT structure according to the present invention will be described with reference to the process drawings.

5A to 5G, 6A to 6G, 7A to 7G, and FIGS. 8A to 8G are cut along the lines IV-IV, VI-VI, VIII-V and V-V of FIG. 3 to thin-film transistor array wiring. Is a cross-sectional view showing a step of forming a film according to the process sequence.

5A, 6A, 7A, and 8A, a pixel region P including a switching region S and a storage region ST is defined on the substrate 100.

Aluminum (Al), aluminum alloy (AlNd), copper (Cu), tungsten (W), chromium (Cr), and molybdenum (Mo) on the substrate 100 in which the plurality of regions S, ST, and P are defined Depositing and patterning one or more materials selected from the group of conductive metals including a gate, and the like, the gate wiring 102 including one side of the pixel region P and a gate pad 106 at one end thereof; The gate electrode 104 is formed to be connected to the gate line 102 and positioned in the switching region S.

At the same time, the storage wiring 108 corresponding to the storage area ST is formed.

Next, an inorganic material including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the gate pad and the gate wiring 106 and 102, the gate electrode 104, and the storage wiring 108 are formed. The gate insulating layer 110 is formed by depositing one or more materials selected from the group of insulating materials.

As shown in FIGS. 5B, 6B, 7B, and 8B, the first semiconductor layer 112 and the second semiconductor layer 114 are stacked on the gate insulating layer 110.

The first semiconductor layer 112 is formed by depositing pure amorphous silicon (a-Si: H), and the second semiconductor layer 114 is an amorphous silicon layer (n + or p + a-Si: H) containing impurities. ) Is formed by vapor deposition.

Next, the metal layer 116 is formed by depositing one or more materials selected from the aforementioned conductive metal groups on the second semiconductor layer 114.

A photoresist is formed on the entire surface of the substrate 100 on which the metal layer 116 is formed to form a photosensitive layer 118, and a mask (or mask) is disposed on the spaced upper portion of the substrate 100 on which the photosensitive layer 118 is formed. Place M).

The mask M may include a transmissive part B1, a reflective part B2, and a transflective part B3, and the transflective part B3 may form a slit as shown, or a translucent film may be used. .

In this case, in particular, the switching region S may include the transflective portion B3 corresponding to the center portion, and the mask M may be positioned such that the reflective portions B2 are formed on both sides of the transflective portion B3.

When the upper portion of the mask M is irradiated with light to expose the lower photosensitive layer 118, the photosensitive layer 118 corresponding to the transmissive portion B1 of the mask M is completely exposed, but the half Only part of the photosensitive layer 118 corresponding to the transmissive portion B3 is exposed.

In addition, the photosensitive layer 118 corresponding to the reflector B2 is not exposed.

The process of developing the partially exposed photosensitive layer 118 is performed.

As shown in FIGS. 5C, 6C, 7C, and 8C, when the developing process is performed, one side of the switching region S and the pixel region P perpendicular to the gate wiring 102 may be corresponded. Thus, the photosensitive pattern 120 is formed.

Next, the metal layer exposed to the outside of the photosensitive pattern 120 is removed to leave the patterned metal layer 116 only at the bottom of the photosensitive pattern.

As shown in FIGS. 5D, 6D, 7D, and 8D, a process of sequentially removing the second semiconductor layer 114 and the first semiconductor layer 112 exposed to the lower portion of the removed metal layer is performed. In addition, the first semiconductor layer 112 and the second semiconductor layer 114 patterned on only the lower portion of the photosensitive layer 120 is left.

As shown in FIGS. 5E, 6E, 7E, and 8E, the process of ashing the photosensitive pattern 120 is performed to expose only a portion of the surface from the surface corresponding to the center of the switching region S. Referring to FIGS. The photosensitive layer of is completely removed so that the underlying metal layer 116 is exposed.

At this time, the photosensitive pattern 120 during the ashing process proceeds while both the surface and the side are sharpened so that when the ashing process is completed, the metal layer 116 is exposed to the periphery F of the entire photosensitive pattern.

As shown in FIGS. 5F, 6F, 7F, and 8F, a process of patterning the exposed metal layer 116 corresponding to the center of the switching region S is performed.

Subsequently, a process of removing the exposed second semiconductor layer 114 under the exposed metal layer is performed.

While the process is in progress, the same process is simultaneously performed to the periphery of the photosensitive pattern 120 to form a shape in which the first semiconductor layer 112 is exposed.

After the etching process as described above, the process of removing the photosensitive pattern 120 is performed.

As shown in FIGS. 5G, 6G, 7G, and 8G, a patterned first semiconductor layer and a second semiconductor layer are stacked in the switching region S, and an upper portion of the second semiconductor layer is exposed. The source electrode 128 and the drain electrode 130 are formed with the first semiconductor layer interposed therebetween, and one side of the pixel region P is connected to the source electrode 128 and is perpendicular to the gate wiring 102. The data line 132 is configured to cross each other and includes a data pad 134 at one end.

In addition, a lower portion of the data line 132 and the data pad 134 also include a first semiconductor layer and a second semiconductor layer.

According to the function, the first semiconductor layer formed in the switching region S is called an active layer 124, and the second semiconductor layer thereon is called an ohmic contact layer 126.

The first and second semiconductor layers stacked below the data line 132 are referred to as a semiconductor pattern SL.

The semiconductor pattern SL functions to prevent the upper data line 132 from floating.

The process of forming the thin film transistor and the array wiring on the substrate has been described above.

Hereinafter, a process of forming a color filter on the thin film transistor array unit will be described with reference to the drawings.

9A to 9E, 10A to 10E, 11A to 11E, and 12A to 12E are cross-sectional views taken along line IV-IV, VI-VI, VIII-V and V-V of FIG. A color filter forming step following the step of forming the transistor array wiring is a sectional view showing the process sequence.

As shown in FIGS. 9A, 10A, 11A, and 12A, nitride is formed on the entire surface of the substrate 100 on which the source and drain electrodes 128 and 130, the data line 132, and the data pad 134 are formed. The protective layer 136 is formed by depositing and patterning one or more materials selected from the group of inorganic insulating materials including silicon (SiN _X ) and silicon oxide (SiO ₂ ).

Next, the passivation layer 136 may be patterned to expose a portion of the drain electrode 124, and the data line 132 may be disposed at an arbitrary position (G1 and G2 of FIG. 3). A second contact hole 140 exposing a part and a plurality of spaced apart third contact holes (not shown) exposing a part of the gate wiring 102 at an arbitrary position (H1, H2 of FIG. 3). do.

At the same time, a process of removing the protective film 136 corresponding to the pixel region P is performed.

9B, 10B, 11B, and 12B, one of the above-described conductive metal groups is deposited and patterned on the entire surface of the substrate 100 on which the passivation layer 136 is formed to form the data line 132. ) And a black matrix 140a in contact with the gate wiring 102, respectively, and contact the exposed drain electrode 130 to form an island pattern on the storage wiring 108 in an island shape. 140b).

In this case, the black matrix 140a formed on the gate line and the data line 102 and 132 is spaced apart from each other at a portion where the gate line 102 and the data line 132 cross each other.

This is because each is configured to be in contact with the gate wiring 102 and the data wiring 132.

In the above-described configuration, a storage capacitor C _ST is formed in the storage area ST, and the metal pattern 140b disposed on the storage wire 108 contacts the drain electrode 132 to emit light. The second electrode of the storage capacitor C _ST is not a blocking function, and the lower storage wiring 108 serves as the first electrode.

This configuration is sufficient even if the area is small because there is no semiconductor layer between the first electrode 108 and the second electrode (metal pattern 140b in the pixel region) and only an inorganic insulating material having a high dielectric constant exists as a dielectric. There is an advantage to getting storage capacity.

In addition, since the black matrix 140a formed on the upper portion of the gate line 102 and the data line 132 is in contact with the lower line, the black matrix 140a blocks the light or prevents different light from being mixed between the pixel areas. At the same time, the gate line or data line 102 and 132 may be repaired when the gate line or data line 102 is cut.

9C, 10C, 11C, and 12C, red, green, and blue colors corresponding to the pixel region P of the substrate 100 on which the black matrix 140a and the metal pattern 140b are formed. A process of sequentially forming the filters 142a and 142b (not shown) in a predetermined order is performed.

As shown in FIGS. 9D, 10D, 11D, and 12D, benzocyclobutene (BCB) and acrylic resin (resin) on the entire surface of the substrate 100 on which the color filters 142a and 142b are formed. The planarization layer 146 is formed by coating one or more materials selected from the group of organic insulating materials including a.

In this case, the planarization layer 146 may be formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ).

Next, the planarization layer 146 is etched to expose the drain contact hole 148 exposing the metal pattern 140b in contact with the drain electrode 130, and the gate pad exposing the gate pad 106. A contact hole 150 and a data pad contact hole 152 exposing the data pad 134 are formed.

As shown in FIGS. 9E, 10E, 11E, and 12E, indium tin oxide (ITO) and indium zinc oxide (IZO) may be formed on the entire surface of the substrate 100 on which the planarization layer 146 is formed. Depositing and patterning a selected one of a transparent conductive metal group including a pixel electrode 154 in contact with the exposed metal pattern 140b in contact with the drain electrode 130, and the exposed gate pad 106. A gate pad terminal 156 in contact with each other and a data pad terminal 158 in contact with the data pad 134 are formed.

Through the process as described above it is possible to manufacture an array substrate for a COT structure liquid crystal display device according to the present invention.

Accordingly, the liquid crystal display of the COT structure manufactured according to the present invention introduces a structure in which a black matrix is formed of an opaque conductive metal and is connected to the gate and the data line, thereby preventing signal delay of the gate line and the data line. It is effective.

Therefore, the width of the gate wiring and the data wiring can be designed small, and the large area and the high-aperture pixel design can be easily performed.

In addition, since the black matrix can be used as a repair wiring when the gate wiring and the data wiring are disconnected, there is an effect that an additional process for repairing the wiring is disconnected.

In addition, since the black matrix is used as the second electrode of the storage capacitor, only a gate insulating layer may exist in the lower portion of the second electrode, thereby ensuring sufficient storage capacity without increasing the area of the storage capacitor. It can work.

Therefore, in the structure in which the storage area is formed in the pixel area, the aperture ratio can be improved.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device;

2 is a cross-sectional view schematically showing a configuration of a general color liquid crystal display device;

3 is an enlarged plan view showing a part of an array substrate for a COT structure liquid crystal display device according to the present invention;

4A and 4B are cross-sectional views schematically illustrating a configuration of a liquid crystal display (COT) structure according to the present invention, in which IV-IV and V-V of FIG.

5A to 5G, 6A to 6G, 7A to 7G, and 8A to 8G are cut along the lines IV-IV, VI-VI, VIII-V and V-V of FIG. 3, respectively. Is a cross-sectional view showing a thin film transistor and an array wiring process of an array substrate for a COT structure liquid crystal display according to a process sequence,

9A to 9E, 10A to 10E, 11A to 11E, and 12A to 12E are cut along the lines IV-IV, VI-VI, VIII-V and V-V of FIG. The cross-sectional view of the color filter forming process of the array substrate for a COT structure liquid crystal display device according to the process sequence is shown.

<Brief description of the main parts of the drawing>

100: substrate 102: gate wiring

104: gate electrode 106: gate pad

108: storage wiring 124: active layer

128: source electrode 130: drain electrode

132: data wiring 134: data pad

140: black matrix 142a, b, c: color filter

154: pixel electrode 156: data pad terminal

158: gate pad terminals

Claims (25)

A first substrate and a second substrate; A gate wiring and a data wiring defining a pixel area by vertically crossing each other on one surface of the first substrate facing the second substrate; A switching element configured at an intersection point of the gate line and the data line; A first black matrix positioned independently of the gate wiring and the data wiring, respectively, and configured to be in contact with the gate wiring or the data wiring below; A color filter configured in the pixel region; A transparent pixel electrode on the color filter and in contact with the switching element; A second black matrix formed on a portion of the second substrate facing the first substrate, the portion corresponding to the switching element; A COT structure liquid crystal display device comprising a transparent common electrode formed on an entire surface of a second substrate including the second black matrix. The method of claim 1, A COT structure liquid crystal display device further comprising a storage wiring corresponding to the pixel area. The method of claim 2, A COT structure liquid crystal display device positioned above the storage wiring and contacting the drain electrode, the metal pattern being the same layer and the same material as the black matrix. The method of claim 1, The black matrix is a C. O. (COT) structure liquid crystal display, characterized in that the opaque conductive metal. The method of claim 1, The color filter is a C. O. (COT) structure liquid crystal display device which is a color filter of red, green, and blue sequentially formed corresponding to the pixel area. The method of claim 1, The switching element includes a gate electrode, an active layer positioned over the gate electrode with an insulating layer interposed therebetween, and source and drain electrodes spaced apart from each other on the active layer. The method of claim 6, The black matrix of the second substrate is configured to correspond to the active layer exposed between the source and drain electrodes. The method of claim 1, A COT structure liquid crystal display device comprising a columnar spacer configured to correspond to the switching element to maintain a gap between the first substrate and the second substrate. The method of claim 1, A COT structure liquid crystal display device further comprising a planarization layer between the pixel electrode and the color filter. Preparing a first substrate and a second substrate; Forming gate lines and data lines on one surface of the first substrate facing the second substrate to vertically cross each other to define pixel regions; Forming a switching element at an intersection point of the gate line and the data line; Forming a first black matrix positioned independently over the gate wiring and the data wiring, each of which is in contact with a gate wiring or a data wiring below; Forming a color filter in the pixel region; Forming a transparent pixel electrode on the color filter and in contact with the switching element; Forming a second black matrix on one surface of the second substrate facing the first substrate, the portion corresponding to the switching element; Forming a transparent common electrode on an entire surface of a second substrate including the second black matrix C. O. (COT) structure liquid crystal display device manufacturing method comprising a. The method of claim 10, A COT structure liquid crystal display device further comprising a storage wiring corresponding to the pixel area. The method of claim 11, And forming a metal pattern on the storage wiring, the metal pattern being made of the same layer and the same material as the first black matrix while being in contact with the drain electrode. The method of claim 12, A COT structure liquid crystal display device having an inorganic insulating film interposed between the storage wiring and the metal pattern. The method of claim 10, And wherein the black matrix is formed of an opaque conductive metal. The method of claim 10, And the color filter is a red, green, and blue color filter formed sequentially corresponding to the pixel area. The method of claim 10, The switching device includes a gate electrode, an active layer disposed over the gate electrode with an insulating layer interposed therebetween, and a source and drain electrode spaced apart from each other on the active layer. Way. The method of claim 16, And a black matrix of the second substrate is formed corresponding to an active layer exposed between the source and drain electrodes. The method of claim 10, And forming a planarization layer between the color filter and the pixel electrode. The method of claim 18, The planarization layer is selected from an organic insulating material group including benzocyclobutene (BCB) and an acrylic resin (resin) or an inorganic insulating material group including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). Manufacturing method of C. O. structure liquid crystal display device formed as one. Defining a pixel region comprising a switching region on the substrate; A first mask process step of forming a gate electrode and a gate wiring connected to the gate electrode in the switching region; Forming a gate insulating film over the gate electrode and the gate wiring; A second semiconductor pattern and a source and drain electrode stacked on an upper portion of the gate insulating layer corresponding to the gate electrode, and a second data line formed on the second semiconductor pattern and the second semiconductor pattern connected to the first semiconductor pattern. A mask processing step; A third mask process step of forming a protective film on an entire surface of the substrate on which the source and drain electrodes and the data wiring are formed, and exposing a portion of the data wiring and the gate wiring; A fourth mask process step of forming a black matrix independently formed on top of said gate wiring and data wiring, each forming a black matrix in contact with a lower exposed gate wiring and data wiring; A fifth mask process step of forming a color filter corresponding to the pixel region; A sixth mask process step of exposing the drain electrode; A seventh mask process step of forming a transparent pixel electrode in contact with the drain electrode and positioned in the pixel region C. O. structure structure array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 20, And forming a storage wiring corresponding to a portion of the pixel region in the first mask process step. The method of claim 21, And forming a metal pattern formed on the same layer as the black matrix and in contact with the drain electrode in the fourth mask process step on the storage wiring. Method for manufacturing an array substrate for use. The method of claim 22, And removing the protective layer corresponding to the pixel area in the third mask process step. The method of claim 23, wherein The gate insulating layer is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ). The method of claim 20, The second mask process step Stacking a gate insulating film, a pure amorphous silicon layer, an amorphous silicon layer containing impurities, and a metal layer on an entire surface of the substrate on which the gate electrode and the gate wiring are formed; Forming a photosensitive layer on the metal layer, and placing a mask including a transmissive part, a reflective part, and a transflective part on the substrate on which the photosensitive layer is formed; Irradiating light to the upper portion of the mask, exposing and developing a lower photosensitive layer to form a photosensitive pattern corresponding to one side of the pixel region perpendicular to the switching region and the gate wiring; Removing the metal layer, the impurity amorphous silicon layer, and the pure amorphous silicon layer exposed to the periphery of the photosensitive pattern; Ashing the photosensitive pattern to completely remove a photosensitive pattern of a portion in which only a part corresponding to the transflective portion of the mask is developed to expose a lower metal layer; Removing the metal layer exposed to the periphery of the photosensitive pattern, and exposing an underlying impurity amorphous silicon layer; Forming a source and drain electrode, a data line, a first semiconductor pattern under the source and drain electrode, and a second semiconductor pattern under the data line by removing the photosensitive pattern. Method of manufacturing array substrate for liquid crystal display device.