KR20050108732A - Test apparatus for semiconductor memory and method therefore - Google Patents

Abstract

The present invention relates to a semiconductor memory test apparatus and a test method. The memory test apparatus according to the present invention includes a clock generator for generating a predetermined test clock signal, and selecting the memory cells in response to a clock signal of the clock generator. An address generator for sequentially generating an address signal and a data signal to maintain a first logical state in a first section and a second logical state in a second section in response to a clock signal of the clock generator. A clock signal of the clock generator is generated in a section in which a data signal generator and a data signal in the data signal generator transition from a first logic state to a second logic state or from a second logic state to a first logic state. It is characterized in that it comprises a clock control unit for controlling not to. According to the present invention, it is possible to test to prevent or minimize the failure while increasing the clock speed.

Description

Test apparatus for semiconductor memory and method therefore

The present invention relates to a test apparatus and a test method of a semiconductor memory, and more particularly, to a test apparatus and a test method of a semiconductor memory for testing in a short time.

In general, semiconductor memory devices such as DRAM and SRAM are becoming smaller and more highly integrated. This is made possible by the development of semiconductor memory device technology and circuit technology. Due to the development of the semiconductor memory device technology and the circuit technology, the design rules of the circuits become smaller and smaller, so that a larger number of memory cells are arranged in a small area.

Such memory cells may fail due to various reasons. In order to detect such a failure, a "burn-in test" is performed in the manufacturing process of such a memory cell. The burn-in test is a method of repeatedly performing a write operation in a state of high voltage and high temperature. And burn-in tests are usually performed in a packaged state. That is, the integrated circuit product performs an electrical test of the chip in the wafer state, then packages only the good chip and performs "burn in" in the package state. This burn-in test is called "Package Burn-in" (PBI).

However, the package burn-in has a problem in that the burn-in time increases due to the increase in the degree of integration of the integrated circuit. As integrated circuits become more versatile and multi-pin, socket density per burn-in board is reduced, which leads to a decrease in productivity. In addition, there is a problem of reduced package yield due to the lack of proper initial failure at the wafer level. In order to solve this problem, various burn-in methods at the wafer level have been proposed.

One such method is wafer burn-in, one example of which is shown in FIGS.

 1 and 2 are schematic diagrams for explaining a test method of a conventional wafer burn-in, Figure 3 is an operation timing diagram for explaining the test method of Figs.

  Hereinafter, a conventional test method will be described according to the operation timing diagram of FIG. 3 with reference to FIGS. 1 and 2.

As shown in FIGS. 1 and 2, word lines W / L and bit lines B / L are connected to a memory cell array including a plurality of cells arranged in rows and columns. . In FIG. 1, the test is performed by writing the data "0" to the memory cell, and in FIG. 2, the test is performed by writing the data "1" to the memory cell.

As shown in FIG. 3, as the clock signal CLK is generated, an address signal is generated so that the word lines W / L0, W / L2, and W / Ln-1 are sequentially selected, and the bit line B is selected. A signal corresponding to data "0" is carried on / L, BLb). Therefore, data is written to the selected cells. Data is continuously written through the word lines W / L that are sequentially selected. When data "0" is written to the last word line W / Ln-1, the data "0" is opposite to the data "0". The data " 1 ", which is data, is written.

The conventional test apparatus and the test method described above are one bit in one clock due to the loading capacitance of the bit line due to the increase in the size of the memory cell array when the clock speed is increased to reduce the burn-in test time. Difficulties arise in converting data on a line to opposite data. Accordingly, when writing the data of the opposite side, as shown in FIG. 3, a fail 20 is caused.

Therefore, in order to solve this problem, conventionally, the clock speed is slowed to prevent such a failure. However, due to the high integration of semiconductor memories, reducing test time has become an important problem, and thus, a method of preventing a fail while increasing a clock speed has been required.

Accordingly, it is an object of the present invention to provide a test apparatus and a test method that can overcome the problems of the prior art.

Another object of the present invention is to provide a test apparatus and a test method capable of preventing or minimizing a failure due to a test while having a high clock speed for a test.

Still another object of the present invention is to provide a test apparatus and a test method which can reduce the testing time required for testing.

According to an aspect of the present invention for achieving some of the technical problems described above, a test apparatus for a semiconductor memory according to the present invention includes a clock generator for generating a predetermined test clock signal, and a clock signal of the clock generator. An address generator for sequentially generating an address signal for selecting the memory cells in response to the second signal; and a first logic state in a first section and a second logic state in a second section in response to a clock signal of the clock generator. In the data signal generating section for generating a data signal to maintain the data signal, and the section in which the data signal of the data signal generating section transitions from the first logic state to the second logic state or from the second logic state to the first logic state And a clock controller for controlling the clock signal of the clock generator not to be generated. The test may be a wafer burn-in test.

According to another aspect of the present invention for achieving some of the above technical problem, a test method of a semiconductor memory according to the present invention, generating a predetermined clock signal, and selecting the memory cells in response to the clock signal Generating an address signal, generating a data signal to maintain a first logical state in a first section in response to the clock signal, and in a section in which the data signal transitions from a first logical state to a second logical state; And controlling a clock signal not to be generated, and generating a data signal to maintain a second logic state in a second section in response to the clock signal.

The first logical state may be a state of data '0', and the first interval may be a period in which data '0' is sequentially written to the memory cells, and the second logical state is a state of data '1' The second section may be a section in which data '1' is sequentially written to the memory cell.

According to the apparatus and method configuration of the present invention, the clock speed is high, thereby reducing the testing time and preventing or minimizing the failure due to the testing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

4 is a block diagram of a test apparatus of a semiconductor memory according to an embodiment of the present invention.

As shown in FIG. 4, a test apparatus for a semiconductor memory according to an embodiment of the present invention includes a clock generator 110, an address signal generator 120, a data signal generator 130, and a clock controller 140. It is configured to include.

The clock generator 140 is a wafer burn-in clock generator and applies a clock signal WCLK to the address signal generator 120 and the data signal generator 130 in response to an external clock signal CLK.

The address signal generator 120 generates an address signal for sequentially selecting the memory cells in the memory cell array in response to the clock signal WCLK applied from the clock generator 110.

The data signal generator 130 may include a first signal in a first section (eg, a section in which even word lines are sequentially selected) in response to a clock signal WCLK applied from the clock generator 110. The second logical state (e.g., data) is maintained in one logical state (e.g., data "0" state) and in the second section (e.g., when an odd word line is sequentially selected). Generate a data signal to maintain " 1 " state.

In the clock controller 140, the data signal of the data signal generator 130 transitions from the first logic state to the second logic state or from the second logic state to the first logic state. The control signal HOLD is generated to control the clock signal WCLK of the clock generator 110 not to be generated, that is, to maintain the hold state.

5 illustrates an operation timing diagram of FIG. 4.

Hereinafter, an operation of the semiconductor memory test apparatus according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5.

First, the clock signal WCLK is generated through the wafer burn-in test clock generator 110 in response to the external clock signal CLK.

The address signal is generated by the address signal generator 120 in response to the clock signal WCLK generated by the clock generator 110. Specific memory cells are sequentially selected by the address signal.

In addition, the data (eg, having a first logic state in the bit line) by the data signal generated by the data signal generator 130 in response to the clock signal WCLK generated by the clock generator 110 (for example, Data "0") is carried.

As the first section is sequentially selected by the address signal, data “0” is written to the selected memory cells.

When the write operation for the first section is finished, the writing operation for the second section is started. Here, in the second section, the write operation of data (for example, data "1") opposite to the data of the first section is performed.

There is a section 200 where a data transition must be made on the bit line. In the related art, the clock speed has been slowed to prevent a failure. However, in the present invention, the clock generation occurs while the data transition occurs through the clock controller 140. The control signal HOLD is generated to prevent the clock signal WCLK of the unit 110 from being generated.

Therefore, while reducing test time, there is an effect that can prevent or minimize the failure.

When the data transition is completely made on the bit lines B / L and B / Lb, the clock generator 110 generates a clock again, and thus data (eg, data "1") during the second period. Write operation is performed.

 The wafer burn-in test is performed by performing the above operation.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention. For example, it may be apparent that in other cases, there may be a change in the order of test operations or a change in the write order of data, and the internal components of the circuit may be replaced with other equivalent elements.

As described above, according to the present invention, it is possible to press the test time by increasing the clock speed, and it is possible to prevent or minimize the fail that may be generated by increasing the clock speed.

1 and 2 are block diagrams illustrating a test method of a conventional general memory cell.

3 is an operation timing diagram of FIGS. 1 and 2;

4 is a block diagram of a test apparatus according to an embodiment of the present invention.

5 is an operation timing diagram of FIG. 4.

* Description of the symbols for the main parts of the drawings *

110: clock generator 120: address signal generator

130: data signal generator 140: clock controller

Claims (8)

In a semiconductor memory test apparatus for sequentially testing a plurality of memory cells constituting a memory cell array: A clock generator for generating a predetermined test clock signal; An address generator for sequentially generating an address signal for selecting the memory cells in response to a clock signal of the clock generator; A data signal generator for generating a data signal in response to a clock signal of the clock generator to maintain a first logical state in a first section and a second logical state in a second section; A clock controller which controls a clock signal of the clock generator not to be generated in a section in which a data signal of the data signal generator transitions from a first logic state to a second logic state or from a second logic state to a first logic state Semiconductor memory test apparatus, characterized in that provided. The method of claim 1,  And the test is a wafer burn-in test. The method of claim 2, And the first logical state is a state of data '0', and the first section is a section in which data '0' is sequentially written to the memory cell. The method of claim 3, And the second logical state is a state of data '1', and the second section is a section in which data '1' is sequentially written to the memory cell. In the semiconductor memory test method for sequentially testing a plurality of memory cells constituting a memory cell array: Generating a predetermined clock signal; Generating an address signal for selecting memory cells in response to the clock signal, and generating a data signal to maintain a first logical state in a first section in response to the clock signal; Controlling the clock signal not to be generated in a section in which the data signal transitions from a first logic state to a second logic state; And And in response to the clock signal, generating a data signal to maintain a second logical state in a second section. The method of claim 5,  Wherein the test is a wafer burn-in test. The method of claim 6, The first logic state is a state of data '0', and the first section is a section in which data '0' is sequentially written to the memory cells. The method of claim 7, wherein And wherein the second logical state is a state of data '1' and the second period is a section in which data '1' is sequentially written to the memory cell.