KR20050102763A - Duty cycle correction circuit having a delay locked loop correcting automatically operation frequency range according to input signal and method thereof - Google Patents

Abstract

A duty cycle correction circuit having a delay lock loop for automatically varying an operating frequency range in accordance with an input signal and a method thereof are disclosed. The duty cycle correction circuit includes a mode detector in a delay lock loop to automatically vary the operating frequency range in accordance with the frequency of the input clock signal. Accordingly, the duty cycle correction circuit may generate an output clock signal that accurately corrects the duty cycle up to a high frequency region even when the frequency of the input clock signal changes.

Description

Duty cycle correction circuit having a delay locked loop correcting automatically operation frequency range according to input signal and method

The present invention relates to a duty cycle correction circuit, and more particularly, to a duty cycle correction circuit and a method for widening an operating frequency range.

In most systems such as semiconductor memory devices such as Rambus Dynamic Random Access Memory (RDRAM) and Double Data Rate (DDR) memory, systems that process video signals, audio signals, or communication systems, a DLL (Delay) is used to produce an accurate clock signal. A duty cycle correction circuit using a locked loop is employed. The duty cycle correction circuit processes the input clock signal to generate a new clock signal having a certain duty factor. The duty factor is a value expressed as a percentage (%) of a clock signal divided by the period of the clock signal by the pulse width of the logic high state. Typically, the clock required by the system is 50% duty factor, but a clock signal with a different duty factor may be used in certain circuits. To ensure normal operation of the system, the duty factor of the new clock signal generated by the duty cycle correction circuit must be constant.

A typical duty cycle correction circuit includes a delay locked loop (DLL) and a phase mixer. In the delay lock loop DLL, a plurality of reference clock signals having different phases are generated from an input clock signal, and a phase synthesizer generates a new clock signal having a duty factor of 50% using the plurality of reference clock signals. .

In a typical duty cycle correction circuit, the delay lock loop (DLL) operates in a constant frequency band. That is, the delay lock loop normally generates reference clock signals corrected for the input clock signal with respect to the input clock signal within a predetermined frequency. Therefore, in a typical duty cycle correction circuit, since a locking range of the input clock signal is restricted, a normal clock signal having a duty factor of 50% is generated when the frequency of the input clock signal is input over the range. The problem is that you can't.

Accordingly, an aspect of the present invention is to provide a duty cycle correction circuit and a method including a delay lock loop which automatically changes an operating frequency range according to an input signal.

A duty cycle correction circuit according to the present invention for achieving the above technical problem is characterized by comprising a delay lock loop and a phase synthesis circuit. The delay lock loop generates a plurality of delay signals having different phases within a phase difference range determined according to a frequency of an input clock signal. The phase synthesis circuit generates an output clock signal by correcting a duty cycle of the input clock signal using the delay signals. The phase combining circuit generates an output clock signal having a duty factor of 50%.

The delay lock loop is characterized by having a plurality of delay cells, a phase detector, a counter, a digital-to-analog converter, and a mode detector. The plurality of delay cells delay the input clock signal by a predetermined time in response to the current control signal and the mode control signal to generate each of the delay signals. The phase detector detects a phase difference between any one of the delay signals and the input clock signal, and generates a phase difference signal corresponding thereto. The counter generates a digital count value proportional to the phase difference in response to the phase difference signal. The digital-analog converter converts the digital count value into an analog signal and outputs the conversion result as the current control signal. The mode detector checks a least significant bit (LSB) of the digital count value and outputs the mode control signal. Each of the input clock signal, the delay signals, and the output clock signal is a set signal including an inverted signal.

Each of the plurality of delay cells is characterized by having a delay circuit and a differential amplifier. The delay circuit receives the set signal of either the input clock signal or the delay signals as an input set signal, and outputs the input set signal by a predetermined time delay. The differential amplifier uses the input set signal and the delayed input set signal to generate each of the delay signals within a different phase difference range according to the logic state of the mode control signal. The differential amplifier generates the delay signal in a low frequency region of the input clock signal when the mode control signal is in a first logic state, and generates the delay signal in the high frequency region of the input clock signal when the mode control signal is in a second logic state. And generating a delay signal.

 The counter is characterized in that when the phase difference reaches a threshold of the range of phase differences by the delay cells, the LSB generates a digital count value which is either a first logic state or a second logic state. The mode detector generates a mode control signal of a second logic state value when the LSB of the digital count value continuously has a first logic state for N cycles of the input clock signal, and the LSB of the digital count value is Generating a mode control signal of the first logic state when the second logic state is continuously present during the N cycles of the input clock signal. N is 3, It is characterized by the above-mentioned.

 The mode detector includes a first DQ flip-flop, a second DQ flip-flop, a third DQ flip-flop, a NAND logic, a NOR logic, a PMOSFET, an NMOSFET, a first inverter, and a second inverter. The first DQ flip-flop receives and outputs the LSB of the digital count value according to the input clock signal. The second DQ flip-flop receives and outputs an output of the first DQ flip-flop according to the input clock signal. The third DQ flip-flop receives and outputs the output of the second DQ flip-flop according to the input clock signal. The NAND logic receives outputs of the first DQ flip-flop, the second DQ flip-flop, and the third DQ flip-flop, performs NAND logic, and outputs a result. The NOR logic receives the outputs of the first DQ flip-flop, the second DQ flip-flop, and the third DQ flip-flop, performs NOR logic, and outputs a result. In the PMOSFET, a gate terminal receives a result of performing the NAND logic, a source terminal is connected to a first power supply, and a drain terminal is connected to an output node. The NMOSFET has a gate terminal receiving a result of performing the NOR logic, a source terminal is connected to a second power supply, and a drain terminal is connected to the output node. The first inverter inverts the signal of the output node and outputs the mode control signal. The second inverter inverts the output of the first inverter and transfers it to the output node.

According to another aspect of the present invention, there is provided a duty cycle correction method of a clock signal, the method including: generating a plurality of delay signals having different phases within a phase difference range determined according to a frequency of an input clock signal; And generating an output clock signal by correcting a duty cycle of the input clock signal using the delay signals. The output clock signal is characterized in that the duty factor is 50%.

The generating of the plurality of delay signals may include detecting a phase difference between any one of the delay signals and the input clock signal, and generating a corresponding phase difference signal; Generating a digital count value proportional to the phase difference in response to the phase difference signal; Converting the digital count value into an analog signal and outputting the conversion result as a current control signal; Checking a LSB of the digital count value and outputting a mode control signal; And generating each of the delay signals by delaying the input clock signal by a predetermined time in response to the current control signal and the mode control signal. Each of the input clock signal, the delay signals, and the output clock signal is a set signal including an inverted signal.

The generating of each of the delay signals may include receiving the set signal of the input clock signal or the delay signals as an input set signal, and outputting the input set signal by a predetermined time delay; And generating each of the delay signals within a different phase difference range according to a logic state of the mode control signal by using the input set signal and the delayed input set signal.

When the mode control signal is in a first logic state, the delay signal is generated in a low frequency region of the input clock signal. When the mode control signal is in a second logic state, the delay signal is generated in a high frequency region of the input clock signal. It is characterized by. When the phase difference reaches a limit of the phase difference range by the delay cells, a digital count value is generated in which the LSB is either a first logic state or a second logic state.

When the LSB of the digital count value continuously has the first logic state for N cycles of the input clock signal, a mode control signal of the second logic state value is generated, and the LSB of the digital count value continuously the input clock When having a second logic state during N cycles of the signal, the mode control signal of the first logic state is generated. N is characterized in that 3.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a duty cycle correction circuit 100 according to an embodiment of the present invention. Referring to FIG. 1, the duty cycle correction circuit 100 includes a delay locked loop (DLL) 110 and a phase mixing circuit 120.

The delay lock loop 110 delays the input clock signals K0 and K0B to generate a plurality of delay signals K1 / K1B to K4 / K4B having different phases. In particular, the delay lock loop 110 generates a plurality of delay signals K1 / K1B to K4 / K4B within a phase difference range determined according to the frequencies of the input clock signals K0 and K0B. For example, the threshold of the phase difference range in the low frequency region and the threshold of the phase difference range in the high frequency region of the input clock signals K0 and K0B are different from each other. A plurality of delay signals K1 / K1B to K4 / K4B are generated by dividing the low frequency region and the high frequency region. The input clock signals K0 and K0B and the delay signals K1 / K1B to K4 / K4B are assumed to be set signals including inverted signals, as shown in FIG. 1. That is, K0B is an inversion signal of K0 and K1B is an inversion signal of K1. The same applies to the remaining delay signals K2 / K2B to K4 / K4B. Operation of the delay lock loop 110 will be described in detail with reference to FIG. 2.

The phase synthesis circuit 120 generates output clock signals CKO and CKOB by correcting duty cycles of the input clock signals K0 and K0B using the delay signals K1 / K1B to K4 / K4B. . That is, the phase synthesis circuit 120 generates output clock signals CKO and CKOB having a duty factor of 50%. The output clock signals CKO and CKOB also include inverted signals. That is, CKOB is an inverted signal of CKO.

FIG. 2 is a detailed block diagram of the delay lock loop 110 of FIG. 1. Referring to FIG. 2, the delay lock loop 110 includes a delay unit 210, a phase detector 220, a counter 230, a digital-analog converter 240, and a mode. The detector 250 is provided.

The delay unit 210 includes a plurality of delay cells 211 to 214 to respond to a current control signal input from the digital-analog converter 240 and a mode control signal MODCNT input from the mode detector 250. Each of the delayed signals K1 / K1B to K4 / K4B is generated by delaying the input clock signals K0 and K0B by a predetermined time δ. The number of the plurality of delay cells 211 to 214 is illustrated as four, but the present invention is not limited thereto and may be designed in different numbers according to the purpose of the circuit. When the number of the plurality of delay cells 211 to 214 is four, the phase difference δ between the delay signals K1 / K1B to K4 / K4B is equal to T / 8 as shown in FIG. 3. Corresponding. Here, T is one cycle time (cycle) of the input clock signals K0 and K0B.

By the operations of the plurality of delay cells 211 to 214 under the control of the mode control signal MODCNT, the delay signals K1 / K1B to K4 / in the low frequency region of the input clock signals K0 and K0B. The limit value of the phase difference range of K4B) and the limit value of the phase difference range of the delay signals K1 / K1B to K4 / K4B in the high frequency region are different. This will be described in more detail with reference to FIG. 4, which shows a specific circuit of the plurality of delay cells 211 ˜ 214.

The phase detector 220 detects a phase difference between any one of the delay signals K1 / K1B to K4 / K4B and the input clock signals K0 and K0B and generates a corresponding phase difference signal. In particular, as shown in FIG. 3, the phase detector 220 detects a phase difference between K4B of the last delayed signal and K0 of the input clock signals K0 and K0B. In normal operation, these two signals are in phase.

The counter 230 generates a digital count value proportional to the phase difference in response to the phase difference signal. The counter 230 may be an 8-bit counter 230, and may be a counter 230 having a different number of bits depending on the circuit purpose.

The digital-analog converter 240 converts the digital count value into an analog signal and outputs the conversion result as the current control signal. When the counter 230 is an 8-bit counter 230, the digital-to-analog converter 240 converts an 8-bit digital signal into an analog signal.

The mode detector 250 checks a least significant bit (LSB) of the digital count value and outputs the mode control signal MODCNT. When the phase difference reaches a limit of the phase difference range by the delay cells 211 to 214, the counter 230 determines whether the LSB is in a first logic state (logical low state) or a second logic state (logical high state). It generates one digital count value. The mode detector 250 checks this to indicate the first mode corresponding to the low frequency region of the input clock signals K0 and K0B and the second mode corresponding to the low frequency region of the input clock signals K0 and K0B. The mode control signal MODCNT is generated and output. Operation of the mode detector 250 is described in more detail with reference to FIG. 5.

4 is a detailed circuit diagram of the delay cells 211 ˜ 214 of FIG. 2. Referring to FIG. 4, each of the delay cells 211 to 214 includes a delay circuit 215 and a differential amplifier 216.

The delay circuit 215 of 211 of the delay cells 211 to 214 of FIG. 2 receives the set signals K0 and K0B of the input clock signals K0 and K0B as the input set signals IN and INB. Each of the input set signals is output after a predetermined time delay (δ). The delay circuit 215 provided in each of 212 to 214 of the delay cells 211 to 214 of FIG. 2 receives a delay signal output from a delay cell of a previous stage as an input set signal, and receives the input set signal for a predetermined time ( δ) Delayed output. Delaying the input set signal for a predetermined time (δ) in each of the delay cells 211 to 214 may include a phase difference between the delay signals K1 / K1B to K4 / K4B due to an interaction with the differential amplifier 216. This is to make δ) become T / 8.

The differential amplifier 216 provided in each of the delay cells 211 to 214 of FIG. 2 uses the input set signal and the delayed input set signals DIN and DINB to transmit the delay signals K1 / K1B to. Each of K4 / K4B). As shown in FIG. 4, the differential amplifier 216 has a structure in which two amplifiers are mixed. That is, the differential amplifier 216 is an output node of an amplifier composed of N-type MOSFETs (metal-oxide-semiconductors) M4, M5, and M6 that operate by receiving the delayed input set signals DIN and DINB. An output node of an amplifier consisting of N-type MOSFETs (M1, M2, M3) and resistors R, R2 that operate by receiving (OUT, OUTB) and the input set signals (IN, INB) as inputs. (OUT, OUTB) has a shared structure. Here, M3 and M6 operate as a current source whose current amount is determined by predetermined bias voltages BIAS1 and BIAS2, and the resistors R1 and R2 apply a constant voltage to a gate electrode of an N-type or P-type MOSFET. It may be formed into a structure. The differential amplifier 216 receives the input set signal IN by the delayed voltage of the delayed input set signals DIN and DINB delayed by T / 8 when the input set signals IN and INB are input. Generates output set signals OUT and OUTB having a phase difference of INB) by T / 8.

In particular, the differential amplifier 216 further includes N-type MOSFETs M7, M8, and M9 that receive the mode control signal MODCNT. Accordingly, the differential amplifier 216 generates each of the delay signals K1 / K1B to K4 / K4B within a different phase difference range according to the logic state of the mode control signal MODCNT.

5 is a detailed circuit diagram of the mode detector 250 of FIG. 2. Referring to FIG. 5, the mode detector 250 includes a first DQ flip-flop 251, a second DQ flip-flop 252, a third DQ flip-flop 253, and a NAND (negative AND) ) Logic 254, NOR (negative-OR) logic 255, PMOSFET (P-type MOSFET) 256, NMOSFET (N-type MOSFET) 257, first inverter 258, and second inverter 259. Here, it is preferable that the number of flip-flops 251 to 253 connected in series is three, but the number may be variously designed according to the purpose of the circuit designer.

The first DQ flip-flop 251, the second DQ flip-flop 252, and the third DQ flip-flop 253 may cycle through the input clock signals K0 and K0B in the same manner as the operation of a general DQ flip-flop. Each time, the logic state of the signal input at the rising edge is output. That is, the first DQ flip-flop 251 receives and outputs the LSB of the digital count value input from the counter 230 according to the input clock signals K0 and K0B. The second DQ flip-flop 252 receives and outputs the output of the first DQ flip-flop 251 according to the input clock signals K0 and K0B. The third DQ flip-flop 253 receives and outputs the output of the second DQ flip-flop 252 according to the input clock signals K0 and K0B. The NAND logic 254 receives the outputs of the first DQ flip-flop 251, the second DQ flip-flop 252, and the third DQ flip-flop 253, and performs NAND logic. Outputs The NOR logic 255 receives the outputs of the first DQ flip-flop 251, the second DQ flip-flop 252, and the third DQ flip-flop 253, and performs NOR logic. Outputs A gate terminal of the PMOSFET 256 receives a result of performing the NAND logic, a source terminal of the PMOSFET 256 is connected to a first power supply VDD, and a drain terminal of the PMOSFET 256 is connected to an output node. The NMOSFET 257 has a gate terminal receiving the result of performing the NOR logic, a source terminal connected to a second power supply VSS, and a drain terminal connected to the output node. The first inverter 258 inverts the signal of the output node and outputs the mode control signal MODCNT. The second inverter 259 inverts the output of the first inverter 258 and transfers it to the output node.

According to the structure of the mode detector 250 as shown in FIG. 5, the mode control signal MODCNT has a first logic state during which the LSB of the digital count value is continuously N (3) cycles of the input clock signals K0 and K0B. Has a second logical state value. In addition, the mode control signal MODCNT has a first logic state value when the LSB of the digital count value continuously has a second logic state during N (3) cycles of the input clock signals K0 and K0B. .

When the phase difference detected by the phase detector 220 reaches a limit of the phase difference range by the delay cells 211 to 214, the LSB of the digital count value output from the counter 230 of FIG. The value of either the first logic state or the second logic state is maintained during the N (3) cycles of the input clock signals K0, K0B. When the phase difference does not reach the limit of the phase difference range by the delay cells 211 to 214, the digital count value output from the counter 230 alternately generates a first logic state and a second logic state. It does not hold either state during the N (3) cycles of the input clock signals K0, K0B. The mode detector 250 configured as shown in FIG. 5 checks the first mode corresponding to the low frequency region of the input clock signals K0 and K0B and the second mode corresponding to the low frequency region of the input clock signals K0 and K0B. The mode control signal MODCNT for indicating a mode is generated and output.

6 is a diagram for describing an operation of delay cells 211 ˜ 214. Referring to FIG. 6, in the first mode corresponding to the first logic state value of the mode control signal MODCNT of FIG. 5, the delay cells 211 to 214 of FIG. 2 operate in the low frequency region. In addition, in the second mode corresponding to the second logic state value of the mode control signal MODCNT of FIG. 5, the delay cells 211 to 214 of FIG. 2 operate in the high frequency region. That is, the differential amplifier 216 of FIG. 4 generates the delay signal in the low frequency region of the input clock signals K0 and K0B when the mode control signal MODCNT is in the first logic state and controls the mode. When the signal MODCNT is in the second logic state, the delay signal is generated in the high frequency region of the input clock signals K0 and K0B.

For example, in FIG. 6, when the delay cells 211 to 214 operate in the first mode, when the phase difference range is between t1 to t2 and reaches the lowest threshold t1, the counter 230 is digital. It outputs "00000000" as the count value to indicate that it corresponds to the high frequency range. When such a digital count value is maintained for more than N (3) cycles, the mode control signal MODCNT has a second logic state value, whereby M7, M8, and M9 of FIG. 4 become active, causing the delay. The cells 211-214 operate in the second mode. In the second mode, the delay cells 211 to 214 operate in a phase difference range of t3 to t4, which indicates that the delay cells 211 to 214 operate at a delay amount smaller by Δt than in the first mode, as shown in FIG. 6. In the second mode, when the maximum threshold t4 is reached, the counter 230 outputs "11111111" as a digital count value to indicate that it corresponds to the low frequency region. Accordingly, when the LSB of the digital count value is maintained for at least N (3) cycles in the state of the second logic state, the mode control signal MODCNT has the first logic state value, and accordingly, M7 and M8 of FIG. M9 is turned off, and the delay cells 211 to 214 operate in the first mode.

As described above, the duty cycle correction circuit 100 according to the exemplary embodiment of the present invention includes a mode detector 250 in the delay lock loop 110, and accordingly to the frequency of the input clock signals K0 and K0B. To change the operating frequency range. Accordingly, the duty cycle correction circuit 100 may generate output clock signals CKO and CKOB that accurately correct the duty cycle up to a high frequency region even when the frequencies of the input clock signals K0 and K0B change.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the duty cycle correction circuit according to the present invention accurately corrects the duty cycle even in the high frequency region of the input clock signal. Therefore, when applied to a semiconductor memory device, a video / audio system, or a communication system, there is an effect that can contribute to the stable operation of the system.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a block diagram illustrating a duty cycle correction circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the delay lock loop of FIG. 1.

3 is an example illustrating a waveform of signals of FIG. 2.

4 is a detailed circuit diagram of delay cells of FIG. 2.

FIG. 5 is a detailed circuit diagram of the mode detector of FIG. 2.

6 is a diagram for describing an operation of delay cells.

Claims (19)

A delay lock loop for generating a plurality of delay signals having different phases within a phase difference range determined according to a frequency of an input clock signal; And And a phase synthesizing circuit for generating an output clock signal corrected for the duty cycle of the input clock signal using the delay signals. The method of claim 1, wherein the delay lock loop, A plurality of delay cells for generating each of the delay signals by delaying the input clock signal by a predetermined time in response to a current control signal and a mode control signal; A phase detector for detecting a phase difference between any one of the delay signals and the input clock signal and generating a phase difference signal corresponding thereto; A counter for generating a digital count value proportional to the phase difference in response to the phase difference signal; A digital-analog converter for converting the digital count value into an analog signal and outputting the conversion result as the current control signal; And And a mode detector for outputting the mode control signal by checking a least significant bit (LSB) of the digital count value. 3. The duty cycle correction circuit of claim 2, wherein each of the input clock signal, the delay signals, and the output clock signal is a set signal including an inverted signal. The method of claim 3, wherein each of the plurality of delay cells, A delay circuit which receives the set signal of the input clock signal or the delay signals as an input set signal, and delays and outputs the input set signal for a predetermined time; And And a differential amplifier using each of the input set signal and the delayed input set signal to generate each of the delay signals within a different phase difference range according to a logic state of the mode control signal. Circuit. The method of claim 4, wherein the differential amplifier, When the mode control signal is in a first logic state, the delay signal is generated in a low frequency region of the input clock signal. When the mode control signal is in a second logic state, the delay signal is generated in a high frequency region of the input clock signal. Duty cycle correction circuit, characterized in that. The method of claim 2, wherein the counter, And the LSB generates a digital count value that is either of a first logic state or a second logic state when the phase difference reaches a threshold of the phase difference range by the delay cells. The method of claim 2, wherein the mode detector, When the LSB of the digital count value continuously has a first logic state for N cycles of the input clock signal, a mode control signal of the second logic state value is generated, and the LSB of the digital count value continuously the input clock. And generating a mode control signal in the first logic state when the second logic state is in the N cycles of the signal. The method of claim 7, wherein N is, Duty cycle correction circuit, characterized in that 3. The method of claim 2, wherein the mode detector, A first DQ flip-flop for receiving and outputting the LSB of the digital count value according to the input clock signal; A second DQ flip-flop for receiving and outputting an output of the first DQ flip-flop according to the input clock signal; A third DQ flip-flop for receiving and outputting an output of the second DQ flip-flop according to the input clock signal; NAND logic to receive outputs of the first DQ flip-flop, the second DQ flip-flop, and the third DQ flip-flop, perform NAND logic, and output a result; NOR logic to receive outputs of the first DQ flip-flop, the second DQ flip-flop, and the third DQ flip-flop, perform NOR logic, and output a result; A gate terminal receives the result of performing the NAND logic, a source terminal is connected to a first power supply, and a drain terminal is connected to an output node; A gate terminal receives the result of performing the NOR logic, a source terminal is connected to a second power supply, and a drain terminal is connected to the output node; A first inverter outputting the mode control signal by inverting the signal of the output node; And And a second inverter for inverting the output of the first inverter and transferring the inverted output to the output node. The method of claim 1, wherein the phase synthesis circuit, A duty cycle correction circuit for producing an output clock signal having a duty factor of 50%. Generating a plurality of delay signals having different phases within a phase difference range determined according to a frequency of an input clock signal; And And generating an output clock signal corrected for the duty cycle of the input clock signal by using the delay signals. The method of claim 11, wherein the generating of the plurality of delay signals comprises: Detecting a phase difference between any one of the delay signals and the input clock signal, and generating a phase difference signal corresponding thereto; Generating a digital count value proportional to the phase difference in response to the phase difference signal; Converting the digital count value into an analog signal and outputting the conversion result as a current control signal; Checking a LSB of the digital count value and outputting a mode control signal; And And delaying the input clock signal by a predetermined time in response to the current control signal and the mode control signal to generate each of the delay signals. The method of claim 12, wherein each of the input clock signal, the delay signals, and the output clock signal is a set signal including an inverted signal. The method of claim 13, wherein generating each of the delay signals comprises: Receiving the set signal of the input clock signal or the delay signals as an input set signal, and outputting the input set signal by a predetermined time delay; And And using the input set signal and the delayed input set signal to generate each of the delay signals within a different phase difference range according to a logic state of the mode control signal. Cycle compensation method. 15. The high frequency region of claim 14, wherein the delay signal is generated in a low frequency region of the input clock signal when the mode control signal is in a first logic state, and when the mode control signal is in a second logic state. And a delay signal is generated in the duty cycle correction method of the clock signal. 13. The clock signal according to claim 12, wherein when the phase difference reaches a limit of the phase difference range by the delay cells, a digital count value is generated in which an LSB is either a first logic state or a second logic state. Duty cycle correction method. 13. The method of claim 12, wherein when the LSB of the digital count value has a first logic state continuously for N cycles of the input clock signal, a mode control signal of a second logic state value is generated, and the LSB of the digital count value And a mode control signal of a first logic state is generated when N is continuously in a second logic state during N cycles of the input clock signal. The method of claim 17, wherein N is, 3. The duty cycle correction method of the clock signal characterized by the above-mentioned. The method of claim 11, wherein the output clock signal, A duty cycle correction method for a clock signal, wherein the duty factor is 50%.