KR100821577B1 - Duty Cycle Correction Apparatus - Google Patents

Abstract

The duty cycle correction apparatus according to the present invention includes: period sensing means for converting one period of the first external signal into a digital code and outputting the digital code; A control signal generator for receiving the digital code and outputting a half cycle control signal; And a half period delay unit delaying the first external signal by a half period of the first external signal and outputting the second external signal as a second external signal in response to the half period control signal, wherein the control signal generator shifts the digital code. A shift register; And a decoding unit for decoding the shifted digital code and outputting the plurality of half-cycle control signals.

Digital code, half-cycle control signal

Description

Duty Cycle Correction Apparatus

1 is a block diagram showing a duty cycle correction apparatus according to the present invention,

FIG. 2 is a block diagram illustrating a half period delay signal generator shown in FIG. 1; FIG.

3 is a circuit diagram illustrating a half cycle delay unit illustrated in FIG. 2;

4 is a block diagram illustrating another example of the half-cycle delay signal generator shown in FIG. 1;

5 is a circuit diagram illustrating a clock signal recovery unit illustrated in FIG. 1;

6 is a timing diagram of a duty cycle correction device according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: period detection unit 200: half cycle delay signal generation unit

300: clock signal recovery unit

The present invention relates to a duty cycle correction device, and more particularly, a period of an external clock signal is output as a digital code by using a time to digital converter (hereinafter referred to as a TDC), and the digital code is The present invention relates to a duty cycle correction device capable of reducing the cycle duration by correcting the duty cycle of the external clock signal by delaying the external clock signal by a half cycle.

It is very important that the duty cycle of the clock signal is accurately controlled in the semiconductor memory. In general, in a semiconductor memory, a clock signal having a duty cycle of 50% is mainly used. A 50% duty cycle means that a high level period and a low level period of the clock signal are the same. Therefore, in the semiconductor memory, the duty cycle correction device is used to generate a 50% clock signal of the duty cycle.

In general, the duty cycle correction apparatus serves to correct the duty cycle of an external signal that is distorted or distorted by an internal delay circuit or outputs the internal signal as an internal signal.

The conventional duty cycle correction device corrects the duty cycle of the distorted external signal by using the distorted external signal and the distorted external signal whose half cycle is delayed by the duty cycle, and the conventional duty cycle correction device inputs the external signal. In addition, since a complicated control circuit for calculating the half-cycle delay time of the external signal must be provided by itself, it takes up a lot of memory layout and increases current consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and by using a digital code corresponding to one cycle delay time of an external clock signal provided from a TDC, a simple control circuit for calculating the half cycle delay time is used. The technical problem is to provide a duty cycle correction device capable of increasing reliability, reducing current consumption due to a simplified circuit, and implementing it in a small area.

According to an aspect of the present invention, there is provided a duty cycle correcting apparatus, comprising: period sensing means for converting and outputting a period of a first external signal into a digital code; A control signal generator for receiving the digital code and outputting a half cycle control signal; And a half period delay unit delaying the first external signal by a half period of the first external signal and outputting the second external signal as a second external signal in response to the half period control signal, wherein the control signal generator shifts the digital code. A shift register; And a decoding unit for decoding the shifted digital code and outputting the plurality of half-cycle control signals.

In addition, the duty cycle correction apparatus according to the present invention further includes a clock signal recovery means for receiving the first external signal and the second external signal and outputs a duty cycle correction signal.
The duty cycle correction apparatus according to the present invention includes: period sensing means for converting one period of the first external signal into a digital code and outputting the digital code; A first decoding unit decoding a higher bit of the digital code and outputting a first half period control signal; A second decoder configured to output a second half period control signal by decoding a lower bit minus the upper bit among the digital codes; A first delay unit delaying the first external signal in response to the first half-cycle control signal; And a second delay unit configured to delay an output signal of the first delay unit in response to the second half period control signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram showing a duty cycle correction apparatus according to the present invention.

The duty cycle correction device according to the present invention is a cycle detection unit 100 for converting a period of the first external signal CLK_IN input from the outside into a digital code (DIG_CD), in response to the digital code (DIG_CD) The half cycle delay signal generator 200 and the first external scene delay the first external signal CLK_IN by a half cycle of the first external signal CLK_IN and output the second external signal CLK_IN_DEL. The clock signal recovery unit 300 receives a call CLK_IN and the second external signal CLK_IN_DEL and outputs a duty cycle correction signal CLK_OUT.

The period sensing unit 100 includes a time-to-digital converter for converting a period of a signal into a digital code, so that a time corresponding to one period of the first external signal CLK_IN is converted into a predetermined bit. Output as digital code (DIG_CD).

Assuming that one period of the first external signal CLK_IN is 30 ns, and the period detecting unit 100 outputs 11110 which is a 5-bit digital code DIG_CD, the 11110 is 30 when converted to decimal. , The time corresponding to decimal 1 is 1ns. As the period detecting unit 100 has more bits of the digital code DIG_CD for the same time, the resolution of the period detecting unit 100 becomes higher and the resolution of the period detecting unit 100 becomes higher. Denotes the resolution of the duty cycle correction apparatus. In addition, a time corresponding to the decimal number 1 is referred to as td, and then the same as the delay time of each of the plurality of signal delay units 211 selected in the half-cycle control signal DEL_SEL shown in FIG. (211) Each one delay time is composed of td / 2.

FIG. 2 is a block diagram illustrating a half-cycle delay signal generator shown in FIG. 1.

The half-cycle delay signal generator 200 receives the digital code DIG_CD output from the period detector 100 and outputs a half-cycle control signal DEL_SEL and a half-cycle control signal. In response to the DEL_SEL, the half cycle delay unit 210 delays the first external signal CLK_IN by a half cycle of the first external signal CLK_IN and outputs the second external signal CLK_IN_DEL.

The control signal generator 230 may right-shift the digital code DIG_CD of a predetermined bit output by the period detector 100 by one bit and the shifted first shift register 231. And a decoding unit 233 which decodes a digital code and outputs a plurality of half-cycle control signals DEL_SEL.

Only one of the half-cycle control signals DEL_SEL is activated and output at a high level, and the other half-cycle control signals DEL_SEL are inactivated and output at a low level.

The period detector 100 outputs a 5-bit digital code DIG_CD <4: 0> corresponding to one period of the first external signal CLK_IN, and outputs the digital code DIG_CD <4: Assuming that the value of 0>) represents 11110, the control signal generator 230 will be described below.

The digital code DIG_CD <4: 0> corresponds to one period of the first external signal CLK_IN so that the digital code DIG_CD <4: 0> = 11110 is 1 bit through the shift register 231. When the bit shift is performed, 01111 corresponding to half of the digital code DIG_CD <4: 0> = 11110 is generated.

In other words, the shift register 231 shifts the 5-bit code 11110 (decimal = 30) by one bit to output 01111 (decimal = 15), thereby outputting the period-sensing unit 100. A digital code corresponding to a half cycle of the digital code DIG_CD is generated, and the decoding unit 233 decodes the shifted digital code 1111 to generate the half cycle control signal DEL_SEL <14: 0>.

In addition, the decoding unit 233 decodes the digital code DIG_CD <4: 0> = 11110 instead of receiving 1111, which is a half-cycle digital code shifted by the shift register 231, and decodes the half-cycle control signal DEL_SEL <. 30: 0>). In this case, as shown in FIG. 3, the delay time of each of the plurality of signal delay units 211 selected by the half-cycle control signal DEL_SEL is td / 2 instead of the time td corresponding to the decimal number 1. A delay unit having a delay time of is configured and used.

3 is a circuit diagram illustrating a half-cycle delay unit illustrated in FIG. 2.

The half-cycle delay unit 210 delays the signal transmitted from the previous stage by a predetermined time (td or td / 2) and then transfers the signal delay unit 211 and the plurality of half-cycle control signals DEL_SEL < N: 0>), the switching unit 213 determines the activation of the plurality of signal delay units 211.

The half period delay unit 210 sequentially delays the first external signal CLK_IN for a predetermined time (td or td / 2) in response to a plurality of the half period control signals DEL_SEL <N: 0>. The delay units 211 are connected to each other in series and vary the number of the signal delay units 211 for delaying the first external signal CLK_IN according to the half-cycle control signal DEL_SEL being activated.

That is, when converting the digital code (DIG_CD) of the predetermined bit into a decimal number, the signal delay unit 211 performs the first external signal () by the predetermined time (td or td / 2) indicated by decimal number 1. In order to delay the CLK_IN, the half-cycle delay unit 210 decodes the digital code DIG_CD to delay the signal delayed by the first external signal CLK_IN in response to the activated half-cycle control signal DEL_SEL. The number of parts 211 is adjusted.

The switching unit 213 includes a plurality of first NAND gates ND1 that receive the first external signal CLK_IN and the respective half-cycle control signals DEL_SEL <N: 0>, and combine and output the signals. do.

The signal delay unit 211 is a first inverter IV1 that inverts the output signals of the second NAND gate ND2 and the second NAND gate ND2 that receive the output signal of the first NAND gate ND1. The second NAND gate ND1 provided in the signal delay unit 211 at the foremost end receives an external power supply VDD from another input terminal, and the remaining signal delay unit 211 is received. The output signal of the signal delay unit 211 of the preceding stage is input to the other input terminal of the second NAND gate ND2 provided in the.

Although the signal delay unit 211 is implemented with the NAND gate ND2 and the inverter IV1 in the present invention, the signal delay unit 211 is implemented using other delay means instead of the NAND gate ND2 and the inverter IV1. It is also possible.

4 is a block diagram illustrating another example of the half-cycle delay signal generator shown in FIG. 1.

As shown in FIG. 4, the half-cycle delay signal generator 200 includes a higher level among signals output from the second shift register 250 and the second shift register 250 for shifting the digital code DIG_CD. A first decoder 260 to input a bit, a second decoder 270 to input a lower bit among the signals output from the second shift register 250, and a second output from the first decoder 260. In response to a first delay unit 280 for delaying the first external signal CLK_IN and a second half cycle control signal DEL_SEL2 output from the second decoding unit 270 in response to a first half-cycle control signal DEL_SEL1. The second delay unit 290 delays the first external signal CLK_IN.

The second shift register 250 outputs a digital code corresponding to half of the digital code DIG_CD by shifting the digital code DIG_CD output from the period detector 100.

The first decoding unit 260 receives a digital code of a predetermined bit among upper bits from the digital code output through the second shift register 250, and decodes the upper bit digital code to generate the first half-cycle control signal. Outputs (DEL_SEL1).

The second decoding unit 270 receives the lower bit digital code other than the bit input to the first decoding unit 260 among the digital codes output through the second shift register 250 and receives the lower bit. The second half period control signal DEL_SEL2 is output by decoding the digital code.

For example, assuming that the signal output from the period detecting unit 100 is 10110, the signal output through the second shift register 250 becomes 01011, and the first decoding unit 260 decodes 10. The input decoding unit 270 receives the second decoding unit 270 and decodes 11.

The first delay unit 280 and the second delay unit 290 may be configured as the half cycle delay unit 210 shown in FIG. 2, and the signal delay provided in the first delay unit 280. The delay time of the unit 211 is longer than the delay time of the signal delay unit 211 provided in the second delay unit 290.

The half-cycle delay signal generator 200 as shown in FIG. 2 requires 15 signal delay units 211 having a delay time of 1 ns to delay the first external signal CLK_IN by 15 ns. The half-cycle delay signal generator 200 includes three signal delay units 211 having the delay time of 1 ns for the second delay unit 290 to delay the first external signal CLK_IN by 15 ns. The first delay unit 280 may include three signal delay units 211 having a delay time of 4 ns. That is, the upper constant bit of the output of the second shift register 250 is delayed hierarchically by the first delay unit 280 in the second delay unit 290 to reduce layout area and current consumption. Can be.

FIG. 5 is a circuit diagram illustrating the clock signal recovery unit illustrated in FIG. 1.

The clock signal recovery unit 300 generates a rising edge 310 of the duty cycle correction signal CLK_OUT in response to the first external signal CLK_IN, and the second external signal. In response to the signal CLK_IN_DEL, a falling edge generator 330 for generating a falling edge of the duty cycle correction signal CLK_OUT and an output unit 350 for outputting the duty cycle correction signal CLK_OUT. It is composed.

The rising edge generator 310 includes a plurality of inverting means IV4, IV5, and IV6 for inverting and delaying the first external signal CLK_IN inverted by a third inverting means IV3, and the plurality of inverting means at a gate end thereof. Inverted by the third inverting means IV3 at the gate terminal and the first PMOS transistor P1 to which the signal output from the inverting means IV4, IV5, IV6 is input and the source terminal is connected to the external power supply VDD. The second PMOS transistor P2 receives the first external signal CLK_IN and a source terminal is connected to a drain terminal of the first PMOS transistor P1 and a drain terminal is connected to a common node.

The falling edge generator 330 receives the first NMOS transistor N1 and the second external signal CLK_IN_DEL that receive the second external signal CLK_IN_DEL from a gate terminal thereof, and have a drain terminal thereof connected to the common node. A plurality of inverting means (IV7, IV8, IV9) and a gate terminal for inverting delay are inputted to the signals output from the plurality of inverting means (IV7, IV8, IV9) at a gate stage, and a drain stage of the first NMOS transistor N1 is input. The second NMOS transistor N2 is connected to the source terminal and the source terminal is connected to the ground terminal VSS.

The output unit 350 includes two inverting means IV10 and IV11 for latching and outputting a signal of the common node, and twelfth to fourteenth inverting delays of the output signal of the inverting means IV10. Inverting means IV12, IV13, IV14.

6 is a timing diagram of a duty cycle correction device according to the present invention.

As shown in FIG. 6, when one cycle of the first external signal CLK_IN is T time, the half cycle delay signal generator 200 outputs the predetermined bit of the digital signal from the cycle detector 100. In response to the code DIG_CD, the first external signal CLK_IN is delayed by a half period T / 2 of the first external signal CLK_IN, and the clock signal recovery unit 300 decodes the first external signal. The duty cycle correction signal CLK_OUT having a duty ratio of 50% may be generated by receiving the signal CLK_IN and the second external signal CLK_IN_DEL.

Hereinafter, a duty cycle correction apparatus according to the present invention will be described with reference to the accompanying drawings.

When the period detector 100 outputs a time corresponding to one period of the first external signal CLK_IN as a digital code DIG_CD of a predetermined bit, the half-cycle delay signal generator 200 may generate the digital code ( The second external signal CLK_IN_DEL is output by delaying the first external signal CLK_IN by a half period in response to DIG_CD, and the clock signal recovery unit 300 outputs the first external signal CLK_IN and the second external signal. The signal CLK_IN_DEL is combined to generate the duty cycle correction signal CLK_OUT having a duty ratio of 50%.

In more detail, by shifting the digital code DIG_CD of the predetermined bit output from the period detecting unit 100 using the first shift register 231, the first external signal CLK_IN may be shifted. Generates a digital code corresponding to a half cycle. Thereafter, the shifted digital code is decoded to generate the half-cycle control signal DEL_SEL.

As illustrated in FIG. 3, the first NAND gate ND1 of the half cycle delay unit 210 combines the half cycle control signal DEL_SEL and the first external signal CLK_IN, and the first NAND gate. In response to the output signal of the gate ND1, the plurality of signal delay units 211 delay the external signal CLK_IN. For example, when the half-cycle control signal DEL_SEL <N> is activated, the first NAND gate ND1 that receives the half-cycle control signal DEL_SEL <N> outputs a low level and the remaining first The NAND gate ND1 outputs a high level. The signal input unit 211 that receives the high level input from the external power supply VDD and the low level outputs a low level signal that is delayed by a predetermined time. The signal input unit 211 connected to the next stage receives the high level output from the first NAND gate ND1 and the low level output from the previous signal input unit 211 and outputs a low level signal delayed by a predetermined time. . By repeating this operation, the first external signal CLK_IN is delayed by a time corresponding to a half period of the first external signal CLK_IN, and the second inverting means IV2 is outputted to the second external signal CLK_IN_DEL. ) To match the phase of the first external signal CLK_IN.

In addition, as illustrated in FIG. 4, the digital code DIG_CD is shifted by the second shift register 250 to correspond to half of the digital code DIG_CD. Output digital code,

The first decoding unit 260 and the second decoding unit 270 decode and output the digital code output through the second shift register 250 into the upper bit digital code and the lower bit digital code. The first half period control signal DEL_SEL1 and the second half period control signal DEL_SEL2 are output.

In response to the first half-cycle control signal DEL_SEL1, in response to the first delay unit 280 and the second half-cycle control signal DEL_SEL2 including the signal delay unit 211 having a long delay time, The current consumption and layout may be reduced by simultaneously delaying the first external signal CLK_IN with the second delay unit 290 having the small time delay unit 211.

The clock signal recovery unit 300 which receives the first external signal CLK_IN and the second external signal CLK_IN_DEL receives the first and second moments when the first external signal CLK_IN is inverted to a high level. The PMOS transistors P1 and P2 are turned on to output the duty cycle correction signal CLK_OUT having a high level from the output unit 350 by the external power supply VDD. 2 As soon as the external signal CLK_IN_DEL is inverted to a high level, the first and second NMOS transistors N1 and N2 are turned on and the output unit 350 is turned on by the ground power supply VSS. ), The duty cycle correction signal CLK_OUT at a low level is output.

As described above, the duty cycle correction apparatus according to the present invention can be configured by simplifying a simple control circuit for calculating the half cycle delay time by using a digital code corresponding to one cycle delay time of the external clock signal provided from the TDC. have.

In the duty cycle correction device according to the present invention, by using a digital code corresponding to one cycle delay time of an external clock signal provided from a TDC, the circuit can be simplified to increase operation reliability, reduce current consumption, and layout efficiency. It is accompanied by an effect that can increase.

Claims (15)

Period sensing means for converting and outputting one period of the first external signal into a digital code; A control signal generator for receiving the digital code and outputting a half cycle control signal; And In response to the half-cycle control signal, including a half-cycle delay unit for delaying the first external signal by a half period of the first external signal to output as a second external signal, The control signal generator, A shift register for shifting the digital code; And And a decoder configured to decode the shifted digital code and output a plurality of the half-cycle control signals. The method of claim 1, And a clock signal recovery means for receiving the first external signal and the second external signal and outputting a duty cycle correction signal. delete delete delete delete The method of claim 1, And the shift register shifts the digital code by one bit. The method of claim 1, The duty cycle correction device, characterized in that only one signal of the plurality of half-cycle control signal is activated. The method of claim 8, The half cycle delay unit, A switching unit configured to receive a plurality of the half-cycle control signals and the first external signal and determine an output path of the first external signal; And And a plurality of signal delay units for sequentially delaying the first external signal in response to the signal output from the switching unit. The method of claim 9, The switching unit, And a plurality of NAND gates configured to output a signal to the signal delay unit corresponding to the first external signal and each of the plurality of half-cycle control signals as inputs. The method of claim 10, The half cycle delay unit, A duty of one signal delay unit receiving an external power source and a corresponding output signal of the NAND gate, and a remaining signal delay unit receiving a signal delayed in a previous signal delay unit and a corresponding output signal of the NAND gate Cycle compensation device. Period sensing means for converting and outputting one period of the first external signal into a digital code; A first decoding unit decoding a higher bit of the digital code and outputting a first half period control signal; A second decoder configured to output a second half period control signal by decoding a lower bit minus the upper bit among the digital codes; A first delay unit delaying the first external signal in response to the first half-cycle control signal; And And a second delay unit configured to delay an output signal of the first delay unit in response to the second half-cycle control signal. The method of claim 12, And a shift register for shifting the digital code, wherein the first decoding unit receives the shifted digital code. The method of claim 13, And the shift register shifts the digital code by one bit. The method of claim 2, The clock signal recovery unit may include: a rising edge generator configured to generate a rising edge of the duty cycle correction signal in response to the first external signal; A falling edge generator configured to generate a falling edge of the duty cycle correction signal in response to the second external signal; And And an output unit for outputting the duty cycle correction signal.

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