KR20050101471A - Reoganizable forward error control system - Google Patents

Abstract

The present invention relates to a reconfigurable forward error correcting apparatus, comprising: a fine grain having a half mixer, a deinterleaver, and a portion of a convolutional mixer performing bit operation, and a coarse grain having a decoder and a part of a convolutional mixer performing byte operation. And a control unit for controlling the fine grains and the coarse grains, and a shared memory in which the fine grains and the coarse grains store data.

Description

Reconfigurable Forward Error Correction System {Reoganizable Forward Error Control System}

The present invention relates to a reconfigurable forward error correcting apparatus, and more specifically, to a forward error correcting apparatus including a reconfigurable apparatus capable of changing the specifications and standards as necessary, rather than supporting only predetermined specifications and standards. It is about.

Forward error correction apparatus is essential in digital communication system. When information such as video, audio, or data is transmitted, noise is always present in the transmission path, causing errors in the information. A forward error correction device is almost always implemented in a communication system in order to detect an error of information received from a receiver or to correct an error if an error occurs. There are many reasons why digital communication is superior to analog communication, but the development of forward error correction is also an important factor.

There are various types and methods of forward error correction apparatus. From the simplest parity checks to complex algorithms that require a lot of computational complexity, such as turbo code, but a high performance algorithm.

1 is a block diagram of a forward error correction apparatus of a digital communication system such as a conventional digital television transmission.

The error correction apparatus includes an external encoder 101, an interleaver 102, an internal encoder 103, and the like.

The embodiment schematically illustrates an error correction process in signal transmission.

Referring to FIG. 1, the external encoder 101 is generally implemented to be able to handle burst abrupt error well like the Reed-Solomon (RS) encoder.

The interleaver 102 mixes the transmission order of information in order to improve the ability of the forward error correction apparatus to cope with burst abrupt errors occurring in the transmission path. That is, since burst burst errors that may occur in the transmission path are spread out in time to convert them into irregular errors, the following decoder can better correct the related errors.

As the internal encoder 103, a convolutional encoder is usually used. The convolutional encoder is generally decoded by a Viterbi decoder, which can correct irregular errors well.

2 is a block diagram of a forward error correction apparatus in a digital television cable QAM receiver.

In the above embodiment, the forward error correcting apparatus of the QAM receiver includes a convolutional decoder 201, a semimixer 202, a deinterleaver 203, and an RS decoder 204.

2, the convolutional decoder 201 is typically implemented as a Viterbi decoder.

Semi-mixer 202 serves to restore the mixture of transmission information for the purpose of timing recovery and energy dissipation at the transmitter. The other components are the same as described above.

3 is a digital television terrestrial VSB receiver, compared to the cable receiver of FIG. 2, wherein the configuration blocks are the same, but the connection order of each block is different.

Recent digital television receiver chips support both cable and terrestrial reception. In other words, both the VSB standard and the QAM standard forward error correction apparatus should be implemented. Although the names of the blocks in FIG. 2 and FIG. 3 are the same, the cable standard and the terrestrial standard have different specifications and therefore must be implemented separately.

4 is an embodiment of a forward error correction apparatus implementing both standards.

The above embodiment is a block diagram provided simultaneously with a forward error correction device in a digital television cable QAM receiver and an error correction device in a digital television terrestrial VSB receiver.

In the digital television receiver chip, since terrestrial wave reception and cable reception do not occur at the same time, the conventional technology is implemented more efficiently by sharing a memory.

However, in the past, as the number of standards to be supported increases, additional implementations are required, and even if multiple standards are supported, only one standard is actually performed in some cases. It is a waste. In addition, if the specification of a standard to be supported after the chip has been added or modified must be redesigned and reprocessed.

An object of the present invention is to solve the above problems and to provide a forward error correction apparatus that can be reconfigurable.

Another object of the present invention is to provide a forward error correcting apparatus having hardware that can accommodate various standards and that can be modified or added by software even after chip fabrication.

In order to achieve the above object, a reconfigurable forward error correcting apparatus of the present invention includes a half grain, a deinterleaver and a convolutional mixer for performing bit operations, and a fine grain, a decoder, and a portion of the convolutional mixer for performing a byte operation. And coarse grain comprising: a control unit for controlling the fine grains and the coarse grains; and a shared memory in which the fine grains and the coarse grains store data.

In the present invention, the coarse grain is preferably an arithmetic logic unit (ALU) in units of bytes.

In the present invention, the control unit is preferably programmable.

In the present invention, the fine grain includes a place logic, a four-input lookup table, a deflip-flop, and first and second multiplexers; A rounding input signal and first and second input signals are inputted to the rounding logic to output a rounding value; In the four-input lookup table, values from which the first to third input signals, the fourth input signal and the rounding input signal pass through the first multiplexer are input, and the output value of the lookup table and the lookup are input to the second multiplexer. It is preferable that an output value in which the output value of the table passes through the flip-flop is input to generate the final output signal.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

5 is a block diagram of a reconfigurable forward error correction apparatus according to an embodiment of the present invention.

In the above embodiment, the forward error correction apparatus includes a controller 501, a fine grain 502, a coarse grain 503, and a shared memory 504.

The above embodiment schematically shows the correlation of each component.

The forward error correction apparatus generally consists of several blocks. In the case of digital television cable / terrestrial receivers, the device consists of a convolutional decoder, a half-mixer, a deinterleaver, and an RS decoder.

Each building block has different characteristics. The half-mixer is mainly composed of bit operations, and in the case of the convolutional decoder, it consists of many multiplexers and registers. In the case of the RS decoder, arithmetic operations are mainly performed in byte units, and in the case of deinterleaver, they are processed in byte units, but memory control is the main operation.

The present invention uses two types of reconstruction circuits, micrograins and coarse grains, to satisfy all the characteristics of these building blocks to be efficient reconstruction hardware.

The fine grain includes a portion of the convolutional encoder, a mixer and a deinterleaver, and the coarse grain includes a portion of the convolutional encoder and an RS decoder.

6 is a block diagram of an apparatus for reconstructing fine grains according to an embodiment of the present invention.

In this embodiment, the fine grain 502 includes a place logic 601, a four-input lookup table 602, a deflip-flop 603, and first and second multiplexers 604 and 605.

The above embodiment shows a four-input lookup table 602 as an example of fine grain 502.

Referring to FIG. 6, the first and second input signals and the rounding input signal of the four input signals are input to the rounding logic 601 to output the next rounding value. The rounding input value is input to the first multiplexer 604 like the fourth input signal, which is the last of the four input signals, and the two signals are summed. The first to third signals and the signal summed by the first multiplexer are input to the four-input lookup table 602. The 4-input lookup table 602 outputs a value corresponding to an input signal according to a predetermined table value. The output value of the 4-input lookup table 602 is input to the second multiplexer 605, the other branch is input to the de-flip-flop 603, and the output value is input to the second multiplexer 605. . The second multiplexer 605 multiplexes an input value to generate an output signal.

The four-input lookup table 602 is the basic building block of a commercial field programmable gate array (FPGA) and has all output values for four input combinations. Therefore, bit operations or operations can be easily implemented in the fine grain reconstruction structure.

One example of sparse grain 503 is an arithmetic logic unit in bytes. Since the coarse grain reconstruction hardware consists of byte-based arithmetic logic devices, the RS decoder, which has many byte-wise operations, is performed more efficiently than the fine grain structure.

In the forward error correcting apparatus of the present invention, a part of bit operations of the half-mixer, the deinterleaver, and the convolutional mixer are implemented in the fine grain reconstruction hardware, and the byte operations of the RS decoder and the convolutional mixer are implemented in the coarse grain reconstruction hardware. It can be implemented more efficiently than a single structure because it is configured using reconstruction hardware suitable for the operation characteristics of each block.

In order to allow fine grain and coarse grain reconstruction hardware to perform cable and terrestrial forward error correction, the corresponding standard algorithms are designed in software and the reconstruction structure is programmed in the controller. In the prior art, hardware for all of the standards to be supported must be separately designed, but in the present invention, since the software can be changed immediately by software, information about the entire standard required in a separate memory is stored and the configuration information is required when a specific standard is required. Simply take it out of the controller and program the reconfiguration hardware.

In addition, even after the digital television receiver chip is manufactured, even if a correction or a new specification is added to the forward error correction device, the software can be easily changed by only changing the corresponding software without remanufacturing the chip.

As described above, according to the present invention, by using a reconstruction device composed of fine grains and coarse grains in the forward error correction device, it is possible to accommodate various standards without additional hardware, and to modify the standards and specifications by software programming after chip fabrication. There is an advantage that can be added.

 1 is a block diagram of a forward error correction apparatus in a digital communication system such as a conventional digital television transmission.

2 is a block diagram of a forward error correction apparatus in a conventional digital television cable QAM receiver.

3 is a block diagram of a forward error correcting apparatus in a conventional digital television terrestrial VSB receiver.

4 is an embodiment of a forward error correction apparatus implementing both standards.

5 is a block diagram of a reconfigurable forward error correction apparatus according to an embodiment of the present invention.

6 is a block diagram of an apparatus for reconstructing fine grains according to an embodiment of the present invention.

{Description of Major Symbols in Drawings}

501 control unit 502 fine grain

503: coarse grain 504: shared memory

601: Placement Logic 602: 4-Input Lookup Table

603: flip-flop 604: first multiplexer

605: second multiplexer

Claims (4)

A fine grain having a half mixer, a deinterleaver and a part of a weaving mixer performing bit operation, a coarse grain having a decoder and a part of a weaving mixer performing byte operation, a controller for controlling the fine grain and the coarse grain, and the Reconfigurable forward error correction device comprising a shared memory for storing fine grain and coarse grain data. 2. The reconfigurable forward error correcting apparatus of claim 1, wherein the coarse grain is an arithmetic logic unit (ALU) in units of bytes. The apparatus of claim 1, wherein the controller is programmable. 2. The apparatus of claim 1, wherein the fine grain comprises a rounding logic, a four-input lookup table, a deflip-flop, and first and second multiplexers; A rounding input signal and first and second input signals are inputted to the rounding logic to output a rounding value; In the four-input lookup table, values from which the first to third input signals, the fourth input signal and the rounding input signal pass through the first multiplexer are input, and the output value of the lookup table and the lookup are input to the second multiplexer. A reconfigurable forward error correction device, characterized in that the output value of the table is passed through the flip-flop is input to generate a final output signal.