KR20050100866A - Dry etching device of semiconductor manufacture device - Google Patents

Abstract

The present invention relates to a dry etching apparatus for forming a small hole in the center portion of the upper electrode of the semiconductor etch chamber compared to the edge to supply gas uniformly to prevent etching defects at the edge of the wafer.

In the semiconductor dry etching apparatus of the present invention, an upper electrode and a lower electrode are provided to apply high frequency power to form a plasma in a process chamber, and a plurality of gas outlets formed in the upper electrode are regularly arranged. The plurality of gas outlets formed at the center of the upper electrode may have a smaller diameter than the plurality of discharge holes formed at the outer portion.

According to the present invention, since the gas injection holes of the upper electrode for injecting the process gas in the semiconductor dry etching apparatus have different sizes of the outer part and the center part so that the gas is uniformly injected, the uniformity of the oxide film thickness and the circuit line width is maintained. Improve the etching uniformity of the wafer.

Description

Dry Etching Equipment of Semiconductor Manufacturing Equipment {DRY ETCHING DEVICE OF SEMICONDUCTOR MANUFACTURE DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching apparatus of a semiconductor manufacturing equipment. In particular, a small hole is formed in a central portion of a gas supply hole of an upper electrode of a semiconductor etch chamber, and gas is uniformly supplied so that gas is uniformly etched. It relates to a dry etching device to prevent.

In general, a wafer for manufacturing a semiconductor device is repeatedly subjected to processes such as cleaning, diffusion, photoresist coating, exposure, development, etching, and ion implantation, and equipment for performing the corresponding process is used for each of these processes.

Among these processes, the etching process can be divided into wet etching and dry etching, and wet etching has been widely applied in the LSI era in which the minimum line width of the device is hundreds to several tens of microseconds, but due to the limitation of integration density, VLSI and ULSI devices show isotropic etching. Rarely used. Therefore, currently, in general, dry etching is used, and the process equipment for ultra-thin wafer processing using plasma among dry etching facilities is completely cut off from the outside when the process is performed using various elements such as gas and high frequency power in the process chamber. Ultra high vacuum is required.

The semiconductor manufacturing equipment which performs the dry etching process is again installed in the process chamber and the process chamber to supply the source gas necessary for generating plasma gas into the process chamber, and serves as a cathode unit, a cathode unit, and a role of an electrode. An anode unit, which faces and serves as another electrode at the same time the wafer is seated, is included. Among them, the cathode unit has a hollow disc, and source gas is supplied to one side of the cathode unit, and a plurality of source gas distribution holes are formed on the side of the cathode unit facing the anode unit more specifically than the other side of the cathode unit. At this time, the diameter and the number of the source gas distribution holes greatly influence the uniformity and thin film characteristics of the thin film deposited on the wafer.

Since the gas distribution hole of the conventional semiconductor manufacturing equipment is formed uniformly over the entire area of the cathode unit, the source gas is supplied between the cathode unit and the anode unit through the gas distribution hole, and is formed between the cathode unit and the anode unit. After the wafer is converted into plasma gas by an electric field, the wafer mounted on the anode unit is etched.

1 is a configuration diagram of an etching apparatus for performing a conventional ionic reaction etching process.

Referring to FIG. 1, an upper electrode 120 and a lower electrode 110 are provided to apply high frequency power to form a plasma in the process chamber 100. The lower electrode 110 is connected to a high frequency power supply 170 for supplying a high frequency power for plasma generation, the upper electrode 120 is grounded, the lower electrode 110 becomes a cathode and the upper electrode 120 is It will act as an anode. The upper electrode 120 serves as a ground when power is applied to form a plasma, and the lower electrode 110 is provided on a chuck capable of seating the wafer 10. The upper electrode 120 has a plurality of gas outlets 121 through which the reaction gas supplied from the gas supply line 150 passes. At this time, a flow control unit (MFC) 151 for controlling the flow rate of the reaction gas supplied is installed in the gas supply line 150. The reaction gas supplied to the space between the lower electrode 110 and the upper electrode 120 through the gas supply line 150 is decomposed into ions and radicals by high frequency (RF) power to form a plasma. In addition, a lower portion of the process chamber 100 is provided with a vacuum pump 190 for making the inside of the process chamber 100 into a predetermined vacuum state.

An etching apparatus for controlling the surface etch rate of the semiconductor wafer 10 by changing the gap between the upper electrode 120 and the lower electrode 110 has been developed and used. The etching apparatus adjusts the distance between the lower electrode 110 and the upper electrode 120 by elevating the upper electrode 120. To this end, an electrode support part 140 is provided on the process chamber 100 to support the upper electrode 120 to be liftable. The electrode support 140 is provided with a driving motor 141 to elevate the upper electrode 120 as necessary.

 In the conventional etching apparatus as described above, as the upper electrode 120 has a plurality of gas outlets 121 formed on the front surface of the wafer at a predetermined interval, the center portion and the outer portion of the wafer positioned on the upper electrode 120 are formed. The distance from the portion to the lower electrode 110 is changed. That is, different lengths from the outer edge of the wafer to the lower electrode 110 cause a difference in the amount of etching due to a distribution difference on the wafer of the reaction gases passing through the lower electrode 110 during the etching process. The thickness of the oxide film formed on the wafer and the uniformity of the circuit line width (CD) were reduced, resulting in a problem of defects in the wafer.

Accordingly, an object of the present invention is to provide a uniform etching amount on the entire surface of a wafer by uniformly distributing the gas supplied between the upper electrode and the lower electrode during the etching process in the semiconductor etching facility to solve the above problems. In providing.

Another object of the present invention is to provide a semiconductor dry etching apparatus for preventing wafer defects by maintaining the uniformity of the thickness and line width (CD) of the oxide film formed on the wafer during the etching process.

The semiconductor dry etching apparatus of the present invention for achieving the above object is provided with an upper electrode and a lower electrode to apply a high frequency power to form a plasma in the process chamber, a plurality of gas outlets formed in the upper electrode It is preferable that the plurality of gas outlets formed at the center of the upper electrode are arranged regularly and have a smaller diameter than the plurality of discharge ports formed at the outer portion.

In the upper electrode of the semiconductor dry etching apparatus of the present invention for achieving the above object, the upper electrode is divided into a central portion and the outer portion, a plurality of gas outlets are regularly arranged in the central portion and the outer portion of the upper electrode, It is preferable that the plurality of gas outlets formed at the center portion have a smaller diameter than the plurality of discharge ports formed at the outer portion.

The plurality of gas outlets formed on the outer portion of the upper electrode have holes formed to have a diameter of 0.33 mm.

The plurality of gas outlets formed at the center of the upper electrode have holes formed to have a diameter of 0.25 mm.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 is a block diagram of an etching apparatus for performing an ionic reaction etching process according to an embodiment of the present invention.

An upper electrode 220 and a lower electrode 210 are provided to apply high frequency power to form a plasma in the process chamber 200. The upper electrode 220 serves as a ground when power is applied to form a plasma, and the lower electrode 210 is provided on a chuck capable of seating the wafer 20. The upper electrode 220 has a plurality of gas outlets 221 through which the reaction gas supplied from the gas supply line 250 passes. The plurality of gas outlets 221 are formed to form a small central portion and a large outer portion. The center portion of the gas outlet 221 is, for example, a diameter? 0.33, and the outer portion is formed by? 0.25. At this time, a flow rate control unit (MFC) 251 for controlling the flow rate of the supplied reaction gas is installed in the gas supply line 250. The reaction gas supplied to the space between the lower electrode 210 and the upper electrode 220 through the gas supply line 250 is decomposed into ions and radicals by RF power to form a plasma. The lower portion of the process chamber 200 is provided with a vacuum pump 290 for making the inside of the process chamber 200 into a predetermined vacuum state.

4 is a structural diagram of the upper electrode 220 according to the embodiment of the present invention.

The upper electrode 220 is formed in a circular shape, and is divided into a central portion 232 and an outer portion 234, and includes a plurality of gas outlets 221. The plurality of gaseous outlets 221 formed in the central portion 232 form a hole having a diameter of 0.33, for example, and the plurality of gaseous outlets 221 formed in the outer portion 234 have a diameter of 0.25, for example. A hole is formed. The upper electrode 200 has a plurality of gaseous outlets 221 formed in a circular shape in 28 rows, the central portion 232 is in the range of 1 to 10, and the outer portion 234 is in the range of 11 to 28.

The upper electrode 220 configured as described above has a plurality of narrow gas outlets 221 formed in the central portion 232 when the gas is injected through the gas injection pipe positioned at the center of the gas supply line 250 during the etching process. The gas flows uniformly through the plurality of gas outlets 221 having a large spacing formed in the portion 234. In this way, the holes of the plurality of gas outlets 221 formed in the central portion 232 and the outer portion 234 are formed different from each other so that the same amount of gas is injected onto the wafer. Therefore, during the etching process, a uniform etching amount is provided on the entire surface of the wafer to maintain uniformity of the thickness of the oxide film and the line width (CD).

As described above, in the semiconductor dry etching apparatus, since the gas injection hole of the upper electrode for injecting the process gas is different from the size of the outer portion and the center portion so that the gas is uniformly injected, the thickness of the oxide film and the width of the circuit line are uniform. It is advantageous to maintain the etching property to improve the etching uniformity of the wafer.

1 is a block diagram of an etching apparatus for performing a conventional ionic reaction etching process

2 is a conventional upper electrode structure diagram

 3 is a block diagram of an etching apparatus for performing an ionic reaction etching process according to an embodiment of the present invention

4 is a structural diagram of an upper electrode 220 according to an embodiment of the present invention.

              Explanation of symbols on main parts of drawing

10, 20: wafer 110, 210: lower electrode

120, 220: upper electrodes 121, 221: a plurality of gas outlets

140, 240: electrode support 141, 241: drive motor

150, 250: gas supply line 151, 251: flow regulator

170, 270: high frequency power supply 190, 290: vacuum pump

Claims (8)

In a semiconductor dry etching device, An upper electrode and a lower electrode are provided to apply high frequency power to form a plasma in the process chamber, and a plurality of gas outlets formed on the upper electrode are regularly arranged, and a plurality of formed at the center of the upper electrode is provided. And a gas outlet having a diameter smaller than that of the plurality of discharge holes formed in the outer portion. The method of claim 1, And a plurality of gaseous outlets formed at the center of the upper electrode are holes having a diameter of 0.25 mm. The method of claim 2, And a plurality of gaseous exit openings formed on the outer portion of the upper electrode, the holes having a diameter of 0.33 mm. The method of claim 3, And a plurality of gaseous outlets formed at the center of the upper electrode are holes having a diameter of 0.25 mm. In the upper electrode of the semiconductor dry etching device, The upper electrode is divided into a central portion and an outer portion, and a plurality of gaseous outlets are regularly arranged in the central portion and the outer portion of the upper electrode, and the plurality of gaseous outlets formed in the central portion are larger than the plurality of discharge openings formed in the outer portion. The upper electrode of the semiconductor dry etching apparatus, characterized in that the diameter is formed small. The method of claim 5, And a plurality of gaseous outlets formed at the center of the upper electrode are holes having a diameter of 0.25 mm. The method of claim 6, And a plurality of gaseous exit openings formed on the outer portion of the upper electrode, the holes having a diameter of 0.33 mm. The method of claim 7, wherein And a plurality of gaseous outlets formed at the center of the upper electrode are holes having a diameter of 0.25 mm.