KR20050094291A - Multi layer printed circuit board in parallel with improved interconnection and method thereof - Google Patents

Abstract

The present invention relates to a multilayer printed circuit board and a method of manufacturing the same. More specifically, the present invention relates to a multilayer printed circuit board having a simple process and improved interlayer matching by using an anisotropic conductive film to provide interlayer connection in an interlayer connection process of a multilayer printed circuit board, and a method of manufacturing the same.

The present invention also provides a substrate, a plurality of via holes penetrating through the substrate to provide electrical connection in a circuit pattern of a pair of copper foils having respective circuit patterns coated on both sides of the substrate and the copper foils on the upper and lower surfaces. A plurality of circuit layers having; And a plurality of bonding layers positioned between the plurality of circuit layers to provide interlayer bonding of the plurality of circuit layers, and wherein conductive particles provide conductivity between adjacent copper foils of the circuit layers that are bonded to each other. A circuit board is provided.

Description

Multi layer printed circuit board in parallel with improved interconnection and method

The present invention relates to a multilayer printed circuit board of the parallel type and a method of manufacturing the same. More specifically, the present invention provides a multilayer printed circuit board having a simple process and improved interlayer matching by providing an interlayer connection using an anisotropic conductive film in an interlayer connection of a multilayer printed circuit board of a parallel type or a batch stacked type. It is about a method.

As electronic products become smaller and thinner, thinner, denser, more compact, and smaller in size, more and more, multilayer printed circuit boards are also undergoing fine patterns, miniaturization, and packaging.

Accordingly, in order to increase the micropattern formation, reliability, and design density of multilayer printed circuit boards, there is a tendency to change the structure of the multilayer structure of the circuit together with the change of raw materials, and the parts are also SMT (Dual In-Line Package) type. As the surface mount technology type is changed, the mounting density is also increasing.

In addition to the portableization of electronic devices, high functionalization, the Internet, moving pictures, and high-capacity data transmission and reception make the design of printed circuit boards complicated and require high-level technology.

The printed circuit board includes a single-sided PCB in which wiring is formed only on one side of the insulated substrate, a double-sided PCB in which wiring is formed on both sides, and an MLB (Multi Layered Board) that is wired in multiple layers. In the past, single-sided PCBs were used because of simple components and simple circuit patterns. However, in recent years, due to increased complexity of circuits and increased demand for high-density and miniaturized circuits, it is common to use double-sided PCBs or multilayer printed circuit boards. The present invention relates to a method of manufacturing a multilayer printed circuit board among them.

The MLB is an additional wiring layer formed to enlarge the wiring area. Specifically, MLB is divided into an inner layer and an outer layer, and a four-layer MLB (two inner layers and two outer layers) having a thin core (T / C) as a material of the inner layer and pre-gluing the outer layer and the inner layer with a preplex. Floor). That is, the multilayer printed circuit board has at least four layers. As the complexity of the circuit increases, it may consist of six, eight, ten or more layers.

A power circuit, a ground circuit, a signal circuit, and the like are formed in the inner layer, and a preplex is sandwiched between the inner layer and the outer layer or between the outer layers to insulate and bond. At this time, the wiring of each layer is connected using a via hole (conducting hole).

MLB has a great advantage that it can significantly increase the wiring density, but there is a disadvantage that the manufacturing process is complicated by that. In particular, in the case of the manufacturing method according to the so-called build-up method in which an inner layer forms an inner layer circuit and accumulates additional layers thereon, deformation is impossible when the process is completed. It becomes this defect. Many inspection devices are required to prevent such errors in advance.

1A to 1D illustrate a circuit layer including a circuit pattern among layers constituting a multilayer printed circuit board in a conventional so-called parallel multilayer printed circuit board manufacturing method or a batch lamination method of a multilayer printed circuit board manufacturing method. The method is shown. After processing the via hole in the circuit layer, the via hole is filled by plating to electrically connect the circuit layer with the via hole of the insulating layer or another circuit layer.

1A shows a copper clad laminate 101 used as a base substrate in the manufacture of a printed circuit board. The copper foil laminated plate 101 is comprised with the base material 103 and the copper foil 102 coated on both sides.

In Fig. 1B, the via holes 104 are machined into the copper clad laminate 101. Via holes are processed to a diameter of 50-100 μm using a YAG or CO ₂ laser or mechanical drilling. In the conventional multilayer printed circuit board, the via hole has a diameter of 200-300 μm, but if the diameter of the via hole is reduced, the inside of the via hole 104 may be filled in the plating without additional paste plugging process.

In Fig. 1C, the upper surface, the lower surface of the copper foil laminated plate 101 and the inner wall of the via hole 104 are plated by electroless plating and electrolytic plating on the copper foil laminated plate 101 on which the via hole 104 is processed. As shown in FIG. 1C, plating layers 105 are formed on upper and lower surfaces of the substrate, and the via holes 104 are filled by plating.

As such, a method of filling the inside of the via hole 104 by plating without conducting a separate filling process is also possible. However, the via hole 104 may be plated by a separate conductive paste filling process by plating the inner wall of the via hole 104. The method of filling the interior of the chamber is also used.

In Fig. 1D, a circuit pattern is formed using a circuit pattern forming method such as etching. The circuit layer 106 thus formed may be used as the circuit layers 106a, 106b, and 106c of FIG. 3 in a so-called parallel or batch stacked multilayer printed circuit board manufacturing method.

The processed circuit layer is used as one of the circuit layers 106a, 106b, and 106c of FIG. 3, and via holes and circuit patterns are designed in consideration of the coupling with the insulating layers.

In addition, the number of necessary circuit layers and insulating layers is determined by the number of layers of the multilayer printed circuit board to be manufactured. For example, two circuit layers are required in a four-layer printed circuit board, and three circuit layers are required in a six-layer printed circuit board and four circuit layers in an eight-layer printed circuit board.

2A to 2D show a method of forming an insulating layer inserted between circuit layers in a conventional parallel multilayer printed circuit board manufacturing method.

FIG. 2A shows a flat insulating material 201 having a polyester release film 202 attached to both sides of the preplex 203.

The thickness of the preplex 203 may be selectively used according to the specification of the product. The thickness of the release film 202 may be 20-30 μm, and may be one already attached at the time of prepreg fabrication. The release film 202 may be bonded to 203 and used.

In FIG. 2B, the via hole 204 is processed by drilling into the flat insulating material 201. In this case, the via hole 204 is typically processed by mechanical drilling. The diameter of the via hole 204 is slightly larger than the diameter of the via hole formed in the circuit layer in consideration of the connection with the circuit layer.

Via holes of the insulating layer connected to the circuit layer 106 manufactured by the method of filling the via holes 104 described with reference to FIGS. 1A to 1D by plating among the above-described circuit layer processing methods are processed to a diameter of about 100 μm. do.

In FIG. 2C, the via hole 204 is filled with the conductive paste 205, and in FIG. 2D, the release film 202 is removed.

Similarly, the insulating layer 206 thus formed is used as one of the insulating layers 206a and 206b of FIG.

The location and size of the via holes must be designed in consideration of the via holes of the circuit layer to which the insulating layer is to be bonded. The number of insulating layers is also determined by the number of layers of the multilayer printed circuit board to be manufactured. For example, one in a four-layer printed circuit board, two in a six-layer printed circuit board, and three insulating layers in an eight-layer printed circuit board are required. This is different from a so-called build-up manufacturing method in which a four-layer printed circuit board has two insulating layers and a six-layer printed circuit board has four insulating layers.

As shown in Fig. 3, the circuit layers 106a, 106b and 106c formed by the method shown in Figs. 1A to 1D and the insulating layers 206a and 206b formed by the method shown in Figs. 2A to 2D are shown. Alternately.

A targeting or pin matching method or the like is used to align the disposed layers so that the via holes match exactly.

Targeting is the process of processing the target hole in the 'target guide mark' of the inner layer, which is the reference point for drilling, after lamination of the substrate, and generally uses a target drill by X-ray.

The pin matching method means that the hole, which is the standard for interlayer matching, that is, the guide hole is processed at the same predetermined position on a plurality of substrates during the via hole processing, and the hole is processed at the pin during lay-up. The circuit layer and the insulating layer are inserted to match the position of the circuit layer and the insulating layer.

Then, as shown in Fig. 3, the arranged circuit layer and the insulating layer are pressed together in a compression press in the direction of the arrow as shown in Fig. 4 to complete a six-layer multilayer printed circuit board as shown in Fig. 4.

Then, post-treatment, such as trimming treatment to prevent scratches and safety accidents of the product by trimming the resin and the copper foil flowing out of the edge of the laminated substrate, is performed.

In the case of a multi-layer printed circuit board manufactured by a so-called build-up method, an insulating layer is laminated on one double-sided printed circuit board and a single-sided printed circuit board is stacked on top of each other. In the case of a multilayer printed circuit board manufactured according to the method, a plurality of double-sided printed circuit boards are continuously stacked with an insulating layer interposed therebetween.

Looking at the cross section by this difference, it is possible to determine in which manufacturing method the finished printed circuit board is manufactured.

However, according to the prior art as described above, there is a problem in that a method or a process capable of coping with a ball pad spacing up to 0.4 pitch is complicated and it is difficult to secure reliability of the electrical connection between layers.

Accordingly, an object of the present invention is to provide a multilayer parallel printed circuit board and a method of manufacturing the same by simplifying the process by using an anisotropic conductive film and improving the interlayer electrical connection by using an anisotropic conductive film.

The multilayer printed circuit board according to the present invention penetrates the substrate to provide electrical connection in a circuit pattern of a copper foil having a substrate, each circuit pattern coated on both sides of the substrate, and copper foils on the upper and lower surfaces. A plurality of circuit layers having a plurality of via holes; And a plurality of bonding layers positioned between the plurality of circuit layers to provide interlayer bonding of the plurality of circuit layers, and wherein conductive particles provide conductivity between adjacent copper foils of the circuit layers that are bonded to each other. It is done.

In addition, the method of manufacturing a multilayer printed circuit board according to the present invention includes a first step of preparing a plurality of circuit layers by processing a plurality of via holes and forming a circuit pattern in each copper-clad laminate; A second step of laminating a bonding layer providing conductivity between conductors adjacent to the conductive particles during heating and pressing between the plurality of circuit layers; And a third step of forming a multilayer printed circuit board providing conductivity between adjacent conductors of the adjacent circuit layers by pressurizing and heating the plurality of circuit layers and the bonding layer stacked in the second step.

Hereinafter, a parallel multilayer printed circuit board and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

5A to 5D illustrate a method for manufacturing a parallel multilayer printed circuit board according to an embodiment of the present invention or a method for manufacturing a multilayer printed circuit board using a batch lamination method, including a circuit pattern among layers constituting the multilayer printed circuit board. The method of manufacturing a circuit layer is shown. After processing the via hole in the circuit layer, the via hole is filled by plating to electrically connect the circuit layer with the via hole of the insulating layer or another circuit layer.

5A shows a copper clad laminate 501 used as a base substrate in the manufacture of a printed circuit board. The copper foil laminated plate 501 is comprised with the base material 503 and the copper foil 502 coated on both sides.

Resin is used as the base material 503 of the copper-clad laminate 501. Resins are excellent in electrical properties, but have the disadvantages of insufficient mechanical strength and 10 times greater dimensional change with temperature than metals. To compensate for these drawbacks, paper, fiberglass and glass nonwoven fabrics are used as reinforcing substrates. By using the reinforcing base material, the strength in the longitudinal and transverse directions of the resin increases, and the dimensional change due to the temperature also decreases.

As the copper foil 502, an electrolytic copper foil is usually used. In order to increase the adhesive force with the resin, the copper foil 502 chemically reacts with the resin at the time of forming the copper foil 502 and is made to penetrate about 5 μm toward the resin. On the other hand, the copper foil 502 is manufactured by a method of thinly plating copper on a rotating drum by electrolysis. The thickness of the copper foil 502 is usually about 18 to 70 um, but recently, the thickness of the copper foil 502 is also very thin, such as 5 um, 7 um, and 15 um, as the thickness of the wiring pattern becomes finer.

In FIG. 5B, the via hole 504 is machined into the copper clad laminate 501. In FIG. Via holes are processed to a diameter of 50-100 μm using a YAG or CO ₂ laser or mechanical drilling. In the conventional multilayer printed circuit board, the diameter of the via hole is 200-300 μm, but if the diameter of the via hole is reduced, the inside of the via hole 504 may be filled in the plating without additional plugging process.

After drilling, deburring and desmear are performed to remove various contaminants and foreign matters generated during processing.

Here, deburring is an operation for removing dust particles on the burr and hole inner wall of the copper foil and dust, fingerprints, etc. on the surface of the copper foil generated during drilling. Another purpose of deburring is to increase the cohesion of copper in the subsequent plating process by imparting roughness to the surface of the copper foil.

In deburring, 'Buff polishing' is first performed using a brush (specially called a Buff brush) to obtain a frontal treatment effect. Next, two steps of washing with high pressure washing are performed to remove the particles falling off during the polishing process.

On the other hand, only a few revolutions per minute of the drill bit is rotated at high speed during drilling, which generates a lot of heat. Due to this heat, the resin constituting the PCB board melts and adheres to the inner wall of the hole, which is called a smear.

The smear must be removed as it plays a decisive role in degrading the quality of copper plating on the inner wall of the hole. This operation is called desmear in the sense of removing the smear.

In FIG. 5C, the upper surface, the lower surface of the copper foil laminated plate 501 and the inner wall of the via hole 504 are plated by electroless plating and electrolytic plating on the processed copper foil laminated plate 501. As shown in FIG. 5C, plating layers 505 are formed on upper and lower surfaces of the substrate, and the via holes 504 are filled by plating.

As such, a method of filling the inside of the via hole 504 by plating without conducting a separate filling process is also possible. However, the via hole 504 may be plated by a separate conductive paste filling process by plating the inner wall of the via hole 504. It is also used to fill the inside of the chamber.

Electroless copper plating is the only plating method for imparting conductivity to the surface of non-conductors such as resins, ceramics, glass, and the like. Electroless copper plating is plating on insulators, so reactions with electrically charged ions cannot be expected. Electroless copper plating is carried out by precipitation reactions, which are promoted by catalysts. To deposit copper from the plating solution, a catalyst must be attached to the surface of the material to be plated. This indicates that electroless copper plating requires a lot of pretreatment.

Electroless copper plating is generally difficult to thicken the plating film, and even the physical properties are less than the electrolytic copper plating, but in recent years, its properties have been greatly improved and its use has been expanded.

Electroless copper plating is performed by immersing the substrate in a plating solution so that not only the inner wall of the hole but also all parts of the substrate are plated. By performing electroless copper plating, the copper foil on the upper surface of the substrate and the copper foil on the lower surface are connected by a conductor. This is called primary copper plating. Primary copper plating is a primary plating for electrolytic copper plating, and the thickness of the plating film is also thin. The electroless copper plating film cannot be used as it is because of poor physical properties, and should be supplemented with electrolytic copper plating.

Electroless copper plating was performed to impart conductivity to the inner wall of the hole, and electrolytic copper plating using electrolysis is now possible. Electrolytic copper plating is easy to form a thick plating film, and the properties of the film are also superior to electroless copper plating.

In Fig. 5D, a circuit pattern is formed using a circuit pattern forming method such as etching. The circuit layer 506 thus formed may be used as the circuit layers 701a, 701b, and 701c of FIG. 7 in a so-called parallel or batch stacked multilayer printed circuit board manufacturing method.

The processed circuit layer is used as one of the circuit layers 701a, 701b, and 701c of FIG. 7, and the via layer and the circuit pattern are designed in consideration of the coupling with the insulating layers.

In addition, the number of necessary circuit layers and insulating layers is determined by the number of layers of the multilayer printed circuit board to be manufactured. For example, two circuit layers are required in a four-layer printed circuit board, and three circuit layers are required in a six-layer printed circuit board and four circuit layers in an eight-layer printed circuit board.

6 is a view showing an anisotropic conductive film of the insulating layer according to the present invention.

As shown in FIG. 6, an anisotropic conductive film (ACF) 601 used in the present invention is a film-like adhesive in which a metal coated plastic or metal particles or the like is dispersed in conductive particles 602. It is widely used for LCD panel and TCP (Tape Carrier Package) or PCB (Printed Circuit Board) and TCP electrical connection.

In the early stage of development of the ACF 601, a thermoplastic resin such as a Stylene block copolymer was used as the adhesive 603. Since thermoplastic resins are soluble in general purpose solvents, they have excellent reworkability. However, thermoplastic resins have high heat resistance and high melting temperature, and thus have high connection resistance. For this reason, in recent years, thermosetting resins, such as epoxy resins, have been used in view of improving connection reliability, and in particular, thermosetting resins in which crosslinkable polymer materials are dispersed in order to provide stress relaxation and reworkability during connection, etc. I use it).

7 is a cross-sectional view of a circuit layer and an insulating layer alternately arranged in the method of manufacturing a parallel multilayer printed circuit board of the present invention.

As shown in Fig. 7, the circuit layers 701a, 701b and 701c formed by the method shown in Figs. 5A to 5D and the anisotropic conductive films 702a and 702b shown in Fig. 6 are alternately arranged.

A targeting or pin matching method or the like is used to align the disposed layers so that the via holes match exactly.

Targeting is a process of processing a target hole in the 'target guide mark' of the inner layer, which is a reference point for drilling, after lamination of the substrate, and generally uses a target drill by X-ray.

The pin matching method means that the hole, which is the standard for interlayer matching, that is, the guide hole is processed at the same predetermined position on a plurality of substrates during the via hole processing, and the hole is processed at the pin during lay-up. The circuit layer and the anisotropic conductive film are inserted to match the circuit layer and the anisotropic conductive film position.

Then, as shown in Fig. 7, the arranged circuit layer and the anisotropic conductive film are compressed and laminated together by a compression press in the direction of the arrow as shown, thereby completing a six-layer multilayer printed circuit board as shown in Fig. 8. .

Then, post-treatment, such as trimming treatment to prevent scratches and safety accidents of the product by trimming the resin and the copper foil flowing out of the edge of the laminated substrate, is performed.

At this time, the anisotropic conductive films 702a and 702b located between the circuit layers 701a, 701b and 701c melt and disperse as they are heated (160 to 180 ° C., connection time: 10 to 20 sec.) And pressurized (2 to 3 MPa). The conductive particles are arranged in a row between the electrodes in which the conductive particles are opposed to each other, so that conductivity can be obtained. On the other hand, an adhesive is filled between adjacent electrodes so that the conductive particles exist independently of each other, thereby obtaining high insulation. Mechanical fusion between the conductive particles and the electrode is maintained by the high adhesion of the adhesive. Therefore, the influence which the performance of an adhesive gives on the connection reliability of ACF is large.

In the multilayer printed circuit board manufactured as described above, the ball pad pitch is 200 to 275 um, the plating thickness is 10 to 20 um, the copper foil is 6 to 9 um, and the pad width is 150. ~ 200um is available, circuit interval is 50 ~ 75um and hole size is 50 ~ 100um.

According to the method of manufacturing a multilayer printed circuit board of the present invention as described above, since an anisotropic conductive film is used without using a Cu filling method, the process is simplified and cost is not reduced because a very expensive Cu paste is not used.

In addition, according to the present invention, since the lamination is excellent, the interlayer matching is excellent, and because the anisotropic conductive film is used, the electrical connection can be made even if a mismatch occurs within the pad size limit, so the matching window is also excellent, and the ball pad pitch Since the gap can be realized from 0.2mm to 0.257mm, it is effective to secure breakthrough design rules when applying high density substrate in the future.

Detailed description of the invention is just one embodiment of a multilayer printed circuit board and a method of manufacturing the same according to the present invention, and the present invention is not limited to the above-described embodiment, and has a general knowledge in the field Anyone can grow up to various modifications within the scope of the present invention as defined by the following claims.

1A to 1D illustrate a circuit layer forming method among layers constituting a multilayer printed circuit board in a conventional parallel multilayer printed circuit board manufacturing method.

2A to 2D show a method of forming an insulating layer inserted between circuit layers in a conventional parallel multilayer printed circuit board.

3 is a cross-sectional view of a state in which circuit layers and insulating layers are alternately arranged in a conventional parallel multilayer printed circuit board manufacturing method.

4 is a cross-sectional view of a six-layer printed circuit board completed according to a conventional parallel multilayer printed circuit board manufacturing method.

5A to 5D illustrate a method of forming a circuit layer among layers constituting a multilayer printed circuit board in the method for manufacturing a parallel multilayer printed circuit board according to the present invention.

6 is a view showing an anisotropic conductive film as an insulating layer inserted between circuit layers in a multilayer printed circuit board according to the present invention.

7 is a cross-sectional view of a circuit layer and an insulating layer alternately arranged in the method for manufacturing a parallel multilayer printed circuit board according to the present invention.

8 is a cross-sectional view of a six-layer printed circuit board completed according to the method for manufacturing a parallel multilayer printed circuit board according to the present invention.

※ Description of the main parts of the drawings

501: copper foil laminated plate 502: copper foil

503: description 504: via hole

505: plating layer 506: circuit layer

601: anisotropic conductive film 602: conductive particles

603: Adhesive

701a, 701b, 701c: circuit layer

702a and 702b: insulation layer

Claims (7)

A base having a plurality of via holes penetrating through the base to provide electrical connection in the circuit pattern of the base, a pair of copper foils having respective circuit patterns coated on both sides of the base, and the upper and lower copper foils. Circuit layer; And A multilayer printed circuit positioned between the plurality of circuit layers and providing an interlayer junction of the plurality of circuit layers, and comprising a plurality of bonding layers, wherein conductive particles provide conductivity between adjacent copper foils of the circuit layers that are bonded to each other. Board. The method of claim 1, And the conductive particles of the bonding layer provide conductivity of the interlayer via holes of the plurality of circuit layers to form stack vias. The method according to claim 1 or 2, The bonding layer is a multilayer printed circuit board, characterized in that the anisotropic conductive film. The method of claim 3, wherein The anisotropic conductive film is a multilayer printed circuit board, characterized in that made of a thermosetting resin. A first step of preparing a plurality of circuit layers by processing a plurality of via holes and forming a circuit pattern in each copper-clad laminate; A second step of laminating a bonding layer providing conductivity between conductors adjacent to the conductive particles during heating and pressing between the plurality of circuit layers; And a third step of forming a multilayer printed circuit board providing conductivity between adjacent conductors of the adjacent circuit layers by pressurizing and heating the plurality of circuit layers and the bonding layer stacked in the second step. Manufacturing method. The method of claim 5, The method of manufacturing a multilayer printed circuit board, wherein the bonding layer of the second step is an anisotropic conductive film. The method according to claim 5 or 6, And wherein the conductor adjacent to the third step is provided with conductivity between via holes to form a stack via.