KR20050094121A - Relaxation oscillator - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a relaxation oscillator capable of linearly changing the frequency of a capacitor value to realize precise frequency resolution. The present invention relates to charging and discharging a capacitor between predetermined threshold voltages internally in a circuit. In the relaxation oscillator for generating an oscillation signal, the capacitor is divided into a load capacitor form so that the same value is formed in the differential node, respectively, characterized in that the connection.

Description

Relaxation oscillator

The present invention relates to a low power relaxation oscillator that provides a synchronization clock for maintaining synchronization between systems in a power down mode in a wireless mobile communication system. More particularly, the present invention relates to a change in a capacitor value. The present invention relates to a relaxation oscillator capable of changing the frequency linearly to realize precise frequency resolution.

In general, an oscillator is a representative example of a signal generating circuit in the electronic circuit field consisting of a signal processing circuit and a signal generating circuit. In other words, the oscillator generates a signal that is stable and periodically changes in time, and is used as a system clock signal for timing control of the system, or as a carrier signal (modulation signal) that converts amplitude or frequency of the signal. do.

Such an oscillator may be divided into a tuned oscillator and a relaxation oscillator called a charge / discharge oscillator according to an implementation method. That is, the charge / discharge oscillator generates an oscillation signal by charging and discharging a capacitor between a predetermined threshold voltage in a circuit. The charge / discharge oscillator, that is, the relaxation oscillator, is a kind of RC oscillator using a resistor as a path for charging and discharging a capacitor, a constant current charge and discharge oscillator using a current source to charge and discharge a capacitor, and a path for charging and discharging a capacitor. It can be classified into a multi-harmonic oscillator using a capacitor connected to an emitter (or a source).

In general, a relaxation oscillator is used as a low power oscillator that provides a synchronization clock for maintaining synchronization between systems in a power down mode in a wireless mobile communication system.

1 is a circuit diagram showing a relaxation oscillator according to the prior art.

The relaxation oscillator includes resistors R1, R2, cross coupled NMOS transistors NT1, NT2, capacitor C, and constant current sources I1, I2.

The resistors R1 and R2 are connected between the power supply voltage and the NMOS transistors NT1 and NT2, respectively, and the capacitor C is connected between the sources of the NMOS transistors NT1 and NT2, and the constant current sources I1 and I2 are the sources and ground voltages of the NMOS transistors NT1 and NT2. It is connected between each.

The relaxation oscillator shown in FIG. 1 satisfies the condition that charge and discharge through capacitor C continues to occur so that oscillation of the circuit can occur at a particular frequency.

NMOS transistors NT1 and NT2 are differentially operated with their gates cross-coupled. When NMOS transistor NT1 is turned on and current flows from node V1 to node V2 when NMOS transistor NT2 is turned off, capacitor C is moved in the same direction. Start charging. Therefore, the potential of the node V1 remains constant, and the potential of the node V2 starts to fall.

When the potential of the node V2 is sufficiently lowered, the NMOS transistor NT2 is turned on, and the NMOS transistor NT1 is turned off, and the charging direction of the capacitor C suddenly changes, discharging the previously charged charge and charging in the opposite direction from the node V2 to the node V1 direction. To start.

FIG. 2A is a simulation waveform diagram showing potentials of nodes V1 and V2 of the relaxation oscillator shown in FIG. 1, and FIG. 2B is a simulation waveform diagram showing an oscillation waveform.

As shown in FIG. 2A, the relaxation oscillator shown in FIG. 1 is oscillated through the charging / discharging process, and the oscillation frequency is determined by the current I and the capacitor C. FIG. That is, the relationship between the current I and the capacitor C is defined as shown in [Equation 1].

[Equation 1]

Therefore, the oscillation frequency Fosc is defined as shown in [Equation 2].

[Equation 2]

If your application requires a specific frequency, tune the value of current I or capacitor C to set the desired frequency.

One way to adjust the value of capacitor C is to connect a switched capacitor array 2 as shown in FIG. 3 across the capacitor C of the relaxation oscillator shown in FIG.

The variable capacitor 2 shown in FIG. 3 comprises a plurality of switch capacitors 4 connected in parallel between node V1 (or node V2) and the ground voltage. Here, the switch capacitor 4 includes a capacitor Cv and a switch SW connected in series.

However, in the relaxation oscillator according to the prior art, the oscillation frequency varies nonlinearly according to the number of connecting the additional capacitor Cv of the variable capacitor 2, as shown in FIG. 4A. 4B is a graph showing an amount of change in oscillation frequency according to the number of capacitors Cv additionally connected.

That is, a momentary change in voltage occurs in the peak portion of the waveform shown in FIGS. 2A and 2B, and the peak value changes sensitively to the minute bias change caused by the on / off of the switch, thereby changing the overall oscillation frequency. .

Therefore, the resolution that can control the frequency is also limited, there is a problem that an error with the desired frequency value occurs.

An object of the present invention for solving the above problems is to implement a precise frequency resolution by linearly changing the frequency of the change in the capacitor value.

A relaxation oscillator of the present invention for achieving the above object is a relaxation oscillator for generating an oscillation signal by charging and discharging a capacitor between a predetermined threshold voltage internally in a circuit, wherein each capacitor has the same value at the differential node It is characterized in that it is divided into a load capacitor form so as to be connected.

In addition, the relaxation oscillator of the present invention is a relaxation oscillator for generating an oscillation signal by charging and discharging between a threshold voltage (internally determined threshold voltage) internally, the first and second gates are cross-coupled to form a differential node transistor; And first and second capacitors connected to each of the differential nodes and having the same value.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a circuit diagram illustrating a relaxation oscillator according to the present invention.

The relaxation oscillator includes resistors R1, R2, cross coupled NMOS transistors NT1, NT2, capacitors C1, C2, and constant current sources I1, I2.

The resistors R1 and R2 are connected between the power supply voltage and the NMOS transistors NT1 and NT2, respectively, and the capacitors C1 and C2 are respectively connected between the source and ground voltages of the NMOS transistors NT1 and NT2, and the constant current sources I1 and I2 are connected to the NMOS transistors NT1, It is connected between the source and ground voltage of NT2 respectively. Here, the capacitors C1 and C2 are divided and connected in the form of a load capacitor so that the same values are formed at the differential nodes V1 and V2, respectively.

The NMOS transistors NT1 and NT2 operate differentially with their gates cross-coupled. At this time, when the NMOS transistor NT1 is turned on and the NMOS transistor NT2 is turned off, the potential of the node V1 rises, the capacitor C1 starts charging, and the potential of the node V2 falls, and the capacitor C2 discharges.

When the potential of the node V2 is sufficiently lowered, the NMOS transistor NT2 is turned on, the NMOS transistor NT1 is turned off, the potential of the node V1 is lowered, the capacitor C1 is discharged, the potential of the node V2 is raised, and the capacitor C2 starts charging. .

FIG. 6A is a simulation waveform diagram showing potentials of nodes V1 and V2 of the relaxation oscillator shown in FIG. 5, and FIG. 6B is a simulation waveform diagram showing an oscillation waveform.

As illustrated in FIG. 6A, the electric potentials of the nodes V1 and V2 have a simple charge / discharge phenomenon continuously without an instantaneous voltage change.

If the actual application requires a specific frequency, tune the value of current I or capacitors C1 and C2 to set the desired frequency.

One way to adjust the values of capacitors C1 and C2 is to connect a switched capacitor array 2 as shown in FIG. 7 between the capacitors C1 and C2 of the oscillator and this shown in FIG.

The variable capacitor 2 shown in FIG. 7 includes a plurality of switch capacitors 4 connected in parallel between node V1 (or node V2) and the ground voltage. Here, the switch capacitor 4 includes a capacitor Cv and a switch SW connected in series.

In the relaxation oscillator according to the present invention, the oscillation frequency varies linearly as shown in FIG. 8A according to the number of connecting the additional capacitor Cv of the variable capacitor 2. 8B is a graph showing an amount of change in oscillation frequency according to the number of capacitors Cv additionally connected.

The relaxation oscillator according to the present invention separates the capacitor into both nodes so that when one capacitor performs the charging operation, the other capacitor performs the discharge operation, so that the current paths across the capacitor are switched instantaneously to maintain the voltage difference between the both ends. It is possible to prevent the peak phenomenon that occurs when the voltage of each node suddenly changes.

Accordingly, as shown in FIGS. 8A and 8B, the amount of change in the oscillation frequency is constant according to the number of connecting the additional capacitors Cv.

As described above, the relaxation oscillator according to the present invention can implement a precise frequency resolution because the oscillation frequency is linearly changed according to the change of the capacitor value, it is possible to implement the SoC (System on Chip).

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a circuit diagram showing a relaxation oscillator according to the prior art.

FIG. 2A is a simulation waveform diagram showing the potentials of nodes V1 and V2 of the relaxation oscillator shown in FIG. 1. FIG.

2B is a simulation waveform diagram showing an oscillation waveform.

3 is a circuit diagram illustrating a switched capacitor array according to the prior art.

4A is a graph showing the oscillation frequency versus the number of additional capacitors of the variable capacitor shown in FIG.

Figure 4b is a graph showing the amount of oscillation frequency change with respect to the number of additional capacitors of the variable capacitor shown in Figure 3 further connected.

5 is a circuit diagram showing a relaxation oscillator according to the present invention.

FIG. 6A is a simulation waveform diagram showing potentials of nodes V1 and V2 of the relaxation oscillator shown in FIG. 5. FIG.

6B is a simulation waveform diagram showing an oscillation waveform of the relaxation oscillator shown in FIG. 5.

7 is a circuit diagram illustrating a switched capacitor array according to the present invention.

8A is a graph showing the oscillation frequency versus the number of additional capacitors of the variable capacitor shown in FIG.

FIG. 8B is a graph showing variation in oscillation frequency with respect to the number of additional capacitors of the variable capacitor shown in FIG.

Claims (9)

In a relaxation oscillator for generating an oscillation signal by charging and discharging a capacitor between a predetermined threshold voltage internally in a circuit, The capacitor is a relaxation oscillator, characterized in that divided in the form of a load (load) capacitor so that the same value is formed at each differential node. The method of claim 1, The capacitor is a relaxation oscillator, characterized in that the variable capacitor capable of changing the capacity. The method of claim 2, And said variable capacitor comprises a plurality of additional capacitors connected in parallel to said differential node. In a relaxation oscillator for generating an oscillation signal by charging and discharging between a predetermined threshold voltage in the circuit, First and second transistors whose gates are cross-coupled to form differential nodes; And And a first and a second capacitor connected to each of said differential nodes and having the same value. The method of claim 4, wherein And a first and a second constant current source for supplying a constant current to the differential node, respectively. The method of claim 4, wherein And a first and a second resistor connected between a power supply voltage and the first and second transistors, respectively. The method of claim 4, wherein And said first and second capacitors are variable capacitors capable of varying capacitance. The method of claim 7, wherein And said variable capacitor comprises a plurality of additional capacitors connected in parallel to said differential node. The method of claim 8, And a plurality of switches for selectively connecting said plurality of additional capacitors to said differential node.