KR20050086293A - Method of manufacturing nand flash memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a NAND flash memory device, wherein a polysilicon layer for a control gate is formed as a double layer during a process of forming a gate in each of a cell region and a peripheral circuit region, and the first layer is formed as an etch protective film of an ONO dielectric layer. Since the ONO dielectric film in the region where the gate contact of the peripheral transistor is to be formed is removed, the structure in which the upper and lower layers of the ONO dielectric film are electrically connected to the gate of the peripheral transistor can simplify the subsequent metal wiring process contact process and secure the contact process margin. have.

Description

Method of manufacturing NAND flash memory device {Method of manufacturing NAND flash memory device}

The present invention relates to a method of manufacturing a NAND flash memory device, and more particularly, to a method of manufacturing a NAND flash memory device capable of improving a gate contact process.

Information stored in a cell of a nonvolatile memory device such as a flash memory device is not destroyed even when the power is cut off. Therefore, flash memory devices are widely applied to memory cards and the like. Flash memory devices are classified into two categories. One is a NAND-type flash memory device, and the other is a NOR-type flash memory device.

NAND flash memory devices can be divided into cell regions and peripheral circuit regions. The cell region is composed of a plurality of strings, and a source select transistor, a plurality of memory cells, and a drain select transistor are connected in series to each string. The source region of the source select transistor is connected with the common source line, and the drain region of the drain select transistor is connected with the bit line. The peripheral circuit area is composed of peripheral transistors such as PMOS transistors and NMOS transistors.

In the case of NAND flash memory devices, a method of forming gate contacts is different compared to other devices. The reason is that the ONO dielectric film is present between the gate materials, so that it must be removed and a gate contact formed.

1 is a cross-sectional view illustrating a method of manufacturing a conventional NAND flash memory device.

Referring to FIG. 1, after a well process and a Vt adjustment process, a tunnel oxide layer is formed on a semiconductor substrate 110 for a self-aligned shallow trench isolation (SA-STI) process. (111), a first polysilicon layer 112a for floating gates and a nitride film (not shown), a trench isolation process for device isolation using a device isolation mask, a well oxidation process, an insulation film deposition process for device isolation, chemical Through the mechanical polishing process and the nitride film removing process, a plurality of device isolation layers (not shown) are formed in the field region of the semiconductor substrate 110 to define the active region.

After forming the second polysilicon layer 112b for the floating gate on the entire structure where the device isolation layers are formed, the second poly for the floating gate to cover the active region while partially overlapping the device isolation layer by an etching process using a mask for the floating gate. The silicon layer 112b is patterned. An ONO dielectric film 113 is formed over the entire structure including the patterned second polysilicon layer 112b for floating gate. After forming the polysilicon layer 114 for the control gate, the metal-silicide layer 115 for the control gate, and the hard mask layer 116 on the ONO dielectric layer 113, the hard gate layer may be hardly etched using the mask for the control gate. Mask layer 116, metal-silicide layer 115 for control gate, polysilicon layer 114 for control gate, dielectric film 113, second polysilicon layer 112b for patterned floating gate and for floating gate The first polysilicon layer 112a is patterned to form gates in each of the cell region and the peripheral circuit region, and the gate spacer 117 is formed on each sidewall of each of the gates. Thereafter, the cell source region 118S, the cell impurity region 118C, the cell drain region 118D, and the source / drain junction portion 118P are formed through a source / drain ion implantation process.

As a result of the above process, the cell region is composed of a plurality of strings, and the source select transistor SST, the plurality of memory cells MC1 to MCn, and the drain select transistor DST are connected in series to each string. Is formed. In the peripheral circuit region, peripheral transistors (Peri-Transistors (PT)) such as PMOS transistors and NMOS transistors are formed. The source select transistor SST has a cell source region 118S, the plurality of memory cells MC1 to MCn have a cell impurity region 118C, and the drain select transistor DST has a cell drain region 118D. The peripheral transistor PT has a source / drain junction 118P.

After the etch stop layer 119 is formed on the entire structure including the transistors SST, MC, and DST, the first interlayer insulating layer 120 is formed on the entire structure of the resultant etch stop layer 119. After planarizing the surface of the first interlayer insulating layer 120 by a chemical mechanical polishing (CMP) process, the first interlayer insulating layer 120 and the etch stop layer 119 are etched by an etching process using a common source line contact mask. After forming a common source line contact hole exposing the cell source regions 118S and the device isolation layers (not shown), and forming a doped polysilicon layer to fill the common source line contact hole, a first interlayer insulating film ( The doped polysilicon layer is fully etched to expose 120 to form a common source line CSL. This process is called a cell source poly plug process.

The second interlayer insulating layer 121 is formed on the first interlayer insulating layer 120 including the common source line CSL, and the second interlayer insulating layer 121 and the first interlayer insulating layer 121 are formed by an etching process using a drain contact mask. 120 and the etch stop layer 119 are etched to form cell drain contact holes exposed to each of the cell drain regions 118D, and a doped polysilicon layer is formed to fill the cell drain contact holes. The doped polysilicon layer is etched entirely so that the insulating layer 121 is exposed to form cell drain contact plugs DCP. This process is called a cell drain poly plug process.

After the trench nitride layer 122 and the trench oxide layer 123 are sequentially formed on the second interlayer insulating layer 121 including the cell drain contact plugs DCP, damascene patterns are formed by a damascene process. . After depositing a metal such as tungsten so that the damascene patterns are buried, a front surface etching process is performed to form a metal wire (not shown) connected to the common source line (CSL) and a bit line 124D connected to the drain contact plug (DCP). ), A metal wire 124G connected to the gate of the peripheral transistor PT, and a metal wire 124P connected to the source / drain junction 118P of the peripheral transistor PT.

In the above-described conventional method, the gate of the peripheral transistor PT is the first polysilicon layer 112a for the floating gate, the second polysilicon layer 112b for the floating gate, the ONO dielectric film 113, the polysilicon for the control gate. The layer 114, the metal-silicide layer 115 for the control gate, and the hard mask layer 116 form a stacked structure. In the laminated structure, the first polysilicon layer 112a for the floating gate, the second polysilicon layer 112b for the floating gate, the polysilicon layer 114 for the control gate and the metal-silicide layer 115 for the control gate are practically It acts as a gate. However, since the ONO dielectric film 113 formed in the middle of these layers electrically insulates the lower layers 112a and 112b and the upper layers 114 and 115, the metal wiring 124G connected to the gate of the peripheral transistor PT is formed. It should extend to the lower layers 112a and 112b. In order to electrically connect the metal wirings 124G to both the lower layers 112a and 112b and the upper layers 114 and 115, the hard mask layer 116 may be formed by a separate gate mask process and an etching process after the control gate mask process and the etching process. ), A portion of the control gate metal-silicide layer 115 and the control gate polysilicon layer 114 are removed to form holes, and then the ONO dielectric layer 113 forming the bottom of the hole through the damascene process described above. Remove it. As described above, the conventional method forms a gate contact of the peripheral transistor PT through a complicated process.

Accordingly, an object of the present invention is to provide a method of manufacturing a NAND flash memory device capable of easily performing a gate contact process to secure a gate contact process margin.

According to an aspect of the present invention, there is provided a method of manufacturing a NAND flash memory device, wherein the first and second polysilicon for floating gates are patterned by performing a self-aligned shallow trench isolation process and a mask process for floating gates. Providing a semiconductor substrate having a layer; Forming a first polysilicon layer for the ONO dielectric film and the control gate over the entire structure; A gate contact mask process and an etching process may be performed to etch the first polysilicon layer for the control gate and the ONO dielectric layer in the region where the gate contact of the peripheral transistor is to be formed to expose an opening in which a portion of the second polysilicon layer for the floating gate is exposed. Forming; After forming the second polysilicon layer, the metal-silicide layer, and the hard mask layer for the control gate on the resultant formed opening, the cell region and the peripheral circuit through the etching process and the source / drain ion implantation process using the mask for the control gate Forming transistors in the region, wherein peripheral circuit transistors of the transistors are electrically connected with upper and lower layers of the ONO dielectric film through the openings; And forming a multi-layered interlayer insulating film over the entire structure including the transistors and applying the damascene process to form the wires, wherein the wires connected to the gates of the peripheral transistors are in contact with the metal-silicide layer.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to make the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In addition, the thickness or size of each layer in the drawings may be exaggerated for convenience and clarity of description. In the drawings, like reference numerals refer to like elements.

2 is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

Referring to FIG. 2, after the well process and the Vt adjustment process, a tunnel oxide layer is formed on the semiconductor substrate 210 for a self-aligned shallow trench isolation (SA-STI) process. 211, the first polysilicon layer 212a for floating gates and a nitride film (not shown), a trench isolation process for device isolation using a device isolation mask, a well oxidation process, an insulation layer deposition process for device isolation, and a chemical A plurality of device isolation layers (not shown) are formed in the field region of the semiconductor substrate 210 through the mechanical polishing process and the nitride film removing process to define the active region.

After forming the second polysilicon layer 212b for the floating gate on the entire structure in which the device isolation layers are formed, the second poly for floating gate to cover the active region while partially overlapping the device isolation layer by an etching process using a floating gate mask. The silicon layer 212b is patterned. An ONO dielectric film 213 is formed over the entire structure including the patterned second polysilicon layer 212b for floating gate. The first polysilicon layer 214a for the control gate is formed on the ONO dielectric film 213.

A gate contact mask process and an etching process are performed to etch the first polysilicon layer 214a and the ONO dielectric film 213 for the control gate in the region where the gate contact of the peripheral transistor is to be formed in the peripheral circuit region, thereby floating An opening is formed in which the gate second polysilicon layer 212b forms a bottom surface. The first polysilicon layer 214a for the control gate serves to protect the ONO dielectric layer 213 during the gate contact mask process and the etching process.

After forming the second polysilicon layer 214b for the control gate, the metal-silicide layer 215 for the control gate, and the hard mask layer 216 on the resultant opening, the hard gate layer is hardly etched using the mask for the control gate. Mask layer 216, control gate metal-silicide layer 215, control gate second polysilicon layer 214b, control gate first polysilicon layer 214a, ONO dielectric film 213, patterned Patterning the second polysilicon layer 212b for the floating gate and the first polysilicon layer 212a for the floating gate to form gates in each of the cell region and the peripheral circuit region, and the gate spacer 217 on each sidewall of the gates. do. Thereafter, a cell source region 218S, a cell impurity region 218C, a cell drain region 218D, and a source / drain junction 218P are formed through a source / drain ion implantation process.

As a result of the above process, the cell region is composed of a plurality of strings, and the source select transistor SST, the plurality of memory cells MC1 to MCn, and the drain select transistor DST are connected in series to each string. Is formed. In the peripheral circuit region, peripheral transistors (Peri-Transistors (PT)) such as PMOS transistors and NMOS transistors are formed. The source select transistor SST has a cell source region 218S, the plurality of memory cells MC1 to MCn have a cell impurity region 218C, and the drain select transistor DST has a cell drain region 218D. The peripheral transistor PT has a source / drain junction 218P.

After the etch stop layer 219 is formed on the entire structure including the transistors SST, MC, and DST, the first interlayer insulating layer 220 is formed on the entire structure of the resultant etch stop layer 219. After the surface of the first interlayer insulating layer 220 is planarized by a chemical mechanical polishing (CMP) process, the first interlayer insulating layer 220 and the etch stop layer 219 are etched by an etching process using a common source line contact mask. After forming a common source line contact hole exposing the cell source regions 218S and the device isolation layers (not shown), and forming a doped polysilicon layer to fill the common source line contact hole, a first interlayer insulating film ( The doped polysilicon layer is completely etched to expose 220 to form a common source line CSL. This process is called a cell source poly plug process.

A second interlayer insulating film 221 is formed on the first interlayer insulating film 220 including the common source line CSL, and the second interlayer insulating film 221 and the first interlayer insulating film are formed by an etching process using a drain contact mask. 220 and the etch stop layer 219 are etched to form cell drain contact holes exposed to each of the cell drain regions 218D, and a doped polysilicon layer is formed to fill the cell drain contact holes, and then a second interlayer is formed. The doped polysilicon layer is etched entirely so that the insulating layer 221 is exposed to form cell drain contact plugs DCP. This process is called a cell drain poly plug process.

After the trench nitride layer 222 and the trench oxide layer 223 are sequentially formed on the second interlayer insulating layer 221 including the cell drain contact plugs DCC, damascene patterns are formed by a damascene process. . After depositing a metal such as tungsten so that the damascene patterns are buried, a front surface etching process is performed to form a metal wire (not shown) connected to a common source line (CSL) and a bit line 224D connected to a drain contact plug (DCP). ), A metal wire 224G connected to the gate of the peripheral transistor PT, and a metal wire 224P connected to the source / drain junction 118P of the peripheral transistor PT.

In the above description, the gate of the peripheral transistor PT includes the first polysilicon layer 212a for the floating gate, the second polysilicon layer 212b for the floating gate, the ONO dielectric layer 213, and the first polysilicon layer for the control gate. 214a, the control gate second polysilicon layer 214b, the control gate metal-silicide layer 215, and the hard mask layer 216 are stacked. In the laminated structure, the first polysilicon layer 212a for the floating gate, the second polysilicon layer 212b for the floating gate, the first polysilicon layer 214a for the control gate, and the second polysilicon layer 214b for the control gate And the metal-silicide layer 215 for the control gate actually serves as a gate. In the past, the lower layers 212a and 212b and the upper layers 214a, 214b, and 215 were electrically insulated by the ONO dielectric film 213. However, in the present invention, as described above, the first polysilicon layer for the control gate ( After forming 214a on the ONO dielectric layer 213, the bottom surface of the second polysilicon layer 212b for floating gate may be formed in a region where a gate contact of the peripheral transistor PT is to be formed through a gate contact mask process and an etching process. Openings are formed to allow the lower layers 212a and 212b to be electrically connected to the upper layers 214a, 214b, and 215. Accordingly, the metal wire 224G connected to the gate of the peripheral transistor PT does not need to be formed to extend to the lower layers 212a and 212b as in the past, so that the metal wires 224G are formed on the lower layers 212a and 212b and the upper layer ( The hard mask layer 216, the metal-silicide layer 215 for the control gate, and the polysilicon layer for the control gate are performed by a separate gate mask process and an etching process, which are conventionally performed to electrically connect to all of the gates 214a, 214b, and 215. The troublesome process of removing a part of 214 may be omitted. Accordingly, the present invention exposes only the metal-silicide layer 215 through the damascene process to form the gate contact of the peripheral transistor PT.

The invention is not limited to the specific field herein described with reference to the suitable embodiments, but rather the scope of the invention should be understood by the claims herein.

As described above, the present invention performs the gate contact so that the upper layer and the lower layer are electrically connected during the gate forming process, thereby simplifying the subsequent metal wiring contact process and securing the contact process margin, thereby increasing the reliability of the device and the productivity of the product. Can improve.

1 is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to the prior art; And

2 is a cross-sectional view illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110 and 210: semiconductor substrate 111 and 211: tunnel oxide film

112a, 212a: first polysilicon layer for floating gate

112b, 212b: second polysilicon layer for floating gate

113 and 213: ONO dielectric film 114: polysilicon layer for control gate

214a: first polysilicon layer for control gate

214b: second polysilicon layer for control gate

115, 215: metal-silicide layer 116, 216: hard mask layer

117 and 217: gate spacer 118S and 218S: cell source region

118C, 118C: cell impurity region 118D, 118D: cell drain region

118P, 118P: source / drain junction 119, 219: etch stop film

120, 220: first interlayer insulating film 121, 221: second interlayer insulating film

122, 222: trench etch stop film 123, 223: trench insulating film

124D, 224D: Bitline

124P and 224P: Metal wiring for source / drain junctions of peripheral transistors

124G, 124G: metal wiring for gates of peripheral transistors

SST: source select transistor MC1, ..., MCn: memory cell

DST: Drain Select Transistor PT: Peripheral Transistor

CSL: Common source line DCP: Drain contact plug

Claims (1)

Providing a semiconductor substrate having a first and a second polysilicon layer for the floating gate patterned by performing a self-aligned shallow trench isolation process and a masking process for the floating gate; Forming a first polysilicon layer for the ONO dielectric film and the control gate over the entire structure; Performing a gate contact mask process and an etching process to etch the first polysilicon layer for the control gate and the ONO dielectric layer in an area where a gate contact of a peripheral transistor is to be formed to expose a portion of the second polysilicon layer for the floating gate Forming a closed opening; After forming the second polysilicon layer, the metal-silicide layer, and the hard mask layer for the control gate on the resultant formed opening, the cell region and the periphery through the etching process and the source / drain ion implantation process using the control gate mask Forming transistors in a circuit region, wherein peripheral circuit transistors of the transistors are electrically connected to upper and lower layers of the ONO dielectric film through the openings; And Forming a multi-layered interlayer insulating film over the entire structure including the transistors and applying a damascene process to form wires, wherein the wires connected to the gates of the peripheral transistors are in contact with the metal-silicide layer. Method of manufacturing a flash memory device comprising.