KR20050084121A - Register file gating to reduce microprocessor power dissipation - Google Patents

Abstract

A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto.

Description

Circuit device, power consumption control method, program storage medium and signal persistence medium {REGISTER FILE GATING TO REDUCE MICROPROCESSOR POWER DISSIPATION}

The present invention generally relates to controlling power dissipation of integrated circuits used in low power and other power sensing applications, for example.

Often, power consumption is a major design constraint for many integrated circuits (IC's) or "chips." For example, integrated circuits are increasingly being used in a wide variety of portable devices and other battery powered applications such as mobile phones and other wireless communication devices, portable computers, portable devices and game consoles. In addition, even in non-portable applications where battery life may not be critical, integrated circuits can easily overheat, requiring expensive and / or large cooling elements or requiring reduced IC reliability. The amount of power consumed by the IC plays an important role in battery life and heat generation of the electronic device.

In addition, as ICs become more complex and incorporate faster clock speeds and more transistors, the amount of power consumed by these ICs increases proportionally. As such, significant development efforts are directed to reducing IC power consumption.

For example, some efforts have been directed to reducing the power consumption of individual transistors in an IC, for example, through improved layout of the transistors and / or reduced supply voltages. To some extent, improvements in transistor design and shrinkage at the supply voltage level offset some of the increase in power consumption resulting from the use of more complex and higher performance ICs. However, further reductions are required for many power sensing applications.

For example, some ICs, such as microprocessors used in mobile applications, utilize voltage and / or frequency scaling to reduce the supply voltage and / or clock frequency and consequently reduce overall power consumption. However, this reduction is typically applied throughout the IC range and is accompanied by a reduction in processing performance.

Other designs may incorporate a sleep mode that puts the IC in a low power state in response to events such as specific commands or instructions or external interrupts. For example, some microprocessors support WAIT or HALT instructions that put the entire microprocessor in low power sleep mode. However, when in this mode, all effective processing operations at the microprocessor are typically stopped until the microprocessor is reawakened by an interrupt or other triggering event.

In another design, the IC can have different circuits that can be selectively enabled when not used to reduce overall power consumption. Typically, such circuits are selectively enabled or disabled in response to the implementation of certain instructions that are encountered in connection with the execution of a computer program, especially for ICs that incorporate some form of processor or processing core. Is enabled.

For example, some low power microprocessor designs allow individual functional units to be selectively disabled by routing certain "power down" instructions to their functional units. The power reduction instructions will be inserted by the compiler during compilation of the computer program, causing the instructions to be processed by individual functional units during execution of the computer program by the microprocessor. However, one disadvantage of this approach is that the ability to send individual instructions to a particular functional unit occupies the processing resources of that functional unit, thus dealing with operations that require other rich calculations. This reduces the effectiveness of processor pipeline residues.

The aforementioned power reduction instructions are associated with each instruction processed by the microprocessor and the use of control bits to dynamically control the enable state of each functional unit of the microprocessor. However, this type of design requires constant instruction decoding of each instruction, which may offset some of the reduction in some power consumption obtained by selectively disabling the individual functional units. In addition, the time required to disable or enable a particular functional unit in response to a particular set of control bits may limit the appropriate operating frequency of the microprocessor, thereby limiting the overall performance of the microprocessor. Moreover, adding control bits to each instruction increases the size of the code, increasing storage requirements or reducing the number of different instructions that may be supported.

Another disadvantage of the above instruction-based control schemes is that they are often limited to controlling the functional units of the microprocessor. Although functional units such as execution units, arithmetic logic units, floating point units, fixed point units, etc., make up a significant portion of the overall power consumption in the microprocessor, most designs It also contributes to power consumption but incorporates a significant amount of additional circuitry, such as caches, register files, and the like, which are not addressed by the control scheme described above.

Another design may include multiple instruction sets that support different power operations of the microprocessor. Typically, in such a design, one instruction set can fully utilize a microprocessor, while another instruction set may use only a portion of the microprocessor to reduce power consumption. However, one disadvantage of this approach is that only a limited number of processor utilization modes are fully supported and regulated, for example. In addition, the complexity of the code, and consequently the complexity of the decoding logic in the processor, can itself increase power consumption.

In related development fields, multiple versions of programs may be used to support different power consumption capabilities. However, storing multiple versions of a program requires the use of a runtime scheduler to select code versions for execution according to current power requirements, and storing multiple code versions results in more program memory and scheduler. It is possible to further increase power consumption by requiring the execution of.

In connection with selectively enabling individual circuits of the IC, various ways of disabling these circuits and thus minimizing their power consumption may be used. For example, clock gating is often used to disable clocking for a circuit, such that switching of the transistors in the circuit, in fact switching of states in the transistor, often often accounts for the maximum amount of power consumption in the circuit. Effectively restricts

For the functional unit of the microprocessor, an alternative way to disable the circuit is to shut down the power supply to the circuit. Another alternative is to deactivate the input signal to the circuit.

In addition, for other circuits, such as memory arrays used in dynamic random access memory (DRAM) devices, the clock signal and sense amplifiers are selectively gated off to disable banks of memory cells in the array and thus in the entire array. Reduces power consumption.

Despite the significant gains made in controlling power consumption in ICs such as microprocessors, further development in the field is needed.

For example, in the selective circuit disabling area, one potential area for improvement is in the control state of power consumption associated with the registers utilized by the processor or processing core of the IC. Registers are often composed of register files and are implemented using CMOS latches or flip-flops, resulting in relatively high power consumption. However, register utilization during many program executions is relatively low, so that many registers in the register file are not used without having to consume power at the IC. In some circumstances it may be desirable to disable certain registers, but conventional ways of disabling memory cells, such as those used in connection with DRAMs, are typically clock gating and / or sensing amplifiers. Disabling is used to disable the memory cell or bank of memory cells. This technique can be used to disable registers in a register file, but the extent to which power consumption is reduced by such techniques is limited.

These and other advantages and features that characterize the invention are described in the claims appended hereto and forming additional parts thereof. However, for a better understanding of the invention and for a better understanding of the advantages and objects obtained through its use, reference should be made to the accompanying drawings, in which the drawings and exemplary embodiments of the invention are described.

1 is a block diagram of a media processor including a dynamic power consumption control circuit in accordance with the present invention;

2 is a block diagram of a central processing unit, referenced in FIG. 1, comprising a dynamic power distribution control circuit in accordance with the present invention;

3 is a block diagram referenced in FIG. 2 and including enable logic to selectively disable a bank of registers;

4 is a block diagram of an exemplary instruction format for a power control instruction suitable for controlling power consumption in the media processor of FIG. 1;

5 is a flow chart illustrating a program flow of a power consumption optimization routine consistent with the present invention;

6 is a block diagram illustrating exemplary program processing by the media processor of FIG. 1;

7 is a block diagram of an alternative manner of controlling the power distribution of a register file as shown in FIG.

The present invention provides a power consumption control capability in a register file through a bank design coupled to enable logic configured to selectively gate off provided clock, address and data inputs to selectively disable unused banks of registers. By providing a circuit arrangement and method for controlling the power consumption provided, the problems associated with the prior art and other problems are described. Specifically, registers in a register file are divided into a number of banks, each of which can be selectively disabled by enable logic to selectively gate off various clock, address, and data inputs for each such bank.

By gateping off the address and data inputs in addition to the clock inputs provided to the various banks of registers provided in the register file, a greater reduction is achieved in power consumption than to gate off only the clock inputs. Also, when the register file is implemented using a resistor fabricated from a CMOS latch or flip-flop that features relatively high wiring capacitance, the reduction in power consumption is more pronounced, which is typically due to gating being a register file bank. This is because the switching action on the internal long wiring is suppressed.

Dynamic power consumption control consistent with the present invention may include either or both of the two concepts that provide significant advantages over conventional power consumption control techniques. The first concept is uniquely applicable to implementing power consumption control over the entire register file utilized by the processor or processing core. In accordance with the present invention, a register file is divided into a number of banks of registers, each bank of registers comprising a clock, data, and address input line. The enable logic is coupled to such a register file to selectively gate off or disable the clock, data, and address input lines for any unused bank of registers in the register file.

The second concept is more generally suitable for a software based approach to controlling power consumption in integrated circuits, including processors or other programmable circuits that process software instructions. In particular, power control instructions embedded in program code executed by a processor are used to control the power mode of a number of hardware resources that are selectively configurable into two or more power modes, each of which is a hardware resource. Has a specific power consumption state for.

Each power control instruction includes power control information disposed in an operand that can set the power mode of a plurality of hardware resources. In addition, once a power mode is set by a particular power control instruction, the set power mode is followed by, for example, until the power mode is reset by another power control instruction or a special event (eg, an external interrupt). Used by the processor during the processing of an instruction.

Each of these concepts will be described in greater detail in connection with the description of an exemplary embodiment of a processor integrated circuit using software based power consumption control of a register file. However, before describing this particular embodiment, exemplary hardware and software environments are described in greater detail below.

Referring to the drawings, like numerals indicate similar parts throughout the several views, and FIG. 1 illustrates an example of a data processing system 10 including a media processor 12 that implements dynamic power consumption control consistent with the present invention. Illustrates a typical hardware and software environment. The media processor 12 may be, for example, a PNX1300 series trimedia-compatible media processor available from Philips Semiconductors, or alternatively another media processor such as Equator Map1000, TI TMS320C6xxx, BOPS ManArray, etc. It may be implemented as an architecture. The media processor 12 includes a system-on-chip comprising a central processing unit (CPU) or processing core 14 coupled via an internal bus 16 to a number of additional circuit elements embedded in the same integrated circuit device. system-on-chip (SOC) integrated circuit devices.

For example, the CPU 14 may be implemented as a register file comprising, for example, a VLIW processor core comprising a 32-bit address space and 128 32-bit general purpose registers. The processor core includes 27 functional units accessible via five issue slots as well as 16-KB data and 32-KB instruction caches, the data cache being dual-ported, Both caches are eight-way sets that are easy to combine with 64-byte block sizes.

The working memory of processor 12 is provided by external memory 18 (e.g., SDRAM memory) accessed via main memory input / output interface block 20, while peripheral bus 22 (e.g. Connectivity to external peripherals in a PCI bus is facilitated by an external bus interface block 24.

To support various media-processing functions, the media processor 12 may include video in / out blocks 26 and 28, audio in / out blocks 30 and 32, SPDIF output block 34, and I2C interface block 36. ), A synchronous serial interface block 38, an image coprocessor block 40, a DVD descrambler (DVDD) block 42, a variable length decoding (VLD) coprocessor block 44, and a timer block 46. Various specialized media processing circuits.

Referring now to FIG. 2, the CPU 14 is illustrated in more detail, including a bus interface unit (BIU) 50 connecting the internal bus 16 to the instruction cache 52 and the data cache 54. Shown. Instructions from the instruction cache 52 are provided to one or more decoders, which may include one or more functional units 58, such as various arithmetic logic units, floating point units, subword-parallel multimedia operating units, Instructions are output to the loading / storage unit, SIMD multimedia operating unit, vector multimedia operating unit, multiplier, branch unit and the like. As mentioned above, the CPU 14 supports VLIW instructions, so that multiple instruction slots (e.g., five) when processing a VLIW instruction to route multiple operations encoded with the VLIW instruction to multiple functional units simultaneously. May be used.

The CPU 14 is typically implemented with a load / store architecture, where the functional unit 58 accesses a register file 60 containing 128 32-bit general purpose registers. Additional support registers are program control and status word (PCSW) registers 61, for example floating point operations, byte sex (big / little endian), interrupt enable, exceptions. Are used to set various configuration settings for the CPU. In order to provide dynamic power consumption control consistent with the present invention, the CPU 14 also includes a power control circuit 62 in which a support register 64, referred to herein as a power mode register, is illustrated. In this register, power mode state information is stored for various hardware resources of the media processor 12 that can be selectively disabled to minimize power consumption in the media processor. In some implementations, it may be desirable to also support the storage of power mode state information in the PCSW or other support registers of the CPU so that the power mode state information is combined with other state information not related to power consumption control.

The power control circuit 62 applies one or more enable signals 66 to enable logic embedded in the various hardware resources of the CPU 14 and / or the media processor 12 to power consumption of the entire CPU 14. Optionally, control power consumption elsewhere in the media processor 12. In such a case, the hardware resource may substantially represent any electronic circuit of the integrated circuit that may be useful and / or desirable to disable for the purpose of reducing power consumption in the integrated circuit. In the CPU 14, for example, the BIU 50, the caches 52, 54, the instruction decoder 56, the functional unit 58, and the register file 60 are all enabled logic on each block. Due to the presence of reference numeral "E", it is illustrated as a hardware resource that can be selectively disabled.

In the illustrated embodiment, the power control circuit 62 selectively applies the enable signal 66 in response to the power mode state information stored in the power mode register 64. This state information is stored in the register 64 in response to power control instructions contained within the program executed by the CPU 14. These power control instructions are typically decoded by the instruction decoder 56 and update the power mode register 64 in much the same way that other conventional registers store instructions commonly used in the art. Used to.

Enable signal 66 is used to fully enable / disable an entire block or hardware resource, or enable / disable only a portion of such block / resource and / or for all or only part of such block / resource It will be appreciated that it may be used to select from among a number of active power consumption states. For example, a hardware resource may have two or more power modes, such as sleep mode or fully off mode, two or more low power or energy saving modes, and full power mode. It can also support. Although a single line is illustrated for each enable signal 66 in FIG. 2, it is noted that multiple signal paths may be used to selectively enable some of each hardware resource depending on the degree of change in each granularity. Will be recognized. In addition, it is recognized that hardware resources may actually utilize such technology as long as any known energy saving technology or power consumption reduction technology known in the art can be selectively enabled under the control of the power control circuit described herein. Will be.

In the embodiments discussed below, for example, hardware resources, such as register files, are individually registered into multiple register banks that can be selectively disabled in response to power control instructions in a program executed by a processor. It may be controlled to organize the file to reduce power consumption. In this regard, each register bank may itself be considered to represent a separate hardware resource.

In the illustrated embodiment, each register bank utilizes enable logic to gate off the address and data input signals for each disable register bank as well as the clock signal. As is more apparent below, gate off clock, address, and data input signals often provide the best energy savings collectively because CMOS latches or flip-flops used in conjunction with general purpose registers often result in higher wire capacitance. . However, other ways of disabling the register file may be used in some embodiments consistent with the present invention.

In addition, although the power control circuit 62 is illustrated as being used to control hardware resources disposed solely within the CPU 14, the power control circuitry may be located anywhere in the same integrated circuit, for example. It will be appreciated that it may be used to control other hardware resources consistent with the present invention, including resources (eg, all or some of the functional blocks illustrated in FIG. 1) and hardware resources disposed on other integrated circuits. . In fact, the power control circuitry in accordance with the present invention may include, for example, register files, memory, caches, slots of occurrence, buses, functional units, functional blocks, IO pads or pins, buffers, instruction reorder logic, embedded field programmable gate arrays. With respect to a wide variety of hardware resources, including (FPGA's), coprocessors, or substantially any type of electronic circuitry that can be disabled and / or set to such a state with reduced levels of power consumption. Can also be used to control consumption. In addition, any of the circuits described above may be selected, for example, by individual portions of such circuits (e.g., individual banks or registers of register files, individual cache sets, individual lines or groups of buses, etc.). It can also be considered to embed a number of hardware resources that can be controlled separately so that they can be disabled.

Further, while power control circuit 62 is illustrated as being disposed in CPU 14, it will be appreciated that power control circuitry may be functionally separate from the CPU or other processing cores. In general, the particular manner in which the power consumption control function is allocated on the integrated circuit may vary in different embodiments, and as such, the invention is not limited to the specific implementations discussed herein.

In addition, an implementation of the power control circuit 62 in the media processor is provided herein by way of example. Power consumption control, in particular the use of power control instructions as described below, may be utilized in a wide variety of alternative integrated circuits consistent with the present invention. Power control instructions may be used in connection with various processor architectures including, for example, VLIW, EPIC, RISC, CISC, DSP, superscalar, and the like. In addition, the present invention is not limited to use within an SOC architecture or other architecture in which the processing core is integrated with other support circuitry.

In many cases, the significant benefit associated with reduced power consumption is that low-availability parallel hardware resources can often be selectively disabled depending on program usage needs, so that parallel hardware resources are always low during VLIW, EPIC, superscalar, or program execution. It will be realized in connection with other broad generation architectures that may be used. However, the present invention is not limited only to applicability related to a wide range of generation architectures and the like.

In general, it will be appreciated that any hardware-based functionality described herein is typically implemented as a circuit device embedded within one or more integrated circuits, and optionally as a circuit device that includes additional support electronics. In addition, as is well known in the art, integrated circuits are typically designed and fabricated using one or more computer data files, referred to herein as hardware designated programs, which designate the layout of circuit devices on the device. do. The program is typically generated by a design tool, which is used sequentially during manufacturing to create a layout mask that defines the circuit arrangement applied to the semiconductor wafer. Typically, a program is provided in a predefined format using hardware definition language (HDL) such as VHDL, verilog, EDIF, and the like. Although the present invention will be described with reference to circuit devices implemented in fully functional integrated circuits and data processing systems using the same, those skilled in the art can also distribute circuit devices in accordance with the present invention as various types of program products and It will be understood that the invention applies substantially the same regardless of the particular type of signal bearing media used to implement the distribution. Examples of signal persistent media include recordable media such as volatile and nonvolatile memory devices, floppy and other removable disks, hard disk drives, magnetic tapes, optical disks (eg, CD-ROMs, DVDs, etc.), in particular digital and Transmission media such as, but not limited to, analog communication links. In some embodiments consistent with the present invention, other integrated circuit technologies, such as FPGAs, may also be used to implement some hardware-based functionality discussed herein.

As described above, the power control circuit 62 may be controlled through power control instructions embedded in a program executed by the CPU 14. These power control instructions may be generated by the programmer or, alternatively, may be automatically added to the program by a computer, linker, optimizer, or the like. In addition, such automatic addition of program control instructions typically occurs before runtime, and in some embodiments, runtime addition of program control instructions may, for example, require just-in-time compilation / optimization or In connection with runtime interpretation / instruction decoding, it may be used.

Regardless of the particular implementation (eg, before or after runtime, in a compiler or optimizer, etc.), the automatic addition of program control instructions is typically implemented using one or more routines, which will be described in more detail below. Whether implemented in an operating system or in a module or sequence, or even a subset, of a particular application, element, program, object, instruction, these routines will be referred to as "computer program code" or simply "program code." Program code typically includes one or more instructions that reside several times in various memories and storage devices of a computer or data processing system, and when the computer reads and executes the data on one or more processors, the computer may modify various aspects of the invention. Allows you to perform the steps necessary to specify or implement the components. In addition, although software-related aspects of the present invention have been described with reference to computers and data processing systems and will be described below, those skilled in the art can distribute the various embodiments of the present invention as various types of program products and substantially execute the distribution. It will be appreciated that the present invention is practically applicable irrespective of the particular type of signal sustaining medium used to do so.

In addition, the various programs described below may be identified based on an application implemented in a particular embodiment of the invention. However, it should be understood that any particular program nomenclature that follows is merely used for convenience, and the present invention should not be limited to being used only in any particular application identified and / or implied by such a list. In addition, computer programs may be used in routines, processes, methods, modules, as well as in various ways, in which program functions may be assigned among the various software layers residing within a typical computer (eg, operating system, libraries, APIs, applications, applets, etc.). Given a substantially infinite manner, which may be organized into objects, objects, and the like, it is to be understood that the invention is not limited to the specific organization and assignment of program functions described herein.

Those skilled in the art will appreciate that the exemplary embodiments illustrated in FIGS. 1 and 2 are not intended to limit the invention. Those skilled in the art will also recognize that other alternative hardware and / or software environments may be used without departing from the scope of the present invention.

As noted above, dynamic power consumption control consistent with the present invention may include any or both of the two concepts that provide a substantial overall benefit over conventional power consumption control techniques. The first concept is uniquely applied to implementing power consumption control for register files utilized by a processor or processing core. The second concept applies more generally to software-controlled schemes for controlling power consumption in integrated circuits. In order to facilitate a better understanding of each of these concepts, an exemplary embodiment that incorporates both concepts is described below with respect to FIGS. However, it will be appreciated that the two concepts discussed below may be used independently in other embodiments, and as such, the invention is not limited to the specific implementations discussed below.

3 through 6 illustrate software based control of power consumption in a register file used in particular in a triple media-compatible media processor. For example, in many programmable architectures (eg, VLIW, EPIC, and superscalar), register files have been found to be a big contributor to overall power consumption. In some applications, it has been found that register files may consume up to 20% of the power consumed by the processing core. Especially in media processors, register files are often relatively large and often contain many ports and registers. Some triple media-compatible processors use, for example, register files with 128 registers and 20 individual ports. Register file design is wire-oriented, and relative power consumption increases with technology scaling. As such, reducing power consumption in a register file often results in substantial savings of energy consumption in the media processor.

Often, the size of a register file in any programmable architecture is determined by the application requiring the highest number of active variables, which are typically stored in a register file. However, while running other applications with fewer active variables, many of the registers in the register file still remain unused. In addition, within a particular application, the utilization of the register file may vary substantially at different points in the application. By way of example, triple media-compatible media processors have been found to have relatively high peak register utilization during AC3 decoding, while often average register utilization is relatively low during other computations in typical applications. Thus, depending on the current requirements of the application in operation, it may be highly desirable to disable the unused portion of the register file to reduce the overall power consumption.

As shown in particular in FIG. 3, a method of selectively disabling some register files may be performed by dividing a register file on the address space (here, register file 60 in FIG. 2) into several banks 70, for example. For example, in response to the enable signal 66 supplied to the banks via the power control circuit 62 (FIG. 2), by conditionally enabling or disabling these banks.

Each bank 70 may include a number of registers in which the register space represented by the register file is divided into register sets. For example, for a register file with 128 registers, it may be desirable to divide the register space into eight banks for each of the 16 registers. Other ways of partitioning registers may be used, but it may be desirable, for example, to use the most significant address input as the bank select signal and select the particular register in the selected bank using the least significant address input. For example, when a register file is divided into eight 16 register banks, seven addresses are used in which three high rank inputs are used as bank select signals and four low rank inputs are used as register select signals.

As is well known in the art, register file 60 includes output selection logic 72 as well as clock input 74, address in input 76 and data in input 78. The register file 60 also outputs data to the data out output 80. It will be appreciated that depending on the number of registers and the width of each register as well as the number of input / output ports supported by the register file, different numbers of address in, data in and data out signals may be provided in the register file. In addition, input selection logic (not shown) may be used to support simultaneous access of multiple registers by multiple functional units.

To selectively disable banks of registers, clock, address in and data in inputs are provided to each bank through enable circuits 82 disposed in each bank. In addition, an enable signal 66 from the power control circuit is further supplied to each enable circuit 82 to selectively gate off or protect the clock, address in and data in inputs for the connected resistor bank 70. .

The enable circuit 82 in each bank may be implemented in many ways consistent with the present invention. For example, one way of implementing an enable circuit is by using a series of gate transistors, which are coupled to the respective clock, address in and data in inputs to the register bank and dedicated to the register bank. Gated by the enable signal 66.

Gate off the address and data inputs for each bank, but not the clock inputs only, typically due to the relatively high wiring capacitance connected to the CMOS latch or flip-flop (synchronized) register implementation. This is obtained because gating typically inhibits switching action for relatively long interconnects used within register file banks. However, it should be appreciated that in some implementations, additional gating logic may cause additional delays to limit performance to a small range. It will also be appreciated that the present invention may be used in connection with register files implemented using different register implementations.

In order to implement software based power consumption control of register file 60, power control instructions are supported in the instruction set architecture of CPU 14. An exemplary format for power control instructions is illustrated at 90 in FIG. 4. As shown, the power control instruction 90 contains an opcode 92 that identifies the instruction as a pwr_control instruction and power control information used to set the power mode for the various banks of registers in the register file 60. It may also include an operand 94 that specifies. Operand 94 may be implemented as an immediate operand, including, for example, a bit mask with enable / disable bit 96 assigned to each bank of registers in a register file. It may be. Thus, for example, for eight banks of register file, an 8-bit immediate operand may be supported in instruction 90.

At a more general level, the size of operand 94 may be specified by a formula.

j is the number of hardware resources to be controlled (here register banks) and Modes (i) is the number of power modes of hardware resource i.

Other instruction formats may alternatively be used. For example, as shown in FIG. 4, it may be desirable to support an optional source register operand 97 that identifies a register in which power mode state information is stored. Thus, rather than storing the power mode state information directly in the power control instructions to perform the operation immediately, the power mode state information is stored in a separate register, and the register operation can be used to retrieve the desired power mode state information. Other addressing modes may alternatively be supported.

In addition, as shown in FIG. 4, it may be desirable to support a guard operand 98, which specifies a condition that must be met before the power mode state information specified by the power control instruction is applied. Can also be used to specify. Indeed, any known condition may be used in accordance with the present invention.

2, in the illustrated embodiment, power control instructions are processed by the CPU 14 to update the power mode register 64 and power control information is specified in the power control instructions. As such, it may be desirable for the power mode register 64 to have the same mapping as the immediate operands to the power control instructions so that the power control instructions are simply processed as an immediate write to the power mode register.

In addition, as noted above, in some cases it may be desirable to store power mode state information using an existing register, such as a PCSW register. In such a case, the power control instruction will not require a separate opcode. Instead, an opcode used to write to an existing appropriate register may be used, with the operand updating those bits used in connection with storing power mode state information.

The power control instructions may be included in the executable program code in many ways consistent with the present invention. For example, power control instructions may be added to source code by a programmer during development. Alternatively, compilers, optimizers, linkers, etc. may perform simulation or static analysis of the program under development to determine the appropriate location to insert power control instructions based on the predicted resource usage.

In addition, profiling, static analysis, or simulation of a program may be used to determine which hardware resources should be used and which resources should be disabled during certain sections of the program. For example, if only ten registers are required in a section of a program but it is determined which ten registers are not important for program semantics, the compiler uses registers from a limited number of register banks. It may then be desirable to insert appropriate power control instructions into the program code to disable unused register banks. Also, if such ten registers are initially distributed across several register banks, it may be desirable to rearrange the registers to concentrate the registers within a reduced number of register banks.

FIG. 5 illustrates a power consumption optimization routine 100 that may be executed, for example, during editing or optimization of a computer program to optimize sections of the computer program for optimal power consumption. For each particular section of the program, the routine 100 first analyzes the section to determine hardware resource usage by the program code section at block 102. Next, block 104 is optionally executed to relocate resources to focus resource usage (e.g., to confine registers to a limited number of register banks) to a limited set of hardware resources. Block 106 then generates the appropriate power control instructions and inserts them into the program code to disable any unused resources. Thereafter, processing of the section is completed.

In addition, routine 100, or a functionally similar routine, may also be used at runtime, for example in connection with interpretation or precise editing. It will also be appreciated that the routine 100 may be used at runtime, for example in a superscalar processor architecture, in connection with the generation of instructions intended for parallel and / or out-of-order operations. . In such an implementation, the compiler and runtime hardware preferably provides power control to minimize the impact on other speculated instructions, for example by assigning side effects to the power control instructions that limit runtime speculation. You must limit the reordering of instructions. In another embodiment, the computing system may schedule / generate power control instructions when the CPU / processor is not fully loaded with the calculations.

Alternatively, the routine 100 may be used in connection with an explicit parallel instruction set architecture such as VLIW or EPIC code when the detection of parallel operations occurs during editing. In such implementations, insertion of power control instructions may be considered to include inserting power control operations into a larger VLIW or EPIC instruction that includes multiple operations.

Program code inserted while the power control instructions are being edited or during runtime includes program control instructions interspersed within the program code only at a time when a change in hardware resource usage is desired. In addition, it is often desirable for a single power control instruction to be able to control the enable / disable state of multiple hardware resources. As such, minimal additional processing overhead is typically associated with power control instructions consistent with the present invention to minimize any adverse performance effects due to inserting additional instructions into program code.

6 diagrammatically illustrates some exemplary executions of a program compiled in the manner described above, as may be used, for example, in connection with a triple media-compatible media processor. In this example, there are five occurrence slots designated by reference numerals 110, 112, 114, 116, and 118, and an instruction executed in each occurrence slot during each cycle (cycles 0-4) causes each occurrence for that cycle. Illustrated in the slot. In addition, the register file contains 128 registers (denoted r0 to r127) divided into eight banks, and the power control instructions indicate that when the binary " 1 " encounters at the operand bit mask location associated with the selected bank. It is assumed that the operand is used immediately when it is enabled. In this example, the latency of the pwr_control instruction is one cycle, but it will be appreciated that the pwr_control instruction has more than one cycle in some implementations.

Also, during cycle 0, one of the instructions processed by the CPU (here generation slot 112) is a power control instruction with 0x1b (binary 00011011), which is a register file (i.e. registers r0-r31, r48-r79). It is assumed that only banks 1, 2, 4, and 5 are enabled. As a result of the execution of this instruction, the power mode register 64 (FIG. 2) is updated to store the value 0x1b (binary 00011011). As a result, during successive cycles, register banks 3, 6, 7, 8 are disabled. However, note that during the execution of the power control instruction in cycle 0, all register banks may be used for access by other instructions (assuming all banks have been previously enabled).

During cycles 1 and 2, no additional power control instructions are encountered. As a result, register banks 3, 6, 7, and 8 remain disabled, and all instructions access registers from banks 1, 2, 4, and 5 (r0-r31, r48-r79). It is limited to.

During cycle 3, the power mode state information stored in power mode register 64 continues to keep register banks 3, 6, 7, and 8 disabled. However, one of the instructions executed during this cycle (generated into occurrence slot 118) is a power control instruction with an immediate operand of 0xff (binary 11111111), for all eight banks of the register file for the instruction executed in cycle 4. Enable.

The dynamic power consumption control technique described above offers many advantages over conventional designs. Compared to a conventional design requiring an instruction to be routed to a specific functional unit or a conventional design requiring an enable / disable command to be attached or constantly decoded to all instructions, there is a large variety of hardware resources with minimal processing overhead. Significant flexibility is provided with regard to controlling.

In addition, the foregoing techniques provide the adaptability to account for various power consumption related occurrences, so as to balance performance and power consumption in a number of useful ways. For example, using the techniques described above, processor performance may be scaled up without, for example, increasing power consumption for code that adds registers or functional units but does not use extra resources. . Also, for applications where performance is not critical, power control instructions may sacrifice performance for lower power consumption, for example by scheduling operations as limited resources but disabling other resources.

It will be appreciated that for software based power consumption control, alternative instruction formats, alternative editing, optimization and / or scheduled routines, and alternative processor architectures may be used in other embodiments consistent with the present invention. In addition, other resource disable circuits as described above in connection with the bank register file design described herein may be used in connection with software based power consumption control consistent with the present invention.

It will also be appreciated that with respect to the bank register file design described herein, other mechanisms than the software based control mechanism described herein may be used in accordance with the present invention. For example, a hardware based control mechanism may be used to dynamically enable certain hardware resources in accordance with the dynamic decoding of read / write addresses. By way of example, FIG. 7 is a gating used to selectively gate off clock input 126, data in input 128, and address in input 130 provided in a register file similar to register file 60 of FIG. Illustrates an alternative register file design 120 that includes a plurality of register banks 122 each having logic 124. However, rather than being provided with enable signals from software-based control circuitry, register file 120 may use an address decoder (dynamically generated) to generate individual bank enable signals 136 for selectively disabling various unused register banks. Hardware-based enable logic circuit 132 including 134.

The address decoder 134 may, for example, selectively disable a register bank during any cycle in which no registers in such a bank are generally accessed. Especially for register files that support multiple input ports, it is easy to determine which registers are accessed for a given cycle, and to register files without any change in compiler and / or instruction set architecture used by a particular processor design. It provides the ability to selectively reduce power consumption.

Various further improvements will be apparent to those skilled in the art and have the benefit of this statement. Accordingly, the invention is subject to the claims appended hereto.

Claims (21)

In the circuit device 14, (a) a register file 60 divided into a plurality of banks 70, each bank comprising at least one register 82, at least one clock input 74, an address input and a data input; , (b) an coupling coupled to the register file and configured to selectively disable at least one unused bank 70 of the plurality of banks by gate-off of the clock 74, address and data inputs Including logic 66 Circuit device. The method of claim 1, Each register in the register file includes at least one of a CMOS flip flop and a CMOS latch. Circuit device. The method of claim 1, The enable logic is a plurality of enable circuits 82-each enable circuit is coupled to a register bank of the register file, and each enable circuit is provided for each clock provided to the connected bank in response to an enable signal. 74), configured to gate off an address and data input. Circuit device. The method of claim 3, wherein Each enable circuit includes a plurality of gate transistors, each gate transistor coupled to one of the clock, address, and data inputs, each gate transistor responsive to the enable signal provided to the enable circuit. Circuit device. The method of claim 1, Further comprising output selection logic 80 coupled to each of the plurality of register banks; Circuit device. The method of claim 1, The enable logic 132 is configured to dynamically determine which register bank is not used and generate an enable signal for each bank in response to the dynamic decision. Circuit device. The method of claim 6, The enable logic includes an address decoder configured to generate the enable signal in response to at least one address specified by the address input provided in the register file. Circuit device. The method of claim 1, The enable logic is configured to generate an enable signal for each bank in response to the stored power mode state information. Circuit device. The method of claim 8, And a support register configured to store the power mode state information, wherein the status register is configured to be updated in response to a power control instruction residing in program code executed by a processor. Circuit device. The method of claim 9, The status register includes a power mode register Circuit device. The method of claim 9, The status register further stores status information not related to power consumption control. Circuit device. The method of claim 1, The circuit device is disposed on an integrated circuit Circuit device. The method of claim 12, The circuit device is arranged in the processor of the integrated circuit Circuit device. A program product comprising a hardware definition program defining a circuit arrangement of claim 1, and a signal bearing medium for sustaining the hardware definition program, comprising: The signal persistent medium includes at least one of a transmission medium and a recordable medium. Program product and signal persistence medium. A method for controlling power consumption in a register file, (a) receive first and second enable signals directed to first and second register banks, respectively, of the plurality of register banks in the register file, each register bank having at least one register and at least one clock input; Including address input and data input, (b) selectively disabling the first register bank in response to the first enable signal by gateing off the clock, address, and data inputs; Power consumption control method. The method of claim 15, Each register in the register file includes at least one of a CMOS flip flop and a CMOS latch. Power consumption control method. The method of claim 15, Selectively disabling the first register bank comprises: a plurality of gate transistors coupled to the enable signal to the first register bank, each gate transistor coupled to one of the clock, address, and data inputs. Comprising the steps of providing Power consumption control method. The method of claim 15, Dynamically determining that the first bank is not used; In response thereto, generating the first enable signal. Power consumption control method. The method of claim 18, Dynamically determining that the first register bank is not used comprises decoding at least one address specified by the address input provided in the register file. Power consumption control method. The method of claim 15, Generating the first and second enable signals in response to stored power mode state information. Power consumption control method. The method of claim 20, The stored power mode state information is stored in a support register, The method further includes updating the support register in response to a power control instruction residing in program code executed by a processor. Power consumption control method.