CN110609601A - Low-power-consumption processor register file control method - Google Patents
Low-power-consumption processor register file control method Download PDFInfo
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- CN110609601A CN110609601A CN201910790729.6A CN201910790729A CN110609601A CN 110609601 A CN110609601 A CN 110609601A CN 201910790729 A CN201910790729 A CN 201910790729A CN 110609601 A CN110609601 A CN 110609601A
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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Abstract
The invention discloses a low-power-consumption processor register file control method, which comprises the following steps: the method comprises the steps of grouping register files in a processor with a reduced instruction set, adopting a dynamic voltage regulation technology and a clock gating technology for each group of registers, adding a state control register to control the power supply state of the register group and the switch state of a clock gating unit, and configuring the value stored in the state control register through control and state register instructions to enable the processor to operate program segments with different calculation intensity degrees by different power supply configurations of the register group. The invention can reduce the power consumption of the register file of the processor.
Description
Technical Field
The invention belongs to the technical field of low-power-consumption design of a processor, and particularly relates to a low-power-consumption processor register file control method.
Background
A large number of emerging applications rise, such as wearable electronic equipment, implantable electronic equipment, the Internet of things and the like, so that the life style of the human society is more convenient. However, the power supply for these applications is very strict, and usually only can be a micro battery or environmental energy such as solar energy, electromagnetic wave or even body temperature, and the power supply and energy replacement are severely limited. Therefore, the power consumption of processors, which are the "brains" of these applications, is becoming increasingly significant.
Currently, research for low power processors is mainly being conducted around asynchronous circuit technology, dynamic voltage and frequency regulation technology, sub-threshold technology, and clock gating technology. While these studies have resulted in some success, they have not been a low power method designed for the circuit characteristics and specific applications of processors.
During processor operation, the register file consumes a significant portion of the processor core energy. Many reduced instruction set processors contain 32 integer registers and 32 floating point registers, which in some low power processors consume up to more than 60% of the processor core power. Among all registers, the functions of a plurality of registers are similar or identical, and the plurality of registers with the same functions can reduce data collision and improve performance. However, most applications do not use all registers, and even in some simple applications, only a small portion of registers are used by the program. At this point, unused registers may greatly increase the power consumption of the processor and may not bring about any performance improvement.
Disclosure of Invention
The invention aims to provide a low-power-consumption processor register file control method for reducing the power consumption of a processor register file.
The technical scheme adopted by the invention is that the method for controlling the register file of the processor with low power consumption comprises the following steps: the method comprises the steps of grouping register files in a processor with a reduced instruction set, adopting a dynamic voltage regulation technology and a clock gating technology for each group of registers, adding a state control register to control the power supply state of the register group and the switch state of a clock gating unit, and configuring the value stored in the state control register through control and state register instructions to enable the processor to operate program segments with different calculation intensity degrees by different power supply configurations of the register group.
The present invention is also characterized in that,
the reduced instruction set in the reduced instruction set processor comprises MIPS or RISCV, the reduced instruction set processor is provided with 32 integer registers with 32 bit width, the number is 0-31, and if the reduced instruction set processor supports the expansion of a single-precision floating-point instruction set or a double-precision floating-point instruction set, the reduced instruction set processor is provided with 32 single-precision floating-point registers with 32 bit width or 32 double-precision floating-point registers with 64 bit width.
The integer register, the single-precision floating point number register and the double-precision floating point register are similar in function, and the 32 registers can respectively store a constant 0, a frame pointer, a stack pointer and a global pointer, store a function parameter, a return value and a return address, store a temporary variable and store a variable.
The number of registers for storing function parameters is more than 4, the number of registers for storing temporary variables is more than 7, and the number of registers for storing and saving variables is more than 8.
The specific steps of grouping the register files are as follows:
dividing 32 integer registers, 32 single-precision floating-point registers and 32 double-precision floating-point registers into 8 groups according to the serial numbers of the registers in sequence respectively: 0-3, 4-7, 8-11, …, each group containing 4 registers, 32 bits for each integer register and single precision floating point register, and 64 bits for each double precision floating point register.
The method comprises the following specific steps of adopting dynamic voltage regulation for each group of registers:
the circuits of 8 groups of registers are respectively placed in 8 independent voltage domains, each voltage domain is provided with two groups of power supply voltages of normal voltage and low voltage, the corresponding register group works in the normal voltage power supply state or the low voltage power supply state by controlling the switching states of two groups of power supply gate control switches, and when a certain register group does not need to be used, the register group works in the low voltage power supply state, so that the power consumption of the register stack is reduced.
The clock gating adopted for each group of registers is as follows:
the clock gating unit of the AND gate structure is inserted into the clock input end of the 8 groups of register groups, whether the system clock signal is transmitted into the corresponding register group is controlled by controlling the switching state of the clock gating unit, and when a certain register group is not required to be used, the system clock signal is prevented from being transmitted into the register group, so that the power consumption of the register file is reduced.
The additional state control register is specifically as follows:
adding a group of 8-bit wide state control registers for dynamically controlling the power supply state of 8 voltage domains where the 8 groups of registers are located, wherein the output of the registers is respectively connected to a power gating switch and a clock gating unit of the 8 groups of registers, changing the value stored in the registers, and further changing the switch state of the power gating switch, so that the power supply state of the register group in the voltage domains is changed; meanwhile, the state control register changes the switch state of the clock gating unit, so that the transmission of a system clock signal is controlled.
The values stored by the configuration state control register are specifically: by the CSR series of instructions in the RISCV instruction set: CSRRWI, CSRRSI, CSRRCI change the value stored in the status control register.
The processor runs program segments with different computation densities by using different register group power supply configurations as follows: segmenting a program executed by a processor by a function, wherein in the function, if 4 registers in a register group are not used by the function, a state control register bit corresponding to the register group is set to be 0 even if the register group works in a low-voltage power supply state; if a register in a register group is used, setting the bit of a state control register corresponding to the register group to be 1 even if the register group works in a normal voltage power supply state, thereby determining the value to be set by the 8-bit state control register, namely the power supply configuration corresponding to the 8 register groups when a function is operated, then respectively inserting a CSR instruction at the head and the tail of the function, wherein the CSR instruction at the beginning of the function is used for configuring the power supply configuration of the register group required by executing the function, and the CSR instruction at the end of the function is used for recovering the power supply configuration of the register group required by the function calling the function.
The invention has the advantages that the method for controlling the register file of the processor with low power consumption groups the registers in the register file, and can dynamically adjust the power supply state of each register group in a software and hardware combined mode according to the requirements of each program segment on the registers, thereby reducing the power consumption of the register file of the processor.
Drawings
FIG. 1 is a block diagram illustrating the architectural partitioning of a processor register file according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a decode module in a processor register file according to an embodiment of the present invention;
FIG. 3 is a power control and clock control block diagram of a low power processor register file control method in an embodiment of the invention;
FIG. 4 is a flowchart of a method for controlling a register file of a processor with low power consumption according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention discloses a low-power-consumption processor register file control method, which comprises the following steps of: the method comprises the steps of grouping register files in a processor with a reduced instruction set, adopting a dynamic voltage regulation technology and a clock gating technology for each group of registers, adding a state control register to control the power supply state of the register group and the switch state of a clock gating unit, and configuring the value stored in the state control register through control and state register instructions to enable the processor to operate program segments with different calculation intensity degrees by different power supply configurations of the register group.
The reduced instruction set in the reduced instruction set processor comprises MIPS or RISCV, the reduced instruction set processor is provided with 32 integer registers with 32 bit width, the number is 0-31, and if the reduced instruction set processor supports the expansion of a single-precision floating point instruction set or a double-precision floating point instruction set, the reduced instruction set processor is provided with 32 single-precision floating point registers with 32 bit width or 32 double-precision floating point registers with 64 bit width.
The integer register, the single-precision floating point number register and the double-precision floating point register are similar in function, and the 32 registers can respectively store a constant 0, a frame pointer, a stack pointer and a global pointer, store a function parameter, a return value and a return address, store a temporary variable and store a variable.
The number of registers for storing function parameters is more than 4, the number of registers for storing temporary variables is more than 7, and the number of registers for storing and saving variables is more than 8.
The specific steps of grouping the register files are as follows:
dividing 32 integer registers, 32 single-precision floating-point registers and 32 double-precision floating-point registers into 8 groups according to the serial numbers of the registers in sequence respectively: 0-3, 4-7, 8-11, …, each group containing 4 registers, 32 bits for each integer register and single precision floating point register, and 64 bits for each double precision floating point register.
The method comprises the following specific steps of adopting dynamic voltage regulation for each group of registers:
the circuits of 8 groups of registers are respectively placed in 8 independent voltage domains, each voltage domain is provided with two groups of power supply voltages of normal voltage and low voltage, the corresponding register group works in the normal voltage power supply state or the low voltage power supply state by controlling the switching states of two groups of power supply gate control switches, and when a certain register group does not need to be used, the register group works in the low voltage power supply state, so that the power consumption of the register stack is reduced.
The clock gating adopted for each group of registers is as follows:
the clock gating unit of the AND gate structure is inserted into the clock input end of the 8 groups of register groups, whether the system clock signal is transmitted into the corresponding register group is controlled by controlling the switching state of the clock gating unit, and when a certain register group is not required to be used, the system clock signal is prevented from being transmitted into the register group, so that the power consumption of the register file is reduced.
The additional state control register is specifically as follows:
adding a group of 8-bit wide state control registers for dynamically controlling the power supply state of 8 voltage domains where the 8 groups of registers are located, wherein the output of the registers is respectively connected to a power gating switch and a clock gating unit of the 8 groups of registers, changing the value stored in the registers, and further changing the switch state of the power gating switch, so that the power supply state of the register group in the voltage domains is changed; meanwhile, the state control register changes the switch state of the clock gating unit, so that the transmission of a system clock signal is controlled.
The values stored by the configuration state control register are specifically: by the CSR series of instructions in the RISCV instruction set: CSRRWI, CSRRSI, CSRRCI change the value stored in the status control register.
The processor runs program segments with different computation densities by using different register group power supply configurations as follows: segmenting a program executed by a processor by a function, wherein in the function, if 4 registers in a register group are not used by the function, a state control register bit corresponding to the register group is set to be 0 even if the register group works in a low-voltage power supply state; if a register in a register group is used, setting the bit of a state control register corresponding to the register group to be 1 even if the register group works in a normal voltage power supply state, thereby determining the value to be set by the 8-bit state control register, namely the power supply configuration corresponding to the 8 register groups when a function is operated, then respectively inserting a CSR instruction at the head and the tail of the function, wherein the CSR instruction at the beginning of the function is used for configuring the power supply configuration of the register group required by executing the function, and the CSR instruction at the end of the function is used for recovering the power supply configuration of the register group required by the function calling the function.
Examples
FIG. 1 is a block diagram of the architectural partitioning of a processor register file according to the present invention. The invention takes an integer register file with one write port, two read ports and 32-bit wide registers as an example, the 32 registers are divided into 8 groups (RF0-RF7), the internal structure of each register group is a register array and comprises 4 32-bit wide registers, all the register groups share 1-bit wide write enable (WrEn) and 32-bit wide write data (WrData) signals, and 5-bit wide write address signals (WrAddr) and 5-bit wide read address signals (RdAddr and RdAddr) are used for each register group after being decoded. The output of the register set is two sets of 32-bit wide read data (RdDataA and RdDataB). The structure of the decoding circuit in the writing address decoding module is the same as that of the decoding circuit in the reading address decoding module.
FIG. 2 is a circuit diagram of a decode module in the processor register file of the present invention. The input signal of the decoding circuit is an address signal with five bit width, the upper 3 bits of the address signal are used for decoding an 8-bit group selection signal (RFEn), and the lower 2 bits of the address signal are used for decoding a register selection signal (REn) in a 4-bit group. The bank select signals are used to select a register bank to be accessed, the intra-bank register select signals are used to access 32-bit wide registers within the bank, and the 8-bit bank select signals and the 4-bit intra-bank register select signals are combined to access 32-bit wide registers within the register file.
FIG. 3 is a power control and clock control block diagram of the low power processor register file control method of the present invention. The dynamic voltage regulation technology is adopted for each group of grouped register circuits, namely, the circuits of 8 groups of registers are respectively placed in 8 independent voltage domains, each voltage domain is provided with two groups of power supply voltages of normal Voltage (VDDH) and low Voltage (VDDL), the voltage value of the normal voltage is greater than the low voltage, the corresponding register group works in a normal voltage power supply state or a low voltage power supply state by controlling the switch states of two groups of power gate control switches (SH and SL), and the number of the power gate control switches of each group is determined by the voltage drop of the corresponding register group circuit. In order to dynamically control the power supply states of 8 voltage domains, a State Control Register (SCR) with 8 bit width needs to be added, and a value stored in the state control register can be changed through an instruction, such as a CSR instruction in a RISCV instruction set. Taking a P-type transistor switch as an example, if a certain register group is occupied by a function, the value stored in the corresponding state control register can be set to be 1, at the moment, the switch SH is switched on, the switch SL is switched off, and the register group circuit is powered by VDDH and is in a normal voltage power supply state; if a certain register group is not occupied by the function, the value stored in the corresponding state control register can be set to be 0, at the moment, the switch SH is turned off, the switch SL is turned on, and the register group circuit is powered by VDDL and is in a low-voltage power supply state.
In order to further reduce power consumption, a clock gating unit (CG) of an AND gate structure is inserted at the clock input end of each group of register groups, the input of the CG is a system clock Signal (SCLK) and the output of the SCR, and the output of the CG is connected to the clock end of the register groups. If the value of a certain SCR is 1, the clock of the clock system is transmitted to the clock end of the corresponding register group through the CG, namely the CG is in an on state; if the value of a certain bit of SCR is 0, the corresponding CG output is 0, and the system clock cannot be transmitted to the clock end of the corresponding register group, i.e. the CG is in an off state.
In addition, the read data output of the 8 register groups is subjected to OR operation to generate final read data output.
FIG. 4 is a control step of the low power consumption register file control method of the present invention. Programs written in high level languages, such as C, are often subjected to compilation, assembly, and linking steps to produce files that can be executed on a processor. In the invention, in order to control the processor to operate different program segments by using different register groups for power supply configuration and realize the purpose of reducing the power consumption of the register file of the processor, analysis and modification steps need to be inserted in the compiling and assembling processes. And the analysis step is to obtain the register use conditions of the main function and each sub function by an assembly file generated after the program is compiled. And the modification step is to modify the assembly file, a CSR instruction is respectively inserted at the head and the tail of each function, the CSR instruction at the beginning of the function is used for configuring the register group power supply configuration required by executing the function, and the CSR instruction at the end of the function is used for recovering the register group power supply configuration required by calling the function of the function.
Claims (10)
1. A low power consumption processor register file control method is characterized by comprising the following steps:
the method comprises the steps of grouping register files in a processor with a reduced instruction set, adopting a dynamic voltage regulation technology and a clock gating technology for each group of registers, adding a state control register to control the power supply state of the register group and the switch state of a clock gating unit, and configuring the value stored in the state control register through control and state register instructions to enable the processor to operate program segments with different calculation intensity degrees by different power supply configurations of the register group.
2. The method of claim 1, wherein the reduced instruction set of the reduced instruction set processor includes MIPS or RISCV, the reduced instruction set processor has 32 integer registers 32 bits wide, numbered 0-31, and if the reduced instruction set processor supports extension of a single-precision floating-point instruction set or a double-precision floating-point instruction set, the reduced instruction set processor has 32 single-precision floating-point registers 32 bits wide or 32 double-precision floating-point registers 64 bits wide.
3. The method of claim 2, wherein the integer register, single-precision floating-point register, and double-precision floating-point register are functionally similar, and the 32 registers are capable of storing a constant 0, a storage frame pointer, a stack pointer, and a global pointer, a storage function parameter, a return value, and a return address, a temporary variable, and a save variable, respectively.
4. A method as claimed in claim 3, wherein the number of registers for storing function parameters is 4 or more, the number of registers for storing temporary variables is 7 or more, and the number of registers for storing variables is 8 or more.
5. The method of claim 4, wherein the step of grouping the register files comprises:
dividing 32 integer registers, 32 single-precision floating-point registers and 32 double-precision floating-point registers into 8 groups according to the serial numbers of the registers in sequence respectively: 0-3, 4-7, 8-11, …, each group containing 4 registers, 32 bits for each integer register and single precision floating point register, and 64 bits for each double precision floating point register.
6. The method of claim 5, wherein the step of dynamically adjusting the voltage of each register set comprises:
the circuits of 8 groups of registers are respectively placed in 8 independent voltage domains, each voltage domain is provided with two groups of power supply voltages of normal voltage and low voltage, the corresponding register group works in the normal voltage power supply state or the low voltage power supply state by controlling the switching states of two groups of power supply gate control switches, and when a certain register group does not need to be used, the register group works in the low voltage power supply state, so that the power consumption of the register stack is reduced.
7. The method of claim 6, wherein clock gating is used for each group of registers as follows:
the clock gating unit of the AND gate structure is inserted into the clock input end of the 8 groups of register groups, whether the system clock signal is transmitted into the corresponding register group is controlled by controlling the switching state of the clock gating unit, and when a certain register group is not required to be used, the system clock signal is prevented from being transmitted into the register group, so that the power consumption of the register file is reduced.
8. The method as claimed in claim 7, wherein the adding of the state control register is as follows:
adding a group of 8-bit wide state control registers for dynamically controlling the power supply state of 8 voltage domains where the 8 groups of registers are located, wherein the output of the registers is respectively connected to a power gating switch and a clock gating unit of the 8 groups of registers, changing the value stored in the registers, and further changing the switch state of the power gating switch, so that the power supply state of the register group in the voltage domains is changed; meanwhile, the state control register changes the switch state of the clock gating unit, so that the transmission of a system clock signal is controlled.
9. The method as claimed in claim 8, wherein the configuration state control register stores values specifically as: by the CSR series of instructions in the RISCV instruction set: CSRRWI, CSRRSI, CSRRCI change the value stored in the status control register.
10. The method as claimed in claim 9, wherein the processor runs the program segments with different computational densities in different register set power configurations as follows: segmenting a program executed by a processor by a function, wherein in the function, if 4 registers in a register group are not used by the function, a state control register bit corresponding to the register group is set to be 0 even if the register group works in a low-voltage power supply state; if a register in a register group is used, setting the bit of a state control register corresponding to the register group to be 1 even if the register group works in a normal voltage power supply state, thereby determining the value to be set by the 8-bit state control register, namely the power supply configuration corresponding to the 8 register groups when a function is operated, then respectively inserting a CSR instruction at the head and the tail of the function, wherein the CSR instruction at the beginning of the function is used for configuring the power supply configuration of the register group required by executing the function, and the CSR instruction at the end of the function is used for recovering the power supply configuration of the register group required by the function calling the function.
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Application publication date: 20191224 |