KR20050080210A - Pulse shape generator for eeprom memory cell - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse shape generator for an EPYROM memory cell, wherein the peak electric field formed in the gate oxide film is smoothed regardless of the input voltage, thereby extending the life of the gate oxide film and improving the reliability thereof. A constant voltage current providing unit connected to an input voltage terminal to provide a reference voltage and a constant current, a time delay unit connected to the input voltage terminal to prevent the output voltage from rising after a predetermined time delay, and rising beyond a predetermined voltage; A first differential amplifier connected to the constant voltage current providing unit, an input voltage terminal, and the time delay unit to control an output voltage of the time delay unit not to be a predetermined voltage or more, and an output voltage of the time delay unit as an input voltage A second differential amplifier for outputting a voltage delayed by a predetermined time A drain is connected to an external driving voltage terminal providing an erase and program voltage of a ROM memory cell, a gate is connected to an output terminal of the second differential amplifier, and a source is connected to an internal driving voltage terminal. And a voltage sensing unit connected in series with a source of the driving transistor and a feedback loop connected to the second differential amplifier to sense a voltage output to the internal driving voltage terminal.

Description

Pulse shape generator for EEPROM memory cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse shape generator for an EPYROM memory cell, and more particularly, to an EPYROM memory capable of extending the life of the gate oxide film and improving reliability by allowing the peak electric field formed in the gate oxide film to be gentle regardless of the input voltage. A pulse shape generator for a cell.

Referring to FIG. 1A, an erase operation is illustrated in an Epyrom memory cell, and referring to FIG. 1B, a program (or write) operation is illustrated.

As shown, the ypyrom memory cell has a source 2 'and a drain 3' (for example, an N-type source and a drain) formed on a surface of the substrate 1 '(for example, a P-type substrate). A gate oxide film 4 'is formed on the substrate 1', and a floating gate 5 ', a protective film 6' ONO, and a control gate are formed on the gate oxide film 4 '. 7 ') (control gate) is formed sequentially.

In this structure of the ypyrom memory cell, a high positive voltage is applied to the control gate 7 'with the drain 3' grounded. As a result, a Flowwe-Nordheim tunnel current (hereinafter referred to as F-N tunnel current) is generated toward the floating gate 5 '. This state where excess electrons are stored in the floating gate 5 'is defined as an erased state (logic "1"). In this state, when a low voltage is applied to the control gate 7 'in order to perform a read operation, since there are almost no electrons in the channel of the substrate 1', the current flows from the drain 3 'to the source 2'. Is not allowed to flow, and accordingly, the voltage Vt of the memory cell is recognized as high (in the erase state (logic "1"), the voltage Vt of the memory cell is high)).

In addition, during the program operation, a high voltage is applied to the drain 3 'with the control gate 7' grounded. As a result, electrons tunnel from the floating gate 5 'to the drain 3'. Thus, the state in which the electrons are few in the floating gate 5 'is defined as a program state (logic "0"). In this state, when a low voltage is applied to the control gate 7 'to perform a read operation, electrons flow in the channel of the substrate 1', so that a current flows from the drain 3 'to the source 2'. The voltage Vt of the memory cell is recognized as a low state according to the flowable state. In the program state logic 0, the voltage Vt of the memory cell is low.

On the other hand, in order to apply a high voltage to the control gate 7 'or the drain 3' as described above, a pulse shape generator for an ipyrom memory cell as shown in Fig. 2 is used.

As shown, a conventional generator basically consists of an RC delay circuit that controls the gate of transistor T1 to generate an internal Vppi signal from an external Vpp signal. Is high, T3 and T4 are turned on. Node 3 is then grounded, and node 1 is set to Vppi = Vcc (T1 is turned off). Is low, T3 and T4 are turned off. Node 1 then begins to rise to high voltage. The rate of raising node 1 to high voltage is determined by the RC delay signal introduced by transistors T5 and T6, which controls the gate of T1 (by T2) through the feedback loop. The shape of the internal Vppi signal is then determined by the RC delay caused by T5 and T6. In a similar way For the Vpp pulse, which is low, Vppi pulse shape control is made.

However, such a conventional pulse shape generator for EPYROM memory cells has a rise time of Vppi. It is changed by the frequency of the oscillator (oscillator) input to. On the other hand, such an input frequency is changed according to the input voltage (Vcc) to implement a constant Vppi rise time.

As a result, the peak electric field formed in the gate oxide film is severely changed, and therefore, such a stress causes a problem that the lifetime of the gate oxide film is reduced and the reliability is lowered.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-described problems, and an object of the present invention is to allow the peak electric field formed in the gate oxide film to be gentle regardless of the input voltage, thereby extending the life of the gate oxide film and improving reliability. A pulse shape generator for a pyrom memory cell is provided.

In order to achieve the above object, a pulse shape generator for an EPYROM memory cell according to the present invention is connected to an input voltage terminal for inputting a range of voltages and provides a constant voltage current providing unit for providing a reference voltage and a constant current, and A time delay unit connected to the constant voltage current providing unit, the input voltage terminal, and the time delay unit to prevent the output voltage from rising above a predetermined voltage after rising by a predetermined time delay. A first differential amplifier for controlling the output voltage not to exceed a predetermined voltage, a second differential amplifier for outputting a voltage delayed by a predetermined time, using the output voltage of the time delay unit as an input voltage, and erasing and programming an EPROM memory cell A drain is connected to an external driving voltage terminal providing a voltage, and a gate of the second differential amplifier A field effect transistor for driving an EPyrom memory cell connected to an output terminal of the drive circuit and a source connected to an internal driving voltage terminal, and a feedback loop connected to the source of the driving transistor in series and a feedback loop connected to the second differential amplifier. Characterized in that the voltage sensing unit for detecting the voltage output to the driving voltage terminal.

Here, the time delay unit is connected to the drain of the input voltage terminal, the gate is provided with a first field effect transistor connected to the constant voltage current providing unit, the drain is connected to the source of the first field effect transistor, the gate is A second field effect transistor is connected to an output voltage terminal of the first differential amplifier, and a time delay capacitor is connected in series to a source of the second field effect transistor, and at the same time, the second field effect transistor and a time delay capacitor are provided. The node between is connected to the first differential amplifier in a feedback loop, and the other side is connected to the input terminal of the second differential amplifier.

The output voltage difference between the output voltage of the second differential amplifier and the driving field effect transistor is buffered between the second differential amplifier and the EPI memory cell driving transistor, and the gate of the driving transistor is buffered. The controlling buffer is more connected.

In addition, the voltage sensing unit has a first and a second capacitor connected in series to a source of the field effect transistor for driving the EP-ROM memory cell, and an internal driving voltage terminal is connected to the source, and a node between the first and second capacitors. A feedback loop is connected to the second differential amplifier to sense the output voltage of the internal drive voltage terminal.

In addition, the front end of the first capacitor is connected to the drain of the first field effect transistor for discharge, the source is grounded, the front end of the second capacitor is connected to the drain of the second field effect transistor for discharge, the source is grounded, The gate of the first and second field effect transistors for discharge further includes a capacitor discharge part connected to a discharge control input terminal.

In this way, the pulse shape generator for EPIROM memory cells according to the present invention is inputted with a predetermined time delay for erasing and programming, thereby slowing down the intensity of the peak electric field applied to the gate oxide layer of EPIROM memory cells. Therefore, the stress of the gate oxide film is reduced, thereby extending its lifespan.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

Referring to Fig. 3, there is shown a circuit diagram of a pulse shape generator for an ypyrom memory cell according to the present invention.

As shown, a pulse shape generator for an EPYROM memory cell according to the present invention includes a constant voltage current providing unit 10, a time delay unit 20, a first differential amplifier 30, a second differential amplifier 40, And a buffer 50, a field effect transistor 60 for driving an EPyrom memory cell, a voltage sensing unit 70, and a discharge unit 80.

First, the constant voltage current providing unit 10 is connected to an input voltage terminal Vin to which an input terminal applies a voltage of approximately 1.8 to 5 V, and an output terminal of the first differential amplifier to provide a constant voltage of approximately 1.2 V. 30) is connected to the input terminal. Of course, the constant voltage current providing unit 10 has a built-in temperature compensation circuit, it is hardly affected by the temperature.

The time delay unit 20 is connected to the input voltage terminal Vin, the constant voltage current providing unit 10, and the first differential amplifier 30 so that the output voltage of the node A is delayed and raised for a predetermined time. Do not rise above a certain voltage. More specifically, the time delay unit 20 has a drain connected to the input voltage terminal Vin, and a gate is provided with a first field effect transistor P1 connected to the constant voltage current providing unit 10. In addition, a drain is connected to the source of the first field effect transistor P1 and a gate is also provided with a second field effect transistor P2 connected to the output voltage terminal of the first differential amplifier 30. In addition, a time delay capacitor C is connected to the source of the second field effect transistor P2 in series, and a node A between the second field effect transistor P2 and the time delay capacitor C is provided. One end is connected to the first differential amplifier 30 in a feedback loop. In addition, the node A is connected to an input terminal of the second differential amplifier 40. Of course, the delay time by the capacitor is determined by its capacity and current.

Therefore, the time delay unit 20 is first turned on by applying a constant voltage from the constant voltage current providing unit 10 to the gate of the first field effect transistor (P1), so that a constant current flows. In addition, a constant voltage is applied to the gate of the second field effect transistor P2 from the first differential amplifier 30 to be turned on, so that a constant current flows. Then, since the time delay capacitor C is first charged by the voltage from the input voltage terminal Vin, and then a predetermined output voltage is output through the node A, the output voltage is delayed for a predetermined time, that is, It has a rising time and gradually increases. On the other hand, since the output voltage of the node A is fed back to the input terminal of the first differential amplifier 30, when the output voltage is a predetermined voltage (about 1.2V or more), the first differential amplifier 30 By lowering the gate voltage of the second field effect transistor P2, the output voltage of the node A does not always increase above a certain voltage. On the other hand, the time for this output voltage is naturally controlled by a separate timing circuit not shown.

In the second differential amplifier 40, an input terminal is connected to the node A, whereby the output voltage having the delay time can be input as it is.

In addition, the buffer 50 is connected between the output terminal of the second differential amplifier 40 and the gate of the EPyrom memory cell driving transistor 60. The reason why the buffer 50 is provided is to buffer the voltage difference between the input voltage terminal Vin (1.8 to 5V) and the external driving voltage terminal Vpp (14.6V) because it is too large.

The field effect transistor 60 for driving the EPyrom memory cell is connected to an external driving voltage terminal Vpp having a drain outputting a voltage of approximately 14.6V, and a gate thereof is connected to the buffer 50. Accordingly, the driving field effect transistor 60 may supply an external driving voltage (14.6V) having a delay time or a rising time according to the output signal of the buffer 50 (ie, the second differential amplifier 40). The internal driving voltage terminal Vppi is output to the internal driving voltage terminal Vppi. On the other hand, since the external driving voltage terminal Vpp is supplied with a voltage from a charge pump, although the voltage is 14.6V, the current is in the unit of several kilowatts.

The voltage sensing unit 70 is connected in series to a source of the driving transistor 60. That is, the first and second capacitors C1 and C2 are connected in series to the source of the driving field effect transistor 60, and a feedback loop is provided to the node B between the first and second capacitors C1 and C2. It is formed and connected to the input terminal of the second differential amplifier 40. In addition, an internal driving voltage terminal Vppi is connected between the source of the driving field effect transistor 60 and the first capacitor C1 to apply an erase and program high voltage to the EPROM memory cell. have.

In addition, according to the above configuration, the high voltage from the external driving voltage terminal Vpp is applied to the internal driving voltage terminal Vppi with a delay time through the driving transistor 60. Of course, at this time, a predetermined signal is delayed and input to the gate of the driving transistor 60 by the second differential amplifier 40 (that is, the buffer 50). Meanwhile, the output voltage of the internal driving voltage terminal Vppi is sensed by the node B of the first and second capacitors C1 and C2 and input to the input terminal of the second differential amplifier 40. That is, the first and second capacitors C1 and C2 serve as voltage divider resistances. The reason why the capacitor is used instead of the resistor is that the current from the external driving voltage terminal (Vpp) is in the unit of several kilowatts. Thus, when the ordinary resistor is used, all of the current is consumed, so that the output voltage of the node B can be accurately detected. Because you can't. Subsequently, when the detected voltage is greater than the voltage input from the node A, the voltage applied to the gate of the driving transistor 60 is applied to the second differential amplifier 40 (ie, the buffer 50). By adjusting, the constant high voltage is always output to the internal driving voltage terminal Vppi.

The capacitor discharge unit 80 may include a first field effect transistor P1 'for discharging connected to the front end of the first capacitor C1 and a second field effect transistor for discharging connected to the front end of the second capacitor C2. P2 ') and a third field effect transistor (P3') for discharge connected between the node (A) and the second differential amplifier (4).

That is, the drain of the discharge first field effect transistor P1 'is connected to the front end of the first capacitor C1, and the source is grounded. In addition, the drain of the second field effect transistor P2 'for discharge is connected to the front end of the second capacitor C2 and the source is grounded. In addition, the drain of the third third field effect transistor P3 'for discharge is connected to the front end of the time delay capacitor C and the source is grounded. In addition, the gates of the first, second, and third field effect transistors P1 ', P2', and P3 'are connected to a discharge control input terminal dis.

By such a configuration, the capacitor discharge unit 80 is output in a low state (ie, in a state in which the driving transistor 60 is turned off) after a high voltage is output from the internal driving voltage terminal Vppi for a predetermined time. By applying a predetermined voltage to the gates of the first, second, and third field effect transistors P1 ', P2', and P3 'through a discharge control input terminal dis, the first and second capacitors C1 and C2 and the time The delay capacitor C is grounded. By this ground, the first and second capacitors C1 and C2 and the time delay capacitor C are completely initialized, and accurate voltage sensing and time delay effects are generated when the field effect transistor 60 for driving the next cycle is operated. You can do it.

Referring to FIG. 4, a timing chart for a pulse shape generator for an Ipyrom memory cell according to the present invention is shown. The pulse shape generating operation according to the present invention will be described with reference to FIG.

First, a voltage of approximately 1.8 to 5 V is applied to the input terminal of the constant voltage current providing unit 10 from the input voltage terminal Vin. The voltage range of 1.8V to 5V is set in this range because all the voltages are different for each application. The input voltage is converted into a constant current and a constant voltage through the constant voltage current providing unit 10 and input to the gate of the first field effect transistor P1 of the signal delay unit 20 and the input terminal of the first differential amplifier 30. . The output constant voltage of the constant voltage current providing unit 10 is approximately 1.2V. Of course, temperature compensation is also achieved by the constant voltage current providing unit 10.

In addition, the input voltage of the 1.8 ~ 5V range is also applied to the drain of the first field effect transistor (P1) of the time delay unit 20. In this case, a constant voltage is applied to the gate of the first field effect transistor P1 by the constant voltage current providing unit 10 to turn on. Therefore, the current (constant current) from the input voltage terminal Vin passes through the first field effect transistor P1. In addition, the current passing through the first field effect transistor P1 is applied to the second field effect transistor P2. At this time, the gate of the second field effect transistor P2 is controlled by the output voltage of the first differential amplifier 30.

On the other hand, the output voltage of the node A gradually increases with a constant delay time despite the turn-on of the second field effect transistor P2. That is, the output voltage of the node A is to charge the time delay capacitor (C) first. In addition, since the output voltage of the node A is transmitted to the first differential amplifier 30 through a feedback loop, a voltage greater than 1.2V input to the other input terminal is cut off. That is, the first differential amplifier 30 controls the gate of the second field effect transistor P2 so that the output voltage through the node A is not more than 1.2V.

That is, the constant voltage current providing unit 10, the first differential amplifier 30 and the signal delay unit 20 have a predetermined time delay even though the voltage from the input voltage terminal Vin varies between 1.8V and 5V depending on the application. This allows an output voltage of 1.2V with a rising time. Of course, the delay time is determined by the capacity and current of the signal delay capacitor C. In addition, the rising time is within about 0.4 ~ 0.6ms, and the voltage of 1.2V is about 2ms.

As described above, while an output voltage of approximately 1.2V having a rising time from the node A is input to the input terminal of the second differential amplifier 40, the voltage of approximately 14.6V from the external driving voltage terminal Vpp is 2 pyrom. The field effect transistor 60 for driving a memory cell is applied. Of course, at this time, a predetermined voltage is applied to the gate of the driving field effect transistor 60 by the second differential amplifier 40 and the buffer 60, so that the rising time of the predetermined time is applied to the internal driving voltage terminal Vppi. A high voltage with is applied.

In addition, the voltage applied to the internal driving voltage terminal Vppi is input to the other input terminal of the second differential amplifier 40 through the voltage sensing unit 70 and the feedback loop. Therefore, when a voltage of, for example, 14.6 V or more is applied to the internal driving voltage terminal Vppi, the second differential amplifier 40 and the buffer 50 reduce the gate voltage of the driving field effect transistor 60. By adjusting, only the correct 14.6V voltage is output to the internal drive voltage terminal Vppi, which always has a constant rising time. Of course, this output voltage is used as a high voltage for erase and programming. In addition, as described above, the erase and program high voltages also have a rising time of approximately 0.5 ms, thereby decreasing the intensity of the peak electric field applied to the gate oxide of the E. pyrom memory cell, and having a 14.6 V voltage time of approximately 2 ms. It is appropriate as an erase and program time.

In addition, the discharge unit 80 is operated after the application of the erase and program high voltage is completed. That is, after a high voltage is output for a predetermined time from the internal driving voltage terminal Vppi, the first and second terminals are discharged through the discharge control input terminal dis in a low state (that is, in a state in which the driving transistor 60 is turned off). By applying a predetermined voltage to the gates of the three field effect transistors P1 ', P2', and P3 ', the first and second capacitors C1 and C2 and the time delay capacitor C are grounded. By this ground, the first and second capacitors C1 and C2 and the time delay capacitor C are completely initialized, and accurate voltage sensing and time delay effects are generated when the field effect transistor 60 for driving the next cycle is operated. Done.

Meanwhile, referring to FIG. 5, the peak electric field on the gate oxide film according to the delay time is shown.

As shown, at the voltage Vpp having a delay time of 0.05 ms, the velocity of electrons passing through the gate oxide film is largely erased and programmed rapidly, but the peak electric field on the gate oxide film appears to be the largest. In addition, it can be seen that the peak electric field is significantly smaller at the linear delay time of 0.5 ms than at the 0.05 ms. In addition, as in the present invention, when the RC delay time is 0.5 ms, it has a more stable peak electric field than the linear delay time 0.5 ms, thereby minimizing the stress of the gate oxide film.

As described above, in the pulse shape generator for an EPYROM memory cell according to the present invention, since the internal driving voltage for erasing and programming is input with a predetermined time delay, the intensity of the peak electric field applied to the gate oxide film of the EPYROM memory cell is moderated. At the same time, it is delayed, thereby reducing the stress of the gate oxide film, thereby improving reliability and extending its lifespan.

In other words, the present invention has the effect of forming a constant Vppi irrespective of the input voltage and the size of the load EEPROM memory cell.

What has been described above is only one embodiment for implementing a pulse shape generator for an EPYROM memory cell according to the present invention, and the present invention is not limited to the above-described embodiment, as claimed in the following claims. Without departing from the gist of the invention, anyone of ordinary skill in the art to which the present invention will have the technical spirit of the present invention to the extent that various modifications can be made.

FIG. 1A is an explanatory diagram showing an erase operation in an Epyrom memory cell, and FIG. 1B is an explanatory diagram showing a program operation.

FIG. 2 is a circuit diagram illustrating a pulse shape generator for a conventional Epyrom memory cell.

FIG. 3 is a circuit diagram showing a pulse shape generator for an EPYROM memory cell according to the present invention.

FIG. 4 is a timing chart of a pulse shape generator for an EPYROM memory cell according to the present invention.

5 is a graph showing a peak electric field on the gate oxide film according to the delay time.

<Description of Symbols for Main Parts of Drawings>

10; A constant voltage current providing unit 20; Time delay

P1; A first field effect transistor P2; Second field effect transistor

C; A time delay capacitor 30; Primary differential amplifier

40; Second differential amplifier 50; buffer

60; Field Effect Transistor for EPI-ROM Memory Cell Drive

70; Voltage sensing unit C1; First capacitor

C2; Second capacitor 80; Discharge

P1 '; First field effect transistor P2 '; Second field effect transistor

P3 '; Third Field Effect Transistor

Vin; Input voltage terminal Vpp; External drive voltage terminal

Vout; Internal drive voltage terminal dis; Discharge control input terminal

Claims (6)

A constant voltage current providing unit connected to an input voltage terminal for inputting a range of voltages to provide a reference voltage and a constant current; A time delay unit connected to the input voltage terminal to prevent the output voltage from rising above a predetermined voltage after a predetermined time delay; A first differential amplifier connected to the constant voltage current providing unit, an input voltage terminal, and the time delay unit to control an output voltage of the time delay unit not to be equal to or greater than a predetermined voltage; A second differential amplifier configured to output the voltage delayed by a predetermined time, using the output voltage of the time delay unit as an input voltage; A drain is connected to an external driving voltage terminal that provides an erase and program voltage of an Epyrom memory cell, a gate is connected to an output terminal of the second differential amplifier, and a source is connected to an internal driving voltage terminal. Field effect transistor; And, And a voltage sensing unit connected to the source of the driving transistor at the same time and having a feedback loop connected to the second differential amplifier to sense a voltage output to the internal driving voltage terminal. . The method of claim 1, wherein the time delay unit has a drain connected to the input voltage terminal, a gate having a first field effect transistor connected to the constant voltage current providing unit, and a drain connected to a source of the first field effect transistor. The gate is provided with a second field effect transistor connected to an output voltage terminal of the first differential amplifier, and a time delay capacitor is connected to the source of the second field effect transistor in series and simultaneously with the second field effect transistor. And a node between the time delay capacitors having one side connected to the first differential amplifier in a feedback loop and the other side connected to an input terminal of the second differential amplifier. 2. The method of claim 1, wherein the output voltage difference between the output voltage of the second differential amplifier and the driving field effect transistor is buffered between the second differential amplifier and the EPI memory cell driving field effect transistor. A pulse shape generator for an EPROM memory cell further comprising a buffer for controlling the gate of the transistor. The first and second capacitors of claim 1, wherein the voltage sensing unit is connected to a source of the field effect transistor for driving the EPyROM memory cell, and an internal driving voltage terminal is connected to the source. And a feedback loop connected to the second differential amplifier so as to sense an output voltage of an internal driving voltage terminal at a node between the two pulse amplifiers. 5. The method of claim 4, wherein a drain of the first field effect transistor for discharge is connected to the front end of the first capacitor and a source is grounded, and a drain of the second field effect transistor for discharge is connected to the front end of the second capacitor. Is grounded, and the gate of each of the first and second field effect transistors for discharging has a capacitor discharge part connected to a discharge control input terminal. 3. The method of claim 2, wherein a drain of the third field effect transistor for discharge is connected to the front end of the time delay capacitor, a source is grounded, and a gate of the third field effect transistor for discharge is connected to a discharge control input terminal. Pulse shape generator for EPROM memory cells.