KR20050079685A - High speed counter circuit using even and odd f/f - Google Patents

Abstract

A counter circuit using an even / od flip-flop is disclosed. The counter circuit of the present invention includes a plurality of even / od flip-flops, wherein one even / od flip-flop includes a carry out signal of the front flip-flop and a max out signal of the rear flip-flop before the input clock signal. It is pre-populated with and a max input signal. Accordingly, the output bit signal of the counter circuit is determined in response to the input clock signal, thereby enabling high speed operation. And it is easy to expand the output bit signal.

Description

High speed counter circuit using even and odd F / F}

TECHNICAL FIELD The present invention relates to digital circuit technology, and more particularly to a high speed counter circuit using even / od flip-flops.

1 is a view for explaining a conventional counter circuit. Referring to this, the counter circuit 100 includes a plurality of flip-flops 101-108, logic circuits 112-118, and a stop signal recognition circuit 110. The first to eighth flip-flops 101 to 108 are sequentially operated in response to the input clock signal clk.

The output cnt_out [0] of the first flip-flop 101 switches from the initial logic low level to the logic high level by the transition from the logic low level to the logic high level of the input clock signal clk, and the second flip. The output cnt_out [1] of the flop 102 is determined by the output of the first logic circuit 112 when the next input clock signal clk transitions from a logic low level to a logic high level. In this way, the outputs cnt_out [2: 8] of each of the third to eighth flip-flops 103, 104, 105, 106, 107, 108 also respond to the second to flip-flop outputs of the previous stage. The seventh logic circuits 113, 114, 115, 116, 117, 118 are determined by the output.

The output signals cnt_out [0: 7] of the first to eighth flip-flops 101-108 are provided to the stop signal recognition circuit 110, which output signals of the flip-flops 101-108. If both (cnt_out [0: 7]) are high level, a stop signal STOP is generated. The stop signal STOP stops the operation of the counter circuit 100 by controlling the clock signal ck of the flip-flops 101-108.

In this counter circuit 100, the output cnt_out [8] of the last flip-flop 108 is determined after all the operations of the first to seventh flip-flops 101 to 107 are completed. For this reason, the counter circuit 100 has a limitation that high speed operation, for example, the input clock signal clk cannot follow the operation speed in the high frequency operation of about 160 MHz. Accordingly, in order to match the operation speed of the counter circuit 100, a problem that a process having a short gate delay time must be introduced in a semiconductor manufacturing process is additionally required.

Therefore, the sequential operation requires the presence of a high speed counter circuit having a short operation time instead of a counter circuit with a long operation time.

It is an object of the present invention to provide a counter circuit using even / od flip-flops.

In order to achieve the above object, the counter circuit of the present invention includes a logic unit for outputting a max signal by inputting a sync signal for notifying the start of the count and the max out signal for notifying the count stop of the first even flip-flop; A first even flip-flop enabled for the max signal and responsive to the carry input signal and clocked to the clock input signal to generate a first output bit signal; The carry out signal of the first even flip-flop is provided as the carry input signal and the max out signal is provided as the max input signal of the first even flip-flop, is enabled for the max signal, responsive to the carry input signal, and clocked to the clock input signal. And a first odd flip-flop to generate a second output bit.

Preferably, the counter circuitry is provided with a carry out signal of the first odd flip-flop as a carry input signal and a max out signal as a max input signal of the first odd flip-flop, enabled for the max signal and in response to the carry input signal. A second even flip-flop responsive and clocked to the clock input signal to generate a third output bit; And a carry out signal of the second even flip-flop is provided as a carry input signal and a max out signal is provided as the max input signal of the second even flip-flop, enabled in the max signal, in response to the carry input signal, and in response to the clock input signal. And a second odd flip-flop that is clocked to generate a fourth output bit.

Therefore, according to the counter circuit of the present invention, the configuration of the circuit can be minimized to enable high-speed operation and the output bit signal can be easily expanded.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a diagram illustrating a counter circuit according to an embodiment of the present invention. Referring to this, the counter circuit 200 performs a four-bit count operation, which is illustrative, and it is apparent to those skilled in the art that various bit count operations may be performed in addition to four bits.

The counter circuit 200 includes a NAND gate 202, an inverter 204, first and second even flip-flops 210 and 212, and first and fourth odd counters 211 and 213. The NAND gate 202 inputs a sync signal SYNC indicating the start of counting and a max out signal mxout of the first even flip-flop 210, and the inverter 204 inputs an output of the NAND gate 202. Generate the max signal max. Each of the first and second even / od counters 210, 211, 212, and 213 is specifically configured as the circuit diagram of FIGS. 3 and 4. The max out signal mxout is a signal for notifying the count stop, and the max signal max is an enable signal of the first and second even / od flip-flops 210, 211, 212, and 213.

Referring to FIG. 3, the first even flip-flop 210 typically includes a clock generator 300 that receives an input clock signal clk and generates first and second clock signals ckb and ck. A control signal generator 310 for receiving the max signal max and the carry input signal cin, which is an enable signal, and generating the first and second control signals cntl and cntlb, a set signal, and a first and first signals. 2 a control signal and an output signal generator 320 generating an output signal q in response to the first and second clock signals, a carry input signal cin, and a carry out signal in response to the output signal q. and a carry out signal generator 330 for generating cout, and a max out signal generator 340 for generating a max out signal mxout.

In the clock generator 300, the input clock signal clk is generated as the first clock signal ckb through the first inverter 301, and the first clock signal ckb is generated through the second inverter 302. It is generated by two clock signals ck.

The control signal generator 310 inputs the third inverter 312 for inputting the max signal max, the carry input signal cin, and the output of the inverter 312 to output the first control signal cntl. 314, and a fourth inverter 316 for inputting the first control signal cntl to generate a second control signal cntlb.

The output signal generator 320 may include a NOR gate 321 for inputting an output signal q and a set signal set, and a first NOR gate 321 in response to the first and second clock signals ckb and ck. A first transmission gate 322 for delivering an output to the sixth inverter 329, a second transmission gate 323 for delivering an output signal q in response to the first and second clock signals ckb and ck, A third transfer gate 324 that delivers the output of the first NOR gate 321 in response to the first and second clock signals ckb and ck, and a third in response to the first and second clock signals ckb and ck. A fourth transmission gate 325 which transmits a signal transmitted through the second or third transmission gates 323 and 324, a set signal set and a signal which is transmitted through the fourth transmission gate 325. A fifth inverter 327 which transfers the output of the second NOR gate 326 to the input of the second NOR gate 326 in response to the two NOR gates 326 and the first and second clock signals ckb and ck; First and second clock A fifth transmission gate 328 which transfers the output of the second NOR gate 326 in response to the calls ckb and ck, and a sixth input which outputs the fifth transmission gate 328 as an output signal q An inverter 329.

The carry-out signal generator 330 includes a first PMOS transistor 331 and a first PMOS transistor 331 having a source connected to a power supply voltage Vdd and a gate connected to an output of the first NOR gate 321. A second PMOS transistor 332 and a carry output signal cout connected to a source thereof, a carry input signal cin connected to the gate thereof, and a carry output signal cout connected to the drain thereof. A first NMOS transistor 333 having a drain connected and a carry input signal cin connected to the gate thereof, a drain connected to a drain of the first NMOS transistor, a gate connected to the output signal q, and grounded. A second NMOS transistor 334 having a source connected to the voltage gnd, and a source connected to the power supply voltage vvd, a drain thereof connected to a carry output signal cout, and a source connected to the output signal q. Third PMOS transistor 335 connected with a gate It includes.

The max out signal generator 340 has a fourth PMOS transistor 341 and a fourth PMOS transistor 341 having a source connected to a power supply voltage Vdd and a gate connected to an output of the first NOR gate 321. The fifth PMOS transistor 342, the max output signal mxout, whose source is connected to its drain, its max input signal maxin is connected to its gate, and its max output signal mxout is connected to its drain. A third NMOS transistor 343 in which a drain is connected and a max input signal maxin is connected to the gate thereof, a drain thereof is connected to the drain of the third NMOS transistor, and a gate thereof is connected to the output signal q, and grounded. A fourth NMOS transistor 344 whose source is connected to a voltage gnd, a source thereof is connected to a ground voltage gnd, a drain thereof is connected to a max out signal mxout, and a first NOR gate 321. Fifth Enmo with its gate connected to the output Switch transistor 345.

The first even flip-flop 210 of FIG. 4 has a control signal generator 410, a carry out signal generator 430, and a max out signal generator 440 compared to the even flip-flop 210 of FIG. 3. There is a difference in the configuration of the clock signal generator 300 and the output signal generator 320 is the same configuration. In order to avoid duplication of description, descriptions of the same components are omitted.

The control signal generator 410 inputs the output of the Noah gate 411 and the Noah gate 411 that input the max signal max and the carry input signal cin to output the first control signal cntl, and the second signal. An inverter 412 outputs a control signal cntlb.

The carry out signal generator 430 includes the PMOS transistors 331 and 332 and the NMOS transistors 333 and 334 described in the carry out signal generator 330 of FIG. 3, and additionally carries a carry out signal. and an NMOS transistor 431 coupled between cout and the ground voltage gnd and gated to the output of the NOR gate 321.

The max out signal generator 440 includes the PMOS transistors 341 and 342 and the NMOS transistors 343 and 344 described in the max out signal generator 340 of FIG. vdd) and a max out signal mxout and a PMOS transistor 441 gated to the output signal q.

2, the counter circuit 200 has a set signal in common with the set signal set of the first and second even / od counters 210, 211, 212, and 213. The output of the inverter 204 is commonly connected to the max signal max of the first and second even / od counters 210, 211, 212, 213, and the input clock signal clk is connected to the first and second even Are commonly connected to the input clock signal clk of the / od counters 210, 211, 212, 213.

The carry input signal cin of the first even flip-flop 210 is connected to the power supply voltage vvd, and the carry input signal cin of the first odd flip-flop 211 is connected to the power supply voltage vvd. The carry output signal cout of the second even flip-flop 212 is connected to the carry output signal cout of the first odd flip-flop 211, and the second odd flip-flop. The carry input signal cin of 213 is connected to the carry output signal cout of the second even flip-flop 212.

The max input signal maxin of the first even flip-flop 210 is connected to the max out signal mxout of the first odd flip-flop 211, and the max input signal maxin of the first odd flip-flop 211. Is connected to the max out signal mxout of the second even flip-flop 212, and the max input signal maxin of the second even flip-flop 212 is the max out signal mxout of the second odd flip-flop 213. The max input signal maxin of the second odd flip-flop 213 is connected to the power supply voltage vvd.

The output signals q of the first and second even / od flip-flops 210, 211, 212, and 213 constitute an output bit signal cnt_out [3: 0] of the counter circuit 200.

The operation of this counter circuit 200 is illustrated by the timing diagram of FIG. Referring to FIG. 5, in response to the logic low level pulse of the synchronization signal sync and the clocking of the input clock signal clk in the inactive state of the set signal set to the logic low level, the output bit signal cnt_out [ 3: 0]) is counted from 0000 (hexa 0) to 1111 (hexa f). The final output bit signal cnt_out [3: 0] is maintained until the sync signal sync is applied to the logic low level.

Here, the even / od counters 210, 211, 212, and 213 have a carry out signal cout, which is the output of the front counter, and a max out signal mxout, which is the output of the rear counter, before the input clock signal clk. Since the carry output signal cin and the max input signal maxin are previously input, the output bit signal cnt_out [3: 0] is determined in response to the input clock signal clk. Accordingly, the counter circuit 200 can operate at high speed.

An example in which the 4-bit counter circuit of the present embodiment is extended and configured as an 8-bit counter circuit is shown in FIG. In the counter circuit 600 of FIG. 6, the first to fourth even / od counters 610-617 are connected in the same manner as that of the counter circuit 200 of FIG. 2. As shown in FIG. 7, the operation of the counter circuit 600 is clocked to the input clock signal clk so that the output bit signal cnt_out [7: 0] is sequentially changed from 00000000 (hexa 00) to 11111111 (hexa ff). Is counted up.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the counter circuit of the present invention described above, the configuration of the circuit is minimized to enable high speed operation and to easily expand the output bit signal.

1 is a view for explaining a conventional counter circuit.

2 is a diagram for explaining a 4-bit counter circuit according to the first embodiment of the present invention.

3 is a diagram illustrating a specific circuit diagram of the first even flip-flop of FIG. 2 according to an example of the present invention.

4 is a diagram illustrating a specific circuit diagram of the first even flip-flop of FIG. 2 according to another example of the present disclosure.

FIG. 5 is a diagram illustrating an operation timing of the 4-bit counter circuit of FIG. 2.

6 is a view for explaining an 8-bit counter circuit according to the second embodiment of the present invention.

FIG. 7 is a diagram illustrating an operation timing of the 8-bit counter circuit of FIG. 2.

Claims (10)

A logic unit configured to output a max signal by inputting a synchronization signal indicating a count start and a max out signal indicating a stop count of the first even flip-flop; The first even flip-flop enabled in the max signal and in response to a carry input signal and clocked in a clock input signal to generate a first output bit signal; A carry out signal of the first even flip-flop is provided as a carry input signal and a max out signal is provided as the max input signal of the first even flip-flop, is enabled in the max signal and responds to the carry input signal And a first odd flip-flop clocked to a clock input signal to generate a second output bit. The method of claim 1, wherein the counter circuit A carry out signal of the first odd flip-flop is provided as a carry input signal and a max out signal is provided as a max input signal of the first odd flip-flop, and is responsive to the max signal and the carry input signal and A second even flip-flop clocked at to generate a third output bit; And A carry out signal of the second even flip-flop is provided as a carry input signal and a max out signal is provided as the max input signal of the second even flip-flop, and is responsive to the max signal and the carry input signal and And a second odd flip-flop clocked at to generate a fourth output bit. The method according to claim 1, wherein the even flip-flop or the odd flip-flop A clock generator which receives the input clock signal and generates first and second clock signals; A control signal generator for receiving the max signal and the carry input signal to generate first and second control signals; An output signal generator for generating the output bit signal in response to a set signal, the first and second control signals, and the first and second clock signals; A carry out signal generator configured to generate the carry out signal in response to the carry input signal and the output bit signal; And And a max out signal generator for generating the max out signal in response to the max input signal and the output signal. The clock generator of claim 3, wherein the clock generator A first inverter configured to input the input clock signal to generate the first clock signal; And And a second inverter for inputting the first clock signal to generate the second clock signal. The method of claim 3, wherein the control signal generator A third inverter for inputting the max signal; A NAND gate configured to input the carry input signal and the third inverter output to output the first control signal; And And a fourth inverter configured to input the first control signal to generate the second control signal. The method of claim 3, wherein the control signal generator A noah gate for inputting the max signal and the carry input signal to output the first control signal; And And an inverter configured to input an output of the NOR gate to output the second control signal. The method of claim 3, wherein the carry-out signal generating unit A first NOR gate for inputting the output bit signal and the set signal; A first PMOS transistor having a source connected to a power supply voltage and a gate connected to the first NOR gate output; A second PMOS transistor having a source connected to a drain of the first PMOS transistor, a carry input signal connected to a gate thereof, and a carry output signal connected to a drain thereof; A first NMOS transistor having a drain connected to the carry output signal and a carry input signal connected to the gate thereof; A second NMOS transistor having a drain connected to a drain of the first NMOS transistor, a gate connected to the output bit signal, and a source connected to a ground voltage; And And a third PMOS transistor connected at a source thereof to the power supply voltage, at a drain thereof to the carry output signal, and at a gate thereof to the output bit signal. The method of claim 3, wherein the carry-out signal generating unit A NOR gate for inputting the output bit signal and the set signal; A first PMOS transistor having a source connected to a power supply voltage and a gate connected to the NOR gate output; A second PMOS transistor having a source connected to a drain of the first PMOS transistor, a carry input signal connected to a gate thereof, and a carry output signal connected to a drain thereof; A first NMOS transistor having a drain connected to the carry output signal and a carry input signal connected to the gate thereof; A second NMOS transistor having a drain connected to a drain of the first NMOS transistor, a gate connected to the output bit signal, and a source connected to a ground voltage; And And a third NMOS transistor having a source connected to the ground voltage, a drain connected to the carry output signal, and a gate connected to the NOR gate output. The method of claim 3, wherein the max out signal generating unit A NOR gate for inputting the output bit signal and the set signal; A first PMOS transistor having a source connected to the power supply voltage and a gate connected to the NOR gate output; A second PMOS transistor having a source connected to a drain of the first PMOS transistor, a max input signal connected to a gate thereof, and a max output signal connected to a drain thereof; A first NMOS transistor connected at a drain thereof to the max output signal and at a gate thereof to the max input signal; A second NMOS transistor having a drain connected to a drain of the first NMOS transistor, a gate connected to the output bit signal, and a source connected to a ground voltage; And And a third NMOS transistor having a source connected to the ground voltage, a drain connected to the max out signal, and a gate connected to the NOR gate output. The method of claim 3, wherein the max out signal generating unit A NOR gate for inputting the output bit signal and the set signal; A first PMOS transistor having a source connected to the power supply voltage and a gate connected to the NOR gate output; A second PMOS transistor having a source connected to a drain of the first PMOS transistor, a max input signal connected to a gate thereof, and a max output signal connected to a drain thereof; A first NMOS transistor connected at a drain thereof to the max output signal and at a gate thereof to the max input signal; A second NMOS transistor having a drain connected to a drain of the first NMOS transistor, a gate connected to the output bit signal, and a source connected to a ground voltage; And And a third PMOS transistor connected at a source thereof to the power supply voltage, at a drain thereof to the max out signal, and at a gate thereof to the output bit signal.