KR20050079533A - Flash memory apparatus - Google Patents

Abstract

The present invention relates to a flash memory device, and the present invention applies a drain select signal and a source select signal applied to a selected cell block and an unselected cell block to different values so that an unselected source select transistor is not fully operated. There is provided a flash memory device capable of preventing generation of leakage current due to an unexpected bias rise due to floating, and a delay of a read operation speed due to an increase in capacitance of a common source line.

Description

Flash memory apparatus

The present invention relates to a flash memory device, and more particularly, to a flash memory device capable of controlling a source selection transistor, which is an output of each block decoder switch, block by block according to an external decoding signal.

The flash memory device applies 4.5 V to the drain select line, 4.5 V to the pass word line, and 0 V to the selected word line at the time of reading, and senses according to the state of the cell hanging on the selected word line. The data will be different. At this time, a large number of unselected blocks apply a voltage of 0V to the drain select line, and the source select line is floated, thereby raising a bias on the source select line. For the source line, this can affect large capacitors, lead speed and leakage.

Accordingly, the present invention provides a flash memory device that can improve the performance of the flash device by separating the input value of the source select line through a separate block decoder switch to solve the above problems.

A plurality of cell strings in which a plurality of cells according to the present invention are connected in series, a plurality of word lines and bit lines for selecting cells in the cell string, and are connected between a drain terminal of the cell string and the bit line to drain A plurality of cell blocks and selected words of the selected cell block including a drain select transistor for driving in accordance with a selection signal, a source selection transistor connected between a source terminal of the cell string and a common source line for driving in accordance with a source selection signal 0V is applied to the line, 4.5V is applied to the pass word line, 4.5V is applied to the drain select signal, 4.5V is applied to the source select signal, and a voltage of 0V is applied to the common source line. Floating the word line of the unselected cell block and selecting the drain selection signal and the source selection It provides a flash memory device that includes a block decoder switch for applying the arc 0V.

The block decoder switch includes a high voltage transmitter for transmitting an external high voltage, a selection signal output unit for outputting the drain selection signal and the source selection signal according to a decoded external signal, and the high voltage transmitter and the selection according to a control signal. It includes a control unit for controlling the signal output unit.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 is a conceptual diagram of a flash memory device according to the present invention.

2 is a circuit diagram of a cell block according to the present invention, Figure 3 is a block decoder switch circuit diagram according to the present invention.

1 to 3, a plurality of cell strings 10 having a plurality of cells connected in series, and a plurality of word lines WL and bit lines BL for selecting cells in the cell string 10. A drain select transistor 20 connected between the drain terminal of the cell string 10 and the bit line BL and driven according to the drain select signal DSL, a source terminal of the cell string 10, 0V to the selected cell line 200 and the plurality of cell blocks 200 including the source select transistors 30 connected between the common source lines CSL and driven according to the source select signal SSL. Is applied, 4.5V is applied to the pass word line Pass WL, 4.5V is applied to the drain select signal DSL, 4.5V is applied to the source select signal SSL, and the common source line CSL is applied. Applies a voltage of 0 V to the word line WL of the unselected cell block 200. And a block decoder switch 100 for applying 0V to the drain select signal DSL and the source select signal SSL.

The block decoder switch 100 may include a high voltage transmitter 110 for transmitting an external high voltage, and a selection signal output unit 120 for outputting a drain select signal DSL and a source select signal SSL according to a decoded external signal. And a controller 130 for controlling the high voltage transmitter 110 and the selection signal output unit 120 according to an external control signal.

The high voltage transmitter 110 is connected between a high voltage (VPP) input terminal and a high voltage output terminal in series to drive the first and second transistors T1 and T2 respectively according to the first and second external signals GA and GB, And third and fourth transistors T3 and T4 diode-connected to maintain a constant level of voltage at the high voltage output stage between the high voltage input stage and the high voltage output stage.

The selection signal output unit 120 outputs the external decoding signal SEGND to the drain selection signal DLS and the source selection signal SSL, respectively, according to a predetermined operation signal of the controller 130. (T5 and T6).

The controller 130 drives the power supply voltages of the seventh and eighth transistors T7 and T8 and the power supply voltages of the eighth transistor T8 and the external program precharge signal PGMPREb. A first NAND gate ND1, a ninth transistor T9 for transmitting an output of the first NAND gate ND1 to a high voltage output terminal according to an external precharge signal PRE, and a first NAND gate ND1. And a second NAND gate ND1 for outputting a state signal in response to an output and an enable signal, and a tenth transistor T10 for discharging the voltage of the high voltage output terminal according to the state signal.

The block decoder switch 100 may be configured to correspond to each of the plurality of cell blocks.

Referring to the operation of the present invention having the above configuration is as follows.

When an external read signal is applied, the high voltage BLKWL, the drain select signal DSL, and the source select signal SSL in the block decoder switch 100 are output so that any one of the plurality of cell blocks 200 is activated. do.

For example, when the cell block of 200a of FIG. 1 is selected, the block decoder switch 100 outputs a predetermined voltage and a selection signal, respectively. In this case, a 4.5 V voltage of logic high is applied to the drain select signal DSL and the source select signal SSL by an external decoding signal SEGND, and a voltage of 4.5 V is applied to the password line Pass WL. A voltage of 0V is applied to the word line Selected WL. Meanwhile, a voltage block of 0 V is applied to the drain select signal DSL and the source select signal SSL by the block decoder switch 100, and the selected word line and the pass word line WL are floated. The block that is not selected will not work.

That is, by applying the drain selection signal and the source selection signal applied to the selected cell block and the non-selected cell block with different values as described above, the unselected source selection transistors are not completely operated and are not intended to be caused by floating. It is possible to prevent the occurrence of leakage current due to unbiased bias and the delay of the read operation speed due to the increased capacitance of the common source line.

As described above, according to the present invention, the drain select signal and the source select signal applied to the selected cell block and the unselected cell block are applied at different values, so that the unselected source select transistors do not operate completely. It is possible to prevent the occurrence of the leakage current due to the unintentional bias rise and the delay of the read operation speed due to the increased capacitance of the common source line.

1 is a conceptual diagram of a flash memory device according to the present invention.

2 is a circuit diagram of a cell block according to the present invention.

3 is a block decoder switch circuit diagram according to the present invention;

<Explanation of symbols for the main parts of the drawings>

10: cell string 20: drain select transistor

30: source select transistor 100: block decoder switch

110: high voltage transmission unit 120: selection signal output unit

130: control unit 200: cell block

Claims (2)

A plurality of cell strings in which a plurality of cells are connected in series, a plurality of word lines and bit lines for selecting cells in the cell string, and a drain terminal and the bit lines of the cell strings in accordance with a drain selection signal. A plurality of cell blocks including a drain selection transistor for driving and a source selection transistor connected between a source terminal of the cell string and a common source line and driven according to a source selection signal; And 0V is applied to the selected word line of the selected cell block, 4.5V is applied to the pass word line, 4.5V is applied to the drain select signal, 4.5V is applied to the source select signal, and the common source line is applied. And a block decoder switch configured to apply a voltage of 0V, plot a word line of the unselected cell block, and apply 0V to the drain select signal and the source select signal. The apparatus of claim 1, wherein the block decoder switch comprises: a high voltage transmitter for transmitting an external high voltage; A selection signal output unit configured to output the drain selection signal and the source selection signal according to a decoded external signal; And And a controller configured to control the high voltage transmitter and the selection signal output unit according to a control signal.