KR20050076246A - Data processing system and memory arbitral method - Google Patents

Abstract

The present invention relates to a memory arbitration method for improving debugging efficiency in a data processing system having a unified memory composed of a single memory including an operation memory and a data buffer memory. In particular, the present invention protects the specific memory area by prohibiting the memory arbiter from generating a write cycle to the specific memory area when an MAU without a write right to the specific memory area in the shared memory generates. In addition, the present invention informs the MAU that caused the write cycle to the write-protected specific memory area by driving an interrupt to the host CPU when the MAU having no write permission for the specific memory area generates a write cycle to the specific memory area.

Description

Data processing system and memory arbitral method

The present invention relates to a memory arbitration method for improving debugging efficiency in a data processing system having a unified memory including an operation memory and a data buffer memory as a single memory.

Nowadays, it is common to implement a Data Processing System (ASIC) composed of a plurality of Memory Access Units (MAUs) such as a digital video processor (DSP).

In addition, a data butter memory is connected to a chip having a data processing system function, and an operation memory is connected to an external CPU.

However, recently developed data processing systems are being developed in the form of SOC (System On Chip). In other words, it integrates existing data processing system functions with external CPU and peripheral functions into one chip.

Therefore, in the past, data buffer memory was used for a data processing system chip and arithmetic memory was used for an external CPU. However, a recent SOC type data processing system chip uses a memory for a memory and a data buffer as one memory. It has a shared memory structure.

FIG. 1 is a block diagram illustrating an SOC data processing system having such a shared memory structure, and shows an example applied to a digital TV receiver.

Referring to FIG. 1, a plurality of MAUs 131 ˜ 135 are connected to the shared memory 110 through a memory arbiter 120 in parallel.

The memory arbiter 120 grants the use of the bus to only one of the MAUs 131-135 participating in the memory data bus arbitration to access the shared memory 110.

That is, any MAU of the plurality of MAUs 131 ˜ 135 may first share the shared memory 110 with the memory arbiter 120 when writing data to the shared memory 110 or reading data stored in the shared memory 110. A request is made to access 110. At this time, if there is one MAU requesting to access the shared memory 110, the memory arbiter 120 grants the MAU the right to use the memory data bus to access the memory 110. However, if at least two MAUs simultaneously request memory accesses, the access order must be determined. That is, the memory arbiter 120 checks the request from each MAU and then determines which MAU request to process first. The MAU is granted a right to use the memory data bus so that the shared memory 110 can be accessed.

In this case, the memory arbiter 120 may process a request from each MAU by prioritizing, or may process a request from a first incoming, or may mix and process two methods. have.

If the shared memory 110 is applied to a digital TV, the MAUs 131 to 135 may write and read a bit stream for audio / video decoding, read data necessary for motion compensation, and write decoded data. And the shared memory 110 for writing, reading, and the like for format conversion of data to be displayed.

To this end, the MAUs include, for example, a system decoder 131, a video decoder 132, a format converter 133, an audio decoder 134, and a host (CPU) 135.

The system decoder 131 selects a desired program among a plurality of programs included in one channel to separate a packetized audio and video bitstream. The separated video bit stream is output to the video decoder 132 through the arbiter 120 and the shared memory 110, and the separated audio bit stream is output to the audio decoder through the arbiter 120 and the shared memory 110. Output to (134).

The video decoder 132 removes overhead (various header information, start codes, etc.) from the input video bitstream. Then, the variable length decoding (VLD) of pure data information is performed, followed by an inverse quantization process, an Inverted Discrete Cosine Transform (IDCT) process, and a motion compensation process using a motion vector. Restore the pixel value. At this time, the video decoder 132 writes and reads a bit stream for video decoding, reads data necessary for motion compensation, and writes decoded data to the memory 110 through the memory arbiter 120. Access.

The format converter 133 reads the data stored in the memory 110 through the memory arbiter 120 and the memory data bus, converts the data into a display format, and then uses the memory arbiter 120 and the memory data bus. Stored in the shared memory 110.

The audio decoder 134 restores an input audio bitstream to an original signal using an MPEG algorithm or an audio coding (AC) -3 algorithm. Like the video decoder 132, the audio decoder 134 also accesses the memory 110 through the memory arbiter 120 to perform writing and reading of a bit stream for audio decoding and writing of decoded data. .

The CPU 135 controls the shared memory 130 through the memory arbiter 120 to control overall control of the digital TV system, e.g., the audio / video data separation, audio / video decoding, and format conversion described above. Access.

FIG. 2 shows an example of a map of the shared memory 110 used in such a digital TV receiver, and is allocated to a plurality of regions so that the plurality of MAUs can each access it. That is, in the region allocated to the shared memory 110, the system decoder region accessed when the system decoder 131 separates the audio bitstream and the video bitstream, the video storing the separated video bitstream, and the audio stream, respectively; It contains an audio buffer area. In addition, the video decoder 132 includes a VDEC area accessed during the video decoding process, and a VDP (Video Display Processor) area accessed by the format converter 133 during format conversion. In addition, the On Screen Display (OSD) includes an OSD area for storing OSD characters and an CPU area accessed by the CPU 135 during the On Screen Display (OSD) processing. The CPU area includes an operation memory area.

However, in the shared memory structure, there are areas to be write protected from arbitrary MAUs, such as an operation memory area used by the CPU 135.

When data is written in any MAU which does not have write permission in the memory area to be write-protected, the data-processing system equipped with the memory, for example, the digital TV receiving system, is brought down. That is, since the CPU 135 does not operate normally due to incorrect data, the CPU cannot reveal the cause of the system down. If the CPU is unable to determine the cause, a lot of trouble occurs in debugging to recover the system normally.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to prohibit any MAU who does not have write permission to write data in a memory area to be write-protected, thereby prohibiting the write of the memory area. A data processing system and a memory arbitration method are provided.

A data processing system and a memory arbitration method having a SOC type shared memory structure according to the present invention for achieving the above object, SOC type shared memory structure for storing the operation memory data and data buffer memory data in one memory In MAU, when a MAU without a write right for a specific memory area generates a write cycle in the specific memory area, the memory arbiter prohibits it and protects the specific memory area.

In addition, when an MAU without write permission for a specific memory area generates a write cycle in the specific memory area, the present invention drives an interrupt to the host CPU to notify the MAU that caused the write cycle in a write-protected specific memory area. There is a characteristic.

In addition, the present invention is characterized by writing data requested by the MAU in an area other than the specific memory area when an MAU without a write right in a specific memory area generates a write cycle in the specific memory area.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

In the present invention, as shown in FIG. 1, a shared memory 110 constituting an operation memory and a data buffer memory as a single memory, a plurality of MAUs 131 to 135 accessing the shared memory 110, and a plurality of the plurality of MAUs 131 to 135. Memory arbiter 120 that mediates access to shared memory 110 of MAUs 131-135.

In FIG. 1, MCMD (Memory Command) is information that an MAU sends to the memory arbiter 120 to access the memory 110. The information includes, for example, row / column address, read / write information, data masking, bank to select, number of banks to access, and addressing mode. MWD is a shared write data bus, and MRD is a shared read data bus.

If the shared memory 110 is applied to a digital TV, the MAUs 131 to 135 may write and read a bit stream for audio / video decoding, read data necessary for motion compensation, and write decoded data. And the shared memory 120 for writing and reading for format conversion of data to be displayed. To this end, the MAUs include, for example, a system decoder 131, a video decoder 132, a format converter 133, an audio decoder 134, and a host (CPU) 135. Since the functions of the respective MAUs have been described in detail in the related art, they are omitted in the present invention.

The shared memory 110 is allocated to a plurality of areas as shown in FIG. 2 so that each of the plurality of MAUs 131 to 135 can be accessed, and each of the MAUs 131 to 135 is assigned to an area allocated thereto. Write data or read data stored in the area. In this case, each area may be fixedly allocated or variably allocated. The start address and end address of each area are stored in the memory arbiter 120. In addition, the memory arbiter 120 stores the start address and the end address of the memory area to be write-protected.

Thus, if any MAU attempts to write data to a particular memory area that is write protected, the memory arbiter 120 stops this write cycle, and at the same time any MAU is write protected to the CPU 135. Interrupt indicates whether a write cycle occurred in the memory area. Therefore, the CPU can be prevented from being down, which can increase debugging efficiency in a data processing system having a shared memory structure.

In the present invention, the write-protected area is limited to the CPU memory area of FIG. 2 for convenience of description. Here, the write-protected area may be applied to a wider variety of applications, and thus the present invention will not be limited to the example provided above.

3 is a register that stores information of the CPU memory area. The start address cpu_start_addr and the end address cpu_end_addr of the CPU memory area are stored. This register may be included in the memory arbiter 120 or may be disposed outside the memory arbiter 120 and the memory arbiter 120 may refer to the register to confirm the start address and the end address of the CPU region. . For example, it is assumed that 12 bits are allocated to the start and end addresses, and a default value of the start address is set to 0x "0A5C" and an end address is set to 0x "0FFF". It is also assumed that the total size of the register is 4 bytes.

4 is an address of a row for storing write data requested by the MAU instead of a CPU memory area in order to protect the CPU memory area when an MAU without write permission in the CPU memory area attempts to write data to the CPU memory area (invalid_write_addr) Is a register specifying. For example, the total size of the register storing the invalidated write address (invalid_write_addr) is 4 bytes, of which 12 bits are allocated to the invalidated write address (invalid_write_addr), and the default value thereof is 0x ". 0000 ". The invalidated write address invalid_write_addr may designate one of the memory areas except the CPU memory area in the CPU. At this time, when data is written in the corresponding MAU to the invalidate write address (invalid_write_addr), the original data is lost. Therefore, the invalid write address (invalid_write_addr) should be assigned to an address of an area that does not affect the operation of the system. For example, the invalidated write address invalid_write_addr may allocate an address of an area in which a video signal is stored. This is because the video signal is easy to deceive the user's eyes.

On the other hand, when an MAU that does not have write permission in the CPU memory area attempts to write data in the CPU memory area, the memory arbiter 120 stops the memory write cycle of the MAU and simultaneously sends the CPU 135 to the CPU 135. Interrupts indicate which MAU caused a write cycle in a write-protected memory area.

5 shows an example of the register of the present invention in which the memory arbiter 120 assigns an error flag for each MAU to generate an interrupt to the CPU 135.

It is assumed that the register has a total size of 4 bytes, is a read only register, and has a read clear characteristic. The CPU 135 may determine which MAU caused a write cycle in a memory area which is write-protected by looking at each error flag.

At this time, the terms of the error flag allocated to each MAU are summarized as follows.

. err_tp is a flag indicating whether the system decoder 131 has a write cycle in the CPU memory area, and assumes a default value of '0'.

. err_vb is a flag indicating whether the video buffer has caused a write cycle in the CPU memory area. It is assumed that the default value is '0'.

. err_fc is a flag indicating whether the format conversion unit 133 has caused a write cycle in the CPU memory area, and assumes a default value of '0'.

. err_vdec is a flag indicating whether the video decoder 132 has written a write cycle in the CPU memory area. It is assumed that the default value is '0'.

. err_audio is a flag indicating whether the audio decoder 134 has caused a write cycle in the CPU memory area, and assumes a default value of '0'.

. err_osd is a flag indicating whether or not the OSD MAU has caused a write cycle in the CPU memory area. It is assumed that the default value is '0'.

. err_dma is a flag indicating whether or not the MAU for DMA has caused a write cycle in the CPU memory area. It is assumed that the default value is '0'.

. err_gfx is a flag indicating whether or not the MAU for the graphics engine (GFX) has caused a write cycle in the CPU memory area. It is assumed that the default value is '0'.

At this time, when the error flag value is changed to '1', the CPU determines that a write cycle is generated in a memory area which is write-protected in the corresponding MAU. For example, when the err_vdec flag value is changed to '1', the CPU 135 determines that the video decoder 132 has caused a write cycle in the CPU memory area.

Here, the number of error flags depends on the number of MAUs accessing the memory 110, and the MAUs may be applied to a wider variety of applications.

FIG. 6 is a flowchart illustrating an example of such a memory arbitration process. It is assumed that a CPU memory area of the shared memory 110 area is accessible only by the CPU 135 and write-protected by other MAUs. .

That is, when a plurality of MAUs request the memory arbiter 120 to use the memory arbiter 120 to read / write data in the memory 110, the memory arbiter 120 confirms a request from each MAU and then determines a arbitration method. It decides which MAU will process the request first. The specific MAU is given a right to use the memory bus to access the shared memory 110 (step 601). Here, the mediation method is not a feature of the present invention, and well-known techniques may be used and thus no detailed description will be given.

At this time, it is determined whether the MAU that has obtained the right to use the memory data bus is the CPU 135 (step 602). If the MAU obtained the bus license is the CPU 135, the memory arbiter 120 writes data requested by the CPU 135 to a row address of a memory area designated by the CPU 135, or writes data at the row address. Read it and pass it to CPU 135 (step 607).

If it is determined in step 602 that the MAU having obtained the bus right is not the CPU 135, it is determined whether the access of the corresponding MAU is a write cycle (step 603). If it is determined in step 603 that it is not a write cycle, that is, a read command, the memory arbiter 120 reads data from a row address of a memory area requested by the MAU and transfers the data to the MAU (step 608).

If it is determined in step 603 that the write cycle is performed, the row address Row_addr that the MAU requests to write is less than or equal to the CPU start address cpu_start_addr stored in the register of FIG. 3, and is greater than or equal to the CPU end address cpu_end_addr. Confirm (step 604). If the row address Row_addr is less than or equal to the CPU start address cpu_start_addr and greater than or equal to the CPU end address cpu_end_addr in step 604, the row address is not an address of the CPU memory area. Accordingly, the memory arbiter 120 writes data requested by the MAU to a row address of a memory area requested by the MAU, or reads data from the row address and transmits the data to the corresponding MAU (step 609).

Meanwhile, if the row address Row_addr is larger than the CPU start address cpu_start_addr and smaller than the CPU end address cpu_end_addr in step 604, that is, the row address Row_addr is the CPU start address cpu_start_addr and the CPU end address cpu_end_addr), the row address is the address of the CPU memory area. That is, the MAU without write permission in the CPU memory area causes a write cycle in the write-protected CPU memory area. Therefore, in this case, the error flag err_xx of the corresponding MAU of FIG. 5 is set to '1' to drive an interrupt to the CPU 135 (step 605). The CPU 135 may then know that any MAU that does not have write permission in the write-protected CPU memory area has generated write cycles. For example, if the video decoder 132 generates a write cycle in the CPU memory area, the interrupt is driven by setting the err_vdec flag of FIG. 5 to '1'.

The data requested by the corresponding MAU is written to the row address indicated by the invalidated write address register of FIG. 4 (step 606). For example, the video decoder 132 writes data of write cycles generated in the CPU memory area to the row address of the memory 110 indicated by the invaluable write address register. At this time, data of write cycles generated in the CPU memory area by the video decoder 132 are not written to the CPU memory area. Then, the read / write cycle for the memory 110 is terminated.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

In addition, since the present invention has been described through the preferred embodiment of the present invention, in view of the technical difficulty aspects of the present invention, those having ordinary skill in the art can easily and other embodiments of the present invention. Other variations can be made. Therefore, it is apparent that all of the embodiments and variations cited in the above description belong to the claims of the present invention.

As described above, according to the data processing system and the memory arbitration method according to the present invention, if a write cycle occurs in the specific memory area in an MAU that does not have write permission for a specific memory area, the memory arbiter determines that the MAU is assigned to the specific memory area. Prevents write cycle data from being written. Instead, the data requested by the MAU is written to the row address of the memory indicated by the invalidate write address register. At the same time, the error flag of the corresponding MAU is set to '1', and then the interrupt is driven by the CPU to indicate that any MAU without write permission in a specific write-protected memory area has caused a write cycle.

By doing so, it is possible to protect the write-protected specific memory area when a write cycle occurs in the MAU in which write permission is not provided in the write-protected specific memory area. As a result, it is possible to prevent the SOC data processing system from going down, thereby facilitating debugging when the data processing system is implemented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

1 is a block diagram showing an example of a data processing system of a general SOC type

FIG. 2 illustrates an example of region division in the shared memory of FIG. 1. FIG.

3 illustrates an example of a register for storing a start address and an end address of a CPU memory area in which a CPU memory area may be variably set according to the present invention.

4 illustrates an example of a register for designating a row address of a memory in which a requested data is to be written instead of the CPU memory area when an MAU without write permission to the CPU memory area attempts to write to the CPU memory area according to the present invention. drawing

FIG. 5 is a diagram illustrating an example of a register to which an error flag for each MAU is allocated that indicates whether an MAU other than the CPU has caused a write cycle to a CPU memory area according to the present invention.

6 is a flowchart showing an example of a memory arbitration method according to the present invention;

Explanation of symbols for main parts of the drawings

110: shared memory 120: memory arbiter

131 ~ 135: MAU

Claims (11)

A memory capable of reading / writing data, the memory being divided into a plurality of areas and allocated; A plurality of memory access units (MAUs) including a CPU requesting usage rights of a memory bus to write or read data to a specific area of the memory; And After granting a memory bus right to a specific MAU according to a predetermined arbitration method among the MAUs requesting the right to use the memory bus, the memory access of the MAU that has granted the memory bus right is a write cycle, and the requested memory area has a write right to the MAU. And a memory arbiter for controlling not to write data of write cycles requested by the MAU to the memory area. The method of claim 1, wherein the memory is A data processing system, characterized in that it is a shared memory consisting of a single memory consisting of the operation memory and the data buffer memory. The apparatus of claim 1, wherein the memory arbiter And an MAU having no write right in a specific area in the memory generates a write cycle in the specific area and drives an interrupt with information indicating the MAU to the CPU. The apparatus of claim 1, wherein the memory arbiter And a data request requested by the MAU in an area other than the specific area of the memory when a MAU having no write permission for the specific area in the memory generates a write cycle in the specific area. The apparatus of claim 1, wherein the memory arbiter A register that stores a start address and an end address of a specific write-protected memory area; A register that stores an address of an area other than the specific memory area to write data requested by the MAU when an MAU without a write right for the specific area in the memory generates a write cycle in the specific area; Assigning error flags corresponding to each MAU, and including a register indicating whether or not each error flag has a write cycle for a specific area in which no MAU has a write permission for the specific area. Data processing system. 6. The apparatus of claim 5, wherein the memory arbiter And an error flag value of the corresponding MAU is changed to a value notifying when an MAU that does not have a write permission for a specific area in the memory generates a write cycle in the specific area. A memory arbitration method of a data processing system including a memory allocated to a plurality of areas and a plurality of memory access units (MAUs) requesting a use of a memory bus to write or read data to the memory, (a) granting a memory bus license to a specific MAU according to a predetermined arbitration method among MAUs requesting the license of the memory bus; And (b) if the memory access of the MAU granting the memory bus use is a write cycle, and the requested memory area is a memory area to which the MAU does not have write permission, control does not write data of a write cycle requested by the MAU to the memory area. Memory arbitration method comprising the steps of. 8. The method of claim 7, wherein step (b) And an MAU which does not have a write permission for a specific area in the memory generates an interrupt with the information indicating the MAU when a write cycle occurs in the specific area. 8. The method of claim 7, wherein step (b) And writing a data requested by the MAU in an area other than the specific area of the memory when a MAU having no write permission for the specific area in the memory generates a write cycle in the specific area. 8. The method of claim 7, wherein step (b) And if the memory access of the MAU granting the memory bus use is a read cycle, reading data stored in a memory area requested by the MAU and transferring the read data to the MAU. 8. The method of claim 7, wherein step (b) If the memory access of the MAU that has granted the memory bus usage is a write cycle, and the requesting memory area is a memory area in which the MAU has write permission, writing the data of the write cycle requested by the MAU to a memory area requested by the MAU. Characterized by a memory mediation method.