KR20050076086A - Frequency offset corrector in dmb receiver - Google Patents

Abstract

The present invention relates to a frequency error correction apparatus for estimating and removing integer frequency errors that may occur when a DMB signal is received by a terrestrial DMB receiver. Particularly, the partial correlator of the integer frequency error correcting apparatus includes a shift register and a memory having N delays, and a comparator. The self-generated PRS signal is sequentially inputted to the shift register, and the received PRS signal is transferred to the memory. After input and storing, a partial correlation value between the output of each stage of the shift register and the signal stored in the memory is obtained through a comparator. The integer frequency error calculator calculates the correlation subtotal by accumulating for N + 1 partial correlation values of the partial correlator for each preset subtotal interval, and accumulates the correlation subtotal for another symbol period to obtain the total correlation sum, and then N +. If the largest value among one total correlation is greater than the maximum value stored previously, the process of updating the stored maximum value to the largest total correlation sum for one frame is repeated. Decide on

Description

Frequency error correction device in DMB receiver {Frequency offset corrector in DMB receiver}

The present invention relates to a terrestrial digital multimedia broadcasting (DMB) receiver, and more particularly, to a frequency error correction apparatus for estimating and correcting an integer frequency error that may occur when a DMB signal is received.

Digitalization of broadcasts has also affected existing analog radio broadcasts, which has led to the advent of digital radio broadcasts. In addition to existing voice radio services, digital multimedia broadcasting (DMB), which includes data transmission and multimedia services, has become possible. Digital multimedia broadcasting is robust against noise and distortion on the transmission channel, has a high transmission efficiency, and has various advantages of enabling various multimedia services.

Digital multimedia broadcasting (DMB), adopted in Korea, is based on Eureka-147 digital radio broadcasting (DAB), which has been adopted as the European terrestrial radio standard. Added to improve multimedia broadcasting performance, RS-code (Reed-Solomon Code) and convolutional interleaver, which are robust against burst errors that may occur on a transmission channel, are added. The two additional blocks are applied to the DAB Ensemble input signal at the transmitter and provide an error rate low enough for video service even in a mobile receiving environment. The transmission channel of the DMB broadcast is a wireless mobile reception channel, and the amplitude of the received signal is not only time-varied, but also the Doppler Spreading of the spectrum of the received signal occurs due to the influence of the mobile receiver. do. In consideration of the transmission and reception in such a channel environment, the DMB transmission scheme is based on Coded Orthogonal Frequency Division Multiplexing (COFDM). Since the COFDM method uses a plurality of multicarriers, the COFDM method has a strong resistance to ghosts generated by the multipath channel and easy channel estimation based on a pilot signal.

That is, in the DMB transmitter, each service signal (audio, video, data service) is individually encoded for error prevention and then interleaved in the time domain, and each service signal interleaved in the time domain is multiplexed and is a main service which is a data channel. Merged into the Channel (Main Service Channel (MSC)). The multiplexed signal is interleaved in the frequency domain together with multiplexing configuration information (MCI) and service information (Service Informaton (SI)) transmitted through a fast information channel (FIC), which is a control channel. At this time, since information transmitted to the FIC does not allow time delay, time domain interleaving is not performed. The frequency interleaved bit string is mapped to a differential quaternary phase shift keying (DQPSK) symbol, and then an OFDM symbol is generated through an inverse fast Fourier transform (IFFT). The OFDM symbol is modulated into an RF signal and transmitted.

At this time, the transmission standard defines four transmission modes of transmission modes 1,2,3,4 that vary according to the frequency band and the reception region.

That is, the number of subcarriers, the frame length, the guard interval length, the effective symbol length, and the null symbol length vary depending on the transmission mode.

In addition, a null symbol and a phase reference symbol (PRS) for pi / 4DQPSK modulation and demodulation are allocated to the synchronization channel SC. The SC is followed by the FIC, followed by the MSCs carrying the audio, data and video services. Data transmission consists of FIC and MSC, which consists of a number of fast information blocks (FIBs) and controls the MSC arrangement. At the heart of the control information is the MCI transmitted over the FIC, which is rearranged as needed.

In addition, the number of subcarriers (i.e., sub-carriers) allocated to the PRS symbol, that is, the number of samples, depends on the transmission mode, which is 1536 samples in transmission mode 1, 384 samples in transmission mode 2, 192 samples in transmission mode 3, and transmission. In mode 4, 768 samples are allocated and transmitted. That is, the number of subcarriers and the number of samples allocated to the PRS symbol are the same.

In addition, interleaving of signals in the time domain and the frequency domain may be performed to correct an error occurring in a transmission channel. DMB transmission signals are transmitted at a much smaller signal strength than conventional analog radio broadcast signals. In consideration of mobile reception such as in a car in a severe fading channel environment such as a city, the actual signal strength of a received signal is very small. .

Therefore, the DMB receiver should be able to correct the transmission error by receiving the received signal as much as possible in such a poor reception environment. In addition, considering the fact that it is a mobile terminal, providing the maximum reception performance at a limited cost is a key requirement of the DMB receiver configuration.

1 is a conceptual block diagram of a DMB receiver according to a DMB transmission scheme scheduled to be serviced in Korea, and the tuner 101 tunes only an RF signal of a specific channel among RF signals received by the antenna 100 to an intermediate frequency; After converting into a pass-band signal of the IF, it is output to the AGC (Auto gain control) unit 102. The AGC unit 102 multiplies the IF signal by a gain value calculated according to a reference signal size for A / D conversion of the IF signal to make the size of the IF signal constant, and then to the A / D converter 103. Output

The A / D converter 103 performs sampling on the gain-adjusted IF signal irrespective of the magnitude of the received signal, converts it into a digital signal, and outputs the digital signal to the I / Q divider 104. The I / Q divider 104 converts the digital signal into a complex component signal that also has a quadrature component (Q) because the input digital signal has only a real component (I). ) Is output to the signal synchronizer 106 and the OFDM demodulator 107.

The mode detector 105 detects a transmission mode of the received signal, and the OFDM demodulator 107 removes unnecessary guard intervals, and then uses a fast fourier transform (FFT) to frequency-domain the signal in the frequency domain. After the conversion to the signal is fed back to the signal synchronizer 106 and output to the frequency deinterleaving unit 108.

The signal synchronizer 106 extracts information necessary for synchronization in the time / frequency domain of the signal using the input and output signals of the OFDM demodulator 107. That is, the signal synchronizer 106 performs frame synchronization, OFDM symbol synchronization, and carrier frequency synchronization.

The frequency de-interleaving unit 108 restores the positions of the frequency interleaved sub-carrier signals to the first channel splitter 109. The first channel divider 109 separates the FIC channel as the control channel and the MSC channel as the data channel, and then outputs the signal of the separated FIC channel to the FIC decoder 110, and the signal of the MSC channel is a time deinterleaving unit. Output to (111).

Here, since the signal of the FIC channel is not time-domain interleaved at the transmitter, the receiver does not perform time-domain deinterleaving. The FIC decoder 110 receives the FIC channel signal as an input, extracts information necessary to decode the MSC channel, and outputs the information to the FIC data decoder 117. In this case, the separate control data transmitted through the FIC channel is recovered by the FIC data decoder 117.

Meanwhile, the time deinterleaving unit 111 restores 16 logical frames of the MSC channel interleaved in the time domain by the DMB transmitter in the original frame order. The time deinterleaved MSC channel signal is input to a convolutional decoder 112, and the convolutional decoder 112 corrects a random error generated in a transmission channel included in the MSC channel. If the random error corrected data is scrambled, the data is descrambled from the energy descramble 113 to the second channel distributor 114, and if not, the data is scrambled to the second channel distributor 114. Passed.

The second channel distributor 114 discriminates whether the transmitted data channel is a data / audio signal for a DAB service or a video signal for a DMB service, and then separates the separated audio / data signal into an audio / data decoder ( 118, and the separated video signal is output to the convolutional de-interleaving unit 115.

The convolutional deinterleaving unit 115 rearranges the data additionally interleaved by the transmitter in the original order, and outputs the data to the RS decoder 116. The RS decoder 116 transmits the RS-encoded data by the transmitter. After reconstruction, the output is output to the video decoder 119. The video decoder 119 reconstructs a video signal for a DMB service.

In this case, the COFDM transmission method used in the DMB uses a large number of carriers, and transmits the desired information on each carrier.

When information is loaded and transmitted in this manner, signal distortion due to multipath and inter-symbol interference is better than a single carrier method. However, in order to have these characteristics, synchronization must be precisely performed in the time domain and the frequency domain. That is, if the synchronization of the transmitted frequency and the received frequency is correctly matched, the information transmitted by the orthogonality can be correctly restored at the receiving end.

At this time, when the transmitted frequency and the received frequency have an error, it is mainly caused by two causes. Firstly, it is caused by an error occurring in a local oscillator, and secondly, a clock of the DMB receiver. This occurs when the frequency is out of phase with the clock frequency of the DMB transmitter.

The frequency error occurring at the DMB receiver is represented by the sum of integral frequency offset and fractional frequency offset. The integer frequency error is expressed as the product of integer multiples of the frequency interval. Displayed as a value less than half of the frequency interval.

In this case, when a frequency multiple frequency error occurs in the DMB receiver, an adjacent carrier interference occurs and an error occurs because orthogonality between carriers is no longer maintained.

On the other hand, if an integer multiple error occurs in the DMB receiver, the orthogonality is maintained, but other information other than the desired information is carried on the carrier so that an error occurs. Therefore, the frequency error generated in the DMB receiver should be removed.

A patent for estimating and removing the integer multiple error has been filed by the present applicant.

The present invention is an improvement of the above-described patent, and an object of the present invention is to provide a frequency error correction apparatus in a DMB receiver to reduce the complexity of the DMB receiver when estimating and removing integer frequency errors.

The frequency error correction apparatus in the DMB receiver according to the present invention for achieving the above object, the integer frequency error correction apparatus of the DMB receiver for estimating and correcting the integer frequency error from the received signal by the inverse fast Fourier transform (IFFT) A PRS generator, comprising: a PRS generator for generating a PRS signal known according to a transmission mode and outputting the PRS signal as a reference PRS signal; After having the shift registers and the memory and the comparator with N delays, the self-generated PRS signal is input to the shift register and shifted sequentially, and the received PRS signal is input to the memory and stored, and then shifted through the comparator. A partial correlator for obtaining and outputting a partial correlation value between the N + 1 outputs of each stage of the register and the signal stored in the memory; The N + 1 partial correlation values of the partial correlator are accumulated for a predetermined subtotal period, respectively, to obtain a correlation subtotal, and the correlation subsum is accumulated for another symbol period to obtain the total correlation sum, and then the N + 1 total correlation sum. If the largest value is greater than the stored maximum value, the process of updating the maximum value stored to the largest total correlation sum for one frame is repeated. After one frame, the maximum value is determined by the integer multiple frequency error. Characterized in that it comprises an error calculator.

The partial correlator operates in synchronization with a symbol mux, which selects and outputs a PRS signal that is self-generated by the PRS generator while the PRS signal is generated by the PRS generator, and selects and outputs a PRS signal that is fed back when all are generated. A first shift register configured to receive N delays, sequentially shifting the output of the mux, and outputting a signal of each stage to correlate with the received PRS signal, and N operating in synchronization with a symbol frequency. A second shift register configured to receive the output of the last delay delay of the shift register, sequentially shift the feedback, feed back to the mux, a memory to store the received PRS signal, and each of the first shift registers. The correlation value between the N + 1 PRS signals outputted from the terminal and the signals stored in the memory is obtained, respectively. And a comparator for outputting N + 1 correlation values.

The comparator selects a zero value when the self-generated PRS signal of each stage of the first shift register is 0, a received PRS signal value when 1, and an inverted received PRS value when -1, and outputs the correlation value as a correlation value. Characterized in that.

The integer frequency error calculator corresponds to N + 1 correlation values of the partial correlator, respectively, and accumulates the correlation values for a predetermined subtotal period to obtain a correlation subtotal, and accumulates the correlation subtotals for another symbol period to obtain a total correlation. After obtaining the sum, the N + 1 correlation sum calculation unit outputting N + 1 total correlation sums is compared with the magnitudes of the N + 1 total correlation sums to detect the largest value, and then the largest detected value is obtained. A size comparison unit for determining whether the value is greater than the previously stored maximum value, and if the maximum total correlation detected is greater than the previously stored maximum value, the maximum value stored is updated with the maximum total correlation detected. It characterized in that it is configured as a maximum value storage for maintaining the same.

Each of the correlation sum calculators calculates a correlation subtotal by accumulating the correlation value output from the partial correlator for a predetermined subtotal period, and takes absolute values of real and imaginary values of the correlation subtotals output from the subtotal calculator, respectively. And an absolute value processor that adds two absolute values and outputs the sum, and a total sum calculator that accumulates the output of the absolute value processor for one symbol period to obtain a total correlation sum.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

FIG. 2 is a block diagram of an integer frequency error correcting apparatus proposed by a previously filed patent. In order to accurately measure integer frequency error, a phase reference symbol (PSR) signal having a good autocorrelation relation property is shown. I use it. In this case, in transmission mode 1, 1536 samples are allocated to a PRS symbol in every frame and transmitted. Similarly, in transmission mode 2, 384 samples are allocated to a PRS symbol every frame, 192 samples are transmitted in transmission mode 3, and 768 samples are allocated in transmission mode 4.

Referring to FIG. 2, when a Fast Fourier Transform (FFT) is performed by the OFDM demodulator 107 on a signal received by a DMB receiver, a signal in a time domain is converted into a signal in a frequency domain. This signal is input to the multiplier 201 of the integer frequency error correction device. The multiplier 201 multiplies the signal in the frequency domain transformed by the OFDM demodulator 107 with a corrected integer frequency error to remove the integer frequency error included in the received signal and outputs the partial correlator 203. At this time, the PRS generator 202 generates a known PRS signal by the promise of the DMB transmitter / receiver and outputs it to the partial correlator 203 as a reference PRS signal. The partial correlator 203 calculates a partial correlation between the output of the multiplier 201 and the reference PRS signal and outputs the partial correlation to the integer frequency error calculator 204. In this case, the partial correlator 203 performs partial correlation on two input signals in order to accurately estimate the integer frequency error even when there is a symbol timing offset. That is, in the case where a symbol timing offset exists in a received symbol, taking a correlation value during one symbol period may result in a low correlation even when a frequency error does not exist in a received PRS signal and a PRS signal generated by itself. Because it is.

The integer frequency error calculator 204 estimates the integer frequency error from the partial correlation value output from the partial correlator 203 and outputs the integer frequency error corrector 205. The integer frequency error corrector 205 corrects the calculated integer frequency error and feeds it back to the multiplier 201.

In this case, the easiest way to perform partial correlation in the partial correlator 203 is to store the received PRS signals in 2048 flip-flops and obtain a correlation while circularly shifting the PRS signals with the generated PRS signals. . However, the structure of the partial correlator 203 is simple, but 2048 * 10 flip flops are needed to store the received PRS signal assuming a 10-bit received signal, which increases complexity and power consumption.

Accordingly, the present invention is to reduce the complexity of the partial correlator 203 and the integer frequency error calculator 204 described above to be suitable for mobile reception, which is one of the uses of the terrestrial DMB receiver, and to implement low power.

3 is a detailed block diagram of the partial correlator 203 of the frequency error correcting apparatus according to the present invention, and includes a mux 301, first and second shift registers 302 and 303, a memory 304, and a comparator 305. FIG. do. That is, the mux 301 selects one of a self-generated PRS signal and a PRS signal fed back from the second shift register 303 and outputs it to the first shift register 302. The first shift register 302 is composed of N delay units operating in synchronization with the symbol frequency, and sequentially receives the output of the mux 301. In this case, an input signal of each delayer of the first shift register 302 and an output signal of the last delayer are output to the comparator 305, and an output signal of the last delayer is output to the second shift register 303. Feedback. The third shift register 303 is also composed of N delayers operating in synchronization with the symbol frequency. The third shift register 303 sequentially shifts the output signal of the first shift register 302, and the output signal of the last delay unit is a mux 301. ) The memory 304 stores the received PRS signal and outputs it to the comparator 305. The comparator 305 compares the signal of each stage of the first shift register 302 with the output signal of the memory 304 and outputs the result to the integer frequency error calculator 204. That is, the comparator 305 outputs N + 1 comparison results to the integer frequency error calculator 204 simultaneously.

4 is a detailed block diagram of the integer frequency error calculator 204, wherein N + 1 correlation sum calculators 411 to 41N + 1, a mux 420, a size comparator 430, and a maximum value store ( 440). That is, the N + 1 correlation sum calculators 411 to 41N + 1 correspond to N + 1 output values of the comparator 305, respectively. Each of the N + 1 correlation sum calculators 411 to 41N + 1 receives the corresponding output of the comparator 350, obtains the correlation subtotal by the size of the preset subtotal, and then obtains the total correlation sum for one symbol period again. Output at 420. The mux 420 selects the largest value among the output values of the N + 1 correlation sum calculators 411 to 41N + 1 and outputs the largest value to the size comparator 430. The size comparator 430 compares the output value selected by the mux 420 with the size of the previous maximum value stored, and outputs the larger value to the maximum value store 440. The maximum value store 440 stores the output of the size comparator 430. That is, the value stored in the maximum value store 440 is updated with the value output from the size comparator 430 for one frame. When one frame is finished, the last updated value becomes an integer frequency error value.

The first correlation sum calculation unit 411 of the N + 1 correlation sum calculation units 411 to 41 N + 1 includes a partial sum correlator 411-1, an absolute value processor 411-2, and a total sum correlator 411-. 3) consists of. Since the internal configuration of the remaining correlation calculation units 412 ˜ 41 N + 1 is also the same as the first correlation sum calculation unit 411 described above, a detailed configuration description thereof will be omitted.

The subtotal correlator 411-1 selects an adder 611 that adds a previous correlation value fed back to the output of the partial correlator 203, and selects an output of the adder 611 only during a predetermined subtotal period, and otherwise, '0'. A selector 612 for selecting and a delayer 613 that stores the output of the selector 612 in synchronization with the symbol frequency and feeds back to the adder 611 as a previous correlation value.

The absolute value processor 411-2 is a delay 621 for storing and outputting the output of the subtotal correlator 411-1 in synchronization with a symbol frequency, and a real value and an imaginary number output from the delay 621. The calculator 622 obtains the absolute value of each value and then calculates the sum of the two absolute values, and a delay 623 stores and outputs the output of the operator 622 in synchronization with the symbol frequency.

The sum total calculator 411-3 selects the output of the absolute value processor 411-2 and selects '0' for the set symbol period, and outputs the selector 631 and the output of the selector 631. An adder 632 that adds the previous correlation value fed back, and a delayer 633 that stores the output of the adder 632 in synchronization with the symbol frequency and feeds back to the adder 632 as a previous correlation value.

In the present invention configured as described above, only one memory having a size of 2048 is used to reduce the complexity of the partial correlator 203 and the integer frequency error calculator 204 and to implement low power, and all operations are operated in synchronization with the symbol frequency.

The operation of the partial correlator 203 and the integer frequency error calculator 204 will now be described in detail with transmission mode 1 as an embodiment.

That is, the received PRS signal output from the multiplier 201 is stored in the memory 304 of size 2048 to take a partial correlation with the self-generated PRS signal.

In addition, the 1536 PRS signals generated by the PRS generator 202 are stored in the first shift register 302 through the mux 202 for 2048 cycles.

When the PRS signal generated by itself until the last delay of the first shift register 302 is shifted, thereafter, eight PRS signals of each stage of the first shift register 302 (that is, input signals of each delay) And the output signal of the last delay unit) are input to the comparator 305 to correlate with the received PRS signal stored in the memory 304. In this case, the eight PRS signals of each stage of the first shift register 302 may be PRS signals having eight different integer frequencies having an integer frequency interval of 1 kHz (if transmission mode 1). The first seven PRS signals among the PRS signals of the last stage of the first shift register 302 (that is, the last delay unit) are outputted to the comparator 305 and fed back to the second shift register 303. The second shift register 303 is required to give the first shift register 303 a signal necessary for a circular shift after all 1536 PRS signals have been generated in the PRS generator 202. That is, the PRS signal input to the second shift register 303 and shifted is input to the first shift register 302 through the mux 301.

At this time, in order to correlate the PRS signal generated by the comparator 305 with the received PRS signal, a multiplier is required as in Equation 1 below.

(Received PRS) x (Self-Generated PRS) ^*

 = (Received Real PRS + j (Received Imaginary PRS)) x (Self Generated Real PRS-j (Self Generated Imaginary PRS))

= ((Received Real PRS x Self-Generated Real PRS) + (Received Imaginary PRS x Self-Generated Imaginary PRS))

+ j ((received imaginary PRS x self-generated real PRS) + (received real PRS x self-generated imaginary PRS))

However, since the generated PRS signal is a noise-free signal, 0, 1, and -1 have one of three values, so that a correlation value can be obtained without a separate multiplier. That is, the comparator 305 can obtain a correlation value without a multiplier by taking a zero value when the generated PRS signal is 0, a received PRS signal value when 1, and an inverted received PRS value when -1. .

In this case, the eight comparators 305 are output to the corresponding correlation sum calculators 411 to 41N + 1 of the integer frequency error calculator 204 of FIG. 5, respectively.

The first to eighth correlation calculation units 411 to 41N + 1 of the integer frequency error calculator 204 have the same configuration except that the input signals are different.

Therefore, only operations of the first correlation sum calculation unit 411 among the first correlation sum calculation units to the eighth correlation sum calculation units 411 to 41N + 1 will be described. The rest is omitted since the operation according to the configuration is the same.

That is, the adder 511 of the partial sum calculator 411-1 of the correlation sum calculator 411 adds the correlation value output from the comparator 305 and the cumulative correlation value fed back from the delay unit 513 to selector 512. Output to the absolute value processor 411-2.

The selector 512 selects an output of the adder 511 and outputs the output to the delayer 513 during a preset subtotal period (that is, the subtotal size). The delay unit 513 updates a cumulative partial correlation value with a value output from the selector 512 in synchronization with the symbol frequency, and feeds back the updated cumulative correlation value to the adder 511.

On the other hand, the selector 512 selects a reset signal (ie, '0') and outputs the delayed signal to the delayer 513 to obtain the next correlation subtotal after the preset partial sum interval ends, and the delayer 513 is reset. In other words, the correlation subtotal is zero.

The delay unit 521 of the absolute value processor 411-2 stores the correlation partial sum output from the adder 511 of the partial sum calculator 411-1 in synchronization with the symbol frequency, and outputs the result to the operator 522. .

The operator 522 takes an absolute value for each real value and an imaginary value output from the delayer 521, calculates a sum of the two absolute values, and outputs the sum to the delayer 522 that operates in synchronization with the symbol frequency. That is, since the value input to the absolute value processor 411-2 is a complex number, the square of each real value and an imaginary value must be squared, and the sum is squared. Therefore, in the present invention, in order to reduce the complexity of the circuit, an absolute value is taken for each real value and an imaginary value, and the sum of the two absolute values is output. This reduces complexity with little impact on performance.

The output of the delayer 523 is input to the total calculator 411-3. The total sum calculator 411-3 accumulates the correlation partial sum output from the absolute value processor 411-2 for one symbol period to obtain the total correlation sum.

That is, the selector 531 of the total calculator 411-3 selects the correlation partial sum output from the absolute value processor 411-2 during one symbol period and outputs it to the adder 532. The adder 532 adds an output of the selector 531 and a cumulative correlation value fed back from the delay unit 533 and outputs the result to the delay unit 533. The delay unit 533 updates the cumulative total correlation value with the value output from the adder 532 in synchronization with the symbol frequency, and feeds the updated cumulative correlation value back to the adder 532 and simultaneously the mux 420. Will output

On the other hand, when one symbol is completed, the selector 531 selects '0' and outputs the result to the adder 532, and the adder 532 outputs the feedback accumulated correlation value to the delayer 533 as it is. In other words, the value of the delay unit 533 is not updated.

In this way, the eight total correlation sums obtained by the correlation sum calculators 411 to 41N + 1 are output to the mux 420, and the mux 420 has the largest value among the eight total correlation sums input. Select and output to the size comparator 430. The comparator 430 compares the output value of the selector 420 with the magnitude of the previous maximum value fed back and outputs the larger value among them as the maximum value to the maximum value store 440. That is, the output of the comparator 430 is output to the maximum value storage unit 440 and fed back to its input terminal and then compared with the output value of the selector 420. At this time, if the output value of the selector 420 is larger than the previous maximum value, the value stored in the maximum value storage unit 440 is updated with a new value, and if the output value is small, the value stored in the maximum value storage unit 440 is the previous value. Keep the value as it is. This operation is repeated for every symbol so that when a frame is finished, the value stored in the maximum store 440 becomes the maximum value of the frame. The maximum value at this time becomes an integer multiple frequency error value and is transmitted to the integer multiple frequency error corrector 205 so that the integer multiple frequency error is corrected.

As described above, according to the frequency error correcting apparatus of the DMB receiver according to the present invention, even when a symbol timing offset exists in a PRS signal received by using a partial correlator, the integer frequency error is accurately detected by removing the integer frequency error. In fact, when terrestrial DMB signals are received, accurate frequency synchronization can be achieved even under poor reception conditions. In particular, by simplifying the hardware architecture of the partial correlator and integer frequency error calculator to find integer frequency error, the complexity of the entire DMB receiver can be reduced and power consumption can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

1 is a configuration block diagram of a typical DMB receiver

2 is a block diagram showing an example of an integer frequency error correction apparatus according to the present invention

3 is a detailed block diagram illustrating an example of the partial correlator of FIG.

4 is a detailed block diagram illustrating an example of an integer frequency error calculator of FIG. 2.

Explanation of symbols for main parts of the drawings

100: antenna 101: tuner

102: AGC unit 103: A / D converter

104: I / Q distributor 105: mode detector

106: signal synchronization unit 107: OFDM demodulator

108: frequency deinterleaving unit 109: channel divider 1

110: FIC decoder 111: time deinterleaving unit

112: convolutional decoder 113: energy descrambler

114: channel distributor 2 115: weaving deinterleaving unit

116: RS decoder 117: FIC data decoder

118: Audio / Data Decoder 119: Video Decoder

201: multiplier 202: PRS generator

203: Partial Correlator 204: Integer Frequency Error Calculator

205: integer multiple frequency error corrector

301,420: mux 302,303: shift register

304: Memory 305: Comparator

411-41N + 1: Correlation calculation part 411-1: Subtotal calculator

411-2: Absolute Value Handler 411-3: Total Calculator

430: size comparator 440: maximum value storage

Claims (7)

An integer frequency error correction apparatus of a DMB receiver which estimates and corrects an integer frequency error from an inverse fast Fourier transform (IFFT) received signal, A PRS generator which generates a known PRS signal according to a transmission mode and outputs the PRS signal as a reference PRS signal; After having the shift registers and the memory and the comparator with N delays, the self-generated PRS signal is input to the shift register and shifted sequentially, and the received PRS signal is input to the memory and stored, and then shifted through the comparator. A partial correlator for obtaining and outputting a partial correlation value between the N + 1 outputs of each stage of the register and the signal stored in the memory; And N + 1 partial correlation values of the partial correlator are accumulated for each preset subtotal interval to obtain a correlation subtotal, and this correlation subtotal is accumulated for another symbol period to obtain a total correlation sum, and then, among the N + 1 total correlation sums. If the largest value is larger than the stored maximum value, the process of updating the maximum value stored to the largest total correlation sum for one frame is repeated. After one frame, the maximum value is determined as an integer multiple frequency error. Frequency error correction apparatus for a DMB receiver, characterized in that it comprises a calculator. The method of claim 1, wherein the partial correlator A mux for selecting a PRS signal generated by the PRS generator while the PRS signal is generated by the PRS generator and selecting and outputting a PRS signal that is fed back when all are generated; A first shift register configured to have N delays operating in synchronization with a symbol frequency, the first shift register receiving the output of the MUX and sequentially shifting the signal, and outputting a signal of each stage to correlate with the received PRS signal; A second shift register configured to have N delays operating in synchronization with a symbol frequency, the second shift register receiving the output of the last delay of the shift register, shifting sequentially, and feeding back a mux; A memory for storing the received PRS signal; In the DMB receiver comprising a comparator for outputting N + 1 correlation values by obtaining a correlation value between the N + 1 PRS signals output from each stage of the first shift register and the signal stored in the memory, respectively Frequency error correction device. The method of claim 2, wherein the transmission mode 1 The N + 1 PRS signal of each stage of the first shift register is a PRS signal having 8 different integer frequencies having an integer frequency interval of 1 kHz which is different from each other by 1 kHz. The method of claim 2, wherein the memory is A frequency error correcting apparatus in a DMB receiver, characterized in that the memory is 2048 sample size. The method of claim 1, wherein the comparator When a self-generated PRS signal of each stage of the first shift register is 0, a value of 0 is selected, a value of a received PRS signal is set to 1, and an inverted received PRS value is selected to be output as a correlation value. Frequency error correction apparatus in the DMB receiver. The method of claim 1, wherein the integer frequency error calculator Corresponding to N + 1 correlation values of the partial correlators, respectively, the correlation values are accumulated for a predetermined subtotal interval to obtain a correlation subtotal, and the correlation subtotals are accumulated for another symbol period to obtain a total correlation sum. N + 1 correlation sum calculation unit for outputting one total correlation sum, A size comparison unit comparing the magnitudes of the N + 1 total correlations and detecting a largest value and determining whether the detected maximum value is larger than a stored maximum value; A DMB, characterized in that the maximum stored value is updated with the largest total correlation detected if the maximum total correlation detected is greater than the maximum value stored, and the maximum value storage is configured to keep the previous maximum value if it is not large. Frequency error correction device at the receiver. The method of claim 6, wherein each correlation sum calculator A subtotal calculator for accumulating a correlation value output from the partial correlator for a predetermined subtotal period to obtain a correlation subtotal; An absolute value processor that takes an absolute value and adds two absolute values to the real and imaginary values of the correlation subtotals output from the subtotal calculator; And a total sum calculator for accumulating the output of the absolute value processor for one symbol period to obtain a total correlation sum.