KR20050073562A - Semiconductor memory - Google Patents

Abstract

A plurality of flags are formed so as to correspond to respective memory cell groups, each consisting of a plurality of volatile memory cells. Each flag indicates that the memory cell contains data in a second storage mode. When the first storage mode in which each memory cell holds data is switched to the second storage mode in which memory cells of each memory cell group holds the same data, each flag is reset in response to the first access of the corresponding memory cell group. For this, in each memory cell group, only the first access is performed in the second storage mode. In the aforementioned switching operation, by accessing a memory cell by the mode in accordance with the flag, a system managing the semiconductor memory can freely access the memory cell even during the switching operation. As a result, it is possible to substantially eliminate the switching time.

Description

Semiconductor Memory {SEMICONDUCTOR MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory which requires a refresh operation to hold data written in a memory cell.

The memory capacity required for portable terminals such as cellular phones is increasing year by year. Among them, a dynamic RAM (hereinafter referred to as DRAM) has been used as a work memory of a portable terminal instead of the conventional static RAM (hereinafter referred to as SRAM). Since the number of elements constituting the memory cell is smaller than that of the SRAM, the DRAM can have a smaller chip size and a lower chip cost than the SRAM.

On the other hand, the semiconductor memory mounted in the portable terminal is required to be low power consumption in order to make the battery usable for a long time. Unlike SRAMs, DRAMs require refresh operations on a regular basis to hold data written to memory cells. For this reason, when using DRAM as a work memory of a portable terminal, even if a portable terminal is not used, power is consumed only by holding | maintaining data, and a battery is consumed.

In order to reduce the power consumption of the DRAM in standby (when in low power consumption mode), partial refresh technology and twin cell technology have been developed. The partial refresh technique is disclosed in Japanese Patent Laid-Open No. 2000-298982. Twin cell technology is disclosed in Japanese Patent Laid-Open No. 2001-143463.

In the partial refresh technique, the number of memory cells to be refreshed is reduced by limiting the memory cells holding the data in the standby state. Since the number of refreshes is reduced by reducing the memory cells to be refreshed, power consumption in standby can be reduced.

In twin cell technology, since complementary data is stored in two memory cells (pair of memory cells) respectively connected to complementary bit lines, the charge held in the pair of memory cells is doubled. Since the "H" data and "L" data are respectively held in the two memory cells, the refresh interval is determined from the longer data retention time of the "H" data and the "L" data. That is, the worst data retention time is not the characteristic of one memory cell but the sum of the characteristics of two memory cells. In contrast, in a single memory cell, the refresh interval is determined from the shorter data holding time of the "H" data and the "L" data. As described above, in the twin cell technology, since data is held in two memory cells, even if there is a small leakage path in one memory cell, it can be supplemented with the other memory cell.

Hereinafter, the prior art documents related to this invention are listed.

Patent Document 1: Japanese Patent Application Laid-Open No. 2000-298982

Tukhemunheo 2: JP 2001-143463 A

1 is a block diagram showing a first embodiment of a semiconductor memory of the present invention.

FIG. 2 is a block diagram showing in detail the operation mode control circuit shown in FIG.

FIG. 3 is a timing diagram showing the operation of the operation mode control circuit shown in FIG.

4 is a block diagram showing in detail the refresh timer shown in FIG.

FIG. 5 is a timing chart showing operations of the refresh timer and the refresh command generation circuit in the first embodiment. FIG.

FIG. 6 is a block diagram showing details of the refresh address counter shown in FIG.

FIG. 7 is a timing diagram showing the operation of the reset circuit of the refresh address counter shown in FIG.

FIG. 8 is an explanatory diagram showing the operation of the refresh address counter shown in FIG.

FIG. 9 is a block diagram showing details of main parts of the memory core shown in FIG.

FIG. 10 is a circuit diagram showing in detail the quarter-word decoder shown in FIG.

FIG. 11 is a circuit diagram showing in detail the sense amplifier and the precharge circuit shown in FIG. 9.

FIG. 12 is a timing diagram illustrating operations of the sense amplifier control circuit and the precharge control circuit shown in FIG. 1.

FIG. 13 is a circuit diagram showing the details of the flag circuit, the flag detection circuit shown in FIG. 1 and the main parts of the word decoder.

Fig. 14 is a timing diagram showing the operation of the flag circuit and the flag detection circuit in the normal operation mode after partial refresh.

FIG. 15 is a timing diagram showing other operations of the flag circuit and the flag detection circuit in the normal operation mode after the partial refresh. FIG.

16 is a timing diagram showing other operations of the flag circuit and the flag detection circuit in the normal operation mode after the partial refresh.

17 is a timing diagram showing other operations of the flag circuit and the flag detection circuit in the normal operation mode after the partial refresh.

18 is a circuit diagram showing in detail the flag reset circuit shown in FIG.

FIG. 19 is a timing diagram showing the operation of the flag reset circuit shown in FIG.

20 is a timing chart showing an operation in a normal operation mode in the first embodiment.

FIG. 21 is a timing chart showing an operation during a shared refresh mode in the first embodiment. FIG.

FIG. 22 is a timing chart showing the operation during the partial refresh mode according to the first embodiment. FIG.

FIG. 23 is a timing chart showing an operation in the case where the apparatus returns to the low power consumption mode from the normal operation mode in the first embodiment.

24 is a timing diagram illustrating an example in which refresh requests are sequentially generated after returning to the normal operation mode.

25 is a timing diagram illustrating an example in which a read command is supplied after the return to the normal operation mode and before the first refresh request.

Fig. 26 is a timing diagram showing an example in which a write command is supplied before the first refresh request after returning to the normal operation mode.

27 is an explanatory diagram showing a relationship between an external command cycle time EXTC and an internal read cycle time IRD.

28 is an explanatory diagram showing the relationship between the external command cycle time EXTC and the internal write cycle time IWR1.

29 is an explanatory diagram showing the relationship between the external command cycle time EXTC and the internal write cycle time IWR2.

30 is a timing diagram showing the operation of the pseudo SRAM of the first embodiment.

Fig. 31 is a block diagram showing the second embodiment of the semiconductor memory of the present invention.

32 is a block diagram showing details of the refresh timer shown in FIG.

FIG. 33 is a timing chart showing operations of the refresh timer and the refresh command generation circuit in the second embodiment. FIG.

34 is a block diagram showing details of the refresh address counter shown in FIG.

35 is an explanatory diagram showing the operation of the refresh address counter shown in FIG.

36 is a block diagram showing details of main parts of the memory core shown in FIG.

FIG. 37 is a circuit diagram showing details of the 1/4 word decoder shown in FIG.

FIG. 38 is a timing diagram illustrating operations of the sense amplifier control circuit and the precharge control circuit shown in FIG. 31.

39 is a circuit diagram showing the details of the flag circuit and the flag detection circuit shown in FIG. 31 and the main parts of the word decoder.

40 is a circuit diagram showing in detail the flag reset circuit shown in FIG.

Fig. 41 is a timing chart showing the operation in the normal operation mode in the second embodiment.

FIG. 42 is a timing chart showing an operation during the shared refresh mode in the second embodiment. FIG.

FIG. 43 is a timing chart showing the operation during the partial refresh mode according to the second embodiment. FIG.

An object of the present invention is to reduce power consumption for holding data in a semiconductor memory having a volatile memory cell.

Another object of the present invention is to switch from an operation mode for holding data to a mode for accessing data at high speed.

In one aspect of the semiconductor memory of the present invention, a plurality of memory cell groups are constituted by a plurality of volatile memory cells that are each connected to a predetermined number of word lines. The control circuit executes the operation of the first storage mode for holding data for each memory cell and the operation of the second storage mode for holding the same data in the memory cells of each memory cell group. The second memory mode is a mode in which the so-called partial technology and the twin cell technology are fused, and some data held in the first memory mode are held in the plurality of memory cells. For this reason, the data holding time of the memory cell in the second storage mode is longer than in the first storage mode. As a result, the refresh rate of the memory cells can be greatly reduced, and power consumption can be reduced.

A plurality of flags each formed in correspondence with the memory cell group indicates that the memory cell stores data in the second storage mode as a set state. In the switching operation of switching all memory cells from the state of the second memory mode to the state of the first memory mode, the flag reset circuit resets each flag in accordance with the first access of the corresponding memory cell group. For this reason, for each memory cell group, the first access is necessarily performed in the second storage mode.

Since the second storage mode stores data in a plurality of memory cells to increase the refresh interval, there is a possibility that the amount of memory (for example, the amount of charge) per memory cell is smaller than that of the first memory mode. For this reason, when the first access is performed in the first storage mode in the switching operation, the data may be lost. By executing the first access in the second storage mode, it is possible to prevent the data of the memory cells being accessed from being lost.

The flag is formed for each memory cell group which is an access unit in the second storage mode. For this reason, it is possible to determine in which memory mode the memory cell holds data for each memory cell accessed. In other words, memory cells holding data in the second storage mode and memory cells holding data in the first storage mode can be mixed during the switching operation. In the switching operation, by accessing the memory cell in the mode according to the flag, the system managing the semiconductor memory can freely access the memory cell even during the switching operation. As a result, substantial switching time can be eliminated.

In another aspect of the semiconductor memory of the present invention, the flag set circuit sets all flags before the switching operation. For this reason, the memory cells of all the memory cell groups can be reliably shifted from the second storage mode to the first storage mode.

In another aspect of the semiconductor memory of the present invention, the flag detecting circuit detects whether or not a corresponding flag is set when the memory cell is accessed. The control circuit executes the operation of the first storage mode or the operation of the second storage mode in accordance with the detection result of the flag detection circuit. By detecting the state of the flag by the flag detection circuit, the operation of the control circuit can be simplified, and the circuit configuration can be simplified.

In another aspect of the semiconductor memory of the present invention, when the first access is a write operation, the control circuit reads data from all the memory cells of the selected memory cell group and rewrites the read data into these memory cells. That is, the data held in the second storage mode is rewritten to the plurality of memory cells in the second storage mode again. By rewriting the data, data is strongly written to each memory cell. Thereafter, data is written to the memory cell in which writing is instructed. That is, data is written to the memory cell indicated in the first storage mode. Memory cells for which writing in the memory cell group is not instructed retain original data. Therefore, even if a write instruction is given to one of the memory cells holding the data in the second storage mode, the new write data can be held in the predetermined memory cell without destroying the original data. After that, the refresh is performed at the refresh interval of the first storage mode, so that any memory cell can read data even if the next access is performed in the first storage mode. As a result, the system can execute the write operation without waiting even during the switching operation.

In another aspect of the semiconductor memory of the present invention, the sense amplifier is connected to the memory cell via a bit line. The control circuitry continues to activate the sense amplifiers during reading, rewriting and writing of data to the memory cells. For this reason, the frequency of activation of the sense amplifier can be reduced, and the recording operation time can be shortened.

In another aspect of the semiconductor memory of the present invention, in the write operation, the word control circuit is configured to cancel word lines connected to the memory cells except for the memory cells to which writing in the memory cell group is instructed during activation of the sense amplifier. It is a choice. Write data is not transferred to the memory cells connected to the unselected word lines. For this reason, the operation of rewriting data in the second storage mode and the operation of recording data in the first storage mode can be performed by simple control while activating the sense amplifier.

In another aspect of the semiconductor memory of the present invention, when the first access is a read operation, the control circuit reads data from all the memory cells of the memory cell group, outputs the read data to the outside of the semiconductor memory, and simultaneously The exported data is rewritten to the memory cell. That is, the data held in the second storage mode is rewritten to the plurality of memory cells in the second storage mode again. For this reason, the system can execute the read operation without waiting even during the switching operation.

In another aspect of the semiconductor memory of the present invention, when the first access is a refresh operation, the control circuit reads data from all memory cells of the selected memory cell group, and rewrites the read data into the memory cell. That is, the data held in the second storage mode is rewritten to the plurality of memory cells in the second storage mode again. Since the flag is reset by the first access, each memory cell in the memory cell group then operates in the first storage mode. By the refresh operation of rewriting data, data is strongly written to each of the refresh-accessed memory cells, and subsequent refreshes are performed at refresh intervals of the first storage mode. Therefore, thereafter, even when each memory cell is accessed in the first storage mode, data can be reliably read or refreshed.

In another aspect of the semiconductor memory of the present invention, the semiconductor memory has a normal operation mode which operates in accordance with an access command supplied from the outside and a refresh command generated therein, and a data holding mode which operates only in accordance with the refresh command. The data is stored in the first storage mode during the normal operation mode, and stored in the second storage mode during the data retention mode. By the application of the present invention, the system can immediately access the semiconductor memory even when the memory cells of the first storage mode and the memory cells of the second storage mode are mixed after switching from the data holding mode to the normal operation mode. That is, the system can be operated at high speed.

In another aspect of the semiconductor memory of the present invention, the memory cells of the memory cell group include partial memory cells that store data held during the second storage mode. The control circuit reads out the data stored in the partial memory cells for each refresh command until all the memory cell groups are in the second storage mode state after the transition from the normal operation mode to the data retention mode. The shared refresh operation for writing to all memory cells in the memory cell group is executed. By the shared refresh operation, data stored in the first memory mode in the partial memory cells can be stored in the second memory mode in each memory cell of the memory cell group. By changing the memory cells in the first storage mode to the second storage mode for each refresh operation, it is possible to efficiently switch from the normal operation mode to the data retention mode.

In another aspect of the semiconductor memory of the present invention, in the first storage mode, one memory cell connected to one line of word lines holds one bit of information. In the second storage mode, all memory cells in the memory cell group hold one bit of information. For this reason, by selecting one or more lines of the word lines, the memory cells can be easily accessed in the first storage mode or the second storage mode.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described using drawing. In the figure, the signal line shown by the bold line shows that it consists of several lines. The block to which the thick signal line is connected is composed of a plurality of circuits. The signal with "Z" at the end represents positive logic. The signal with "/" at the head and the signal with "X" at the end represent negative logic. The double circles in the figure represent external terminals. The same code as the signal name is used for the signal line through which the signal is transmitted. In the following description, the "clock signal CLK" may be abbreviated as "CLK signal" and the "chip enable signal CE", such as "CE signal", in which the signal name is omitted.

1 shows a first embodiment of a semiconductor memory of the present invention. This semiconductor memory is formed as a pseudo SRAM having a memory cell of DRAM and having an interface of an SRAM using CMOS technology. The pseudo SRAM performs a refresh operation periodically inside the chip without receiving a refresh command from the outside, and holds the data written to the memory cell. This pseudo SRAM is used for, for example, a work memory mounted in a mobile phone.

The pseudo SRAM includes the command decoder 10, the operation mode control circuit 12, the refresh timer 14, the refresh command generation circuit 16, the refresh address counter 18, the address buffer 20, and the data input / output buffer 22. And a multiplexer 24, a flag reset circuit 26, a flag detection circuit 28, a flag circuit 30 (flag set circuit), a core control circuit 32, and a memory core 34. The operation mode control circuit 12 and the core control circuit 32 operate as control circuits for performing operations in the first and second storage modes described later.

The command decoder 10 receives a command signal (chip enable signal CE, write enable signal / WE and output enable signal / OE) through an external terminal, decodes the received command, and reads out a control signal RDZ. Alternatively, the write control signal WRZ is output. The command decoder 10 also outputs a partial mode start signal PREFS (pulse signal) in synchronization with the falling edge of the CE signal, and the partial mode release signal PREFR (pulse signal) in synchronization with the rising edge of the CE signal. Outputs

The operation mode control circuit 12 outputs the mode signals MODE1, MODE2, and MODE3 in accordance with the partial mode start signal PRES, the partial mode release signal PREREF, and the refresh control signal REREF. The refresh timer 14 outputs the refresh request signal TREF having an oscillation period in accordance with the mode signal MODE1-3.

When the refresh command generation circuit 16 receives the refresh request signal TREF faster than the read control signal RDZ or the write control signal WRZ, the refresh command generation circuit 16 receives the refresh control signal REFZ in synchronization with the refresh request signal TREF. Output When the refresh command generation circuit 16 receives the refresh request signal TREF later than the read control signal RDZ or the write control signal WRZ, the refresh command generation circuit 16 performs a read operation in response to the RDZ signal or a write operation in response to the WRZ signal. After that, the refresh control signal REFZ is output. That is, the refresh command generation circuit 16 operates as an arbiter circuit that determines the priority of the read operation, the write operation and the refresh operation.

The refresh address counter 18 updates the refresh address signal REFAD R5-0 in synchronization with the refresh control signal REFZ. The update specification of the refresh address signal REFAD is changed in accordance with the mode signal MODE2-3. The number of bits of the refresh address signal REFAD corresponds to the number of word lines WL formed in the memory core 34 (64 lines in this example). For this reason, the number of bits of the refresh address signal REFAD is not limited to six bits, but is set in accordance with the number of word lines WL formed in the memory core 34.

The address buffer 20 receives the address signal AD through the address terminal, and outputs the received signal as a row address signal RAD (high address) and a column address signal CAD (lower address). In other words, this pseudo SRAM is an address non-multiplexed memory that simultaneously receives an upper address and a lower address.

The data input / output buffer 22 receives the read data through the common data bus CDB, outputs the received data to the data terminal DQ, receives the write data through the data terminal DQ, and receives the received data. To the common data bus (CDB). The number of bits of the data terminal DQ is, for example, 16 bits.

The multiplexer 24 outputs the refresh address signal REFAD as the row address signal RAD2 when the refresh control signal REFZ is at the high level, and the refresh control signal REFZ is at the low level. At this time, the row address signal RAD is output as the row address signal RAD2.

When the flag reset circuit 26 receives the flag detection signal FDTC, it outputs a flag reset signal FRAX or FRBX in accordance with the least significant bit X0 of the row address signal RAD2. The flag detection circuit 28 outputs the value of a pair of flags hold | maintained as flag output signals S1AX and S1BX, respectively, in synchronization with the decode signal XDX. The flag detection circuit 28 sets the flag in synchronization with the pulse of the partial mode release signal PRER, and resets the flag in synchronization with the pulses of the flag reset signals FRAX and FRBX, respectively. The flag circuit 30 outputs the flag detection signal FDTC when it receives the flag output signals S1AX and S1BX.

The core control circuit 32 has a register 36, a timing control circuit 38, a sense amplifier control circuit 40, and a precharge control circuit 42. The register 36 reads the read control signal RDZ or the write control signal when the refresh command generation circuit 16 outputs the refresh control signal REFZ in preference to the read control signal RDZ or the write control signal WRZ. Hold (WRZ) temporarily. The timing control circuit 38 outputs a row activation signal RASZ when one of the RDZ signal, the WRZ signal, and the REFZ signal is received. The sense amplifier control circuit 40 outputs sense amplifier activation signals PSA and NSA for activating the sense amplifier SA in synchronization with the RASZ signal. The precharge control circuit outputs the precharge signal PREZ when the memory core 34 is not operated in synchronization with the RASZ signal. The operation timings of the sense amplifier control circuit 40 and the precharge control circuit 42 are changed in accordance with the values of the least significant bit X0 of the mode signal MODE2 and the refresh address signal REFAD.

The memory core 34 includes a sense amplifier SA, a precharge circuit PRE, a memory cell array ALY, a word decoder WDEC, a column decoder CDEC, a sense buffer SB, and a write amplifier WA. Have The sense amplifier SA operates according to the sense amplifier activation signals PSA and NSA. The precharge circuit PRE operates according to the precharge signal PREZ. The memory cell array ALY includes a plurality of volatile memory cells MC (dynamic memory cells; hereinafter referred to as C00, C10, etc.), a plurality of word lines WL and a plurality of bit lines connected to the memory cells MC. Has (BL) The memory cell MC is the same as the memory cell of a general DRAM, and has a capacitor for holding data as a charge and a transfer transistor disposed between the capacitor and the bit line BL. The gate of the transfer transistor is connected to the word line WL.

The word decoder WDEC selects one or two lines of the word lines WL according to the row address signal RAD2, the mode signal MODE3, and the flag detection signal FDTC, and selects the selected word line WL. Raise to high voltage. The word decoder WDEC outputs the decode signal XDX corresponding to the word line WL in synchronization with the selection of the word line WL.

The column decoder CDEC, in accordance with the column address signal CAD, turns on the column line signal (CSW described later) to turn on the column switch (CSW in FIG. 4 to be described later) connecting the bit line BL and the data bus DB, respectively. CLZ of FIG. 4 is output. The sense buffer SB amplifies the signal amount of the read data on the data bus DB and outputs it to the common data bus CDB. The write amplifier WA amplifies the signal amount of the write data on the common data bus CDB and outputs it to the data bus DB.

FIG. 2 shows the operation mode control circuit 12 shown in FIG. 1 in detail.

The operation mode control circuit 12 has a counter 12a and a mode signal generation circuit 12b. The counter 12a counts in synchronization with the rising edge of the refresh control signal REFZ, and outputs the counter signal CNT64 at the 64th count. The counter 12a is reset by receiving the reset signal RESET. The reset signal RESET is output when the mode signal MODE1 or the mode signal MODE3 is at a high level.

On the other hand, the count number "64" corresponds to the number of word lines WL formed in the memory core 34. In the present embodiment, for ease of explanation, the word line WL is 64 lines, but the word line WL is actually formed of, for example, 2048 lines. At this time, the counter 48a outputs a counter signal at the 2048th count, respectively.

The mode signal generation circuit 12b outputs the mode signal MODE1-3 in accordance with the partial mode start signal PREFS, the partial mode release signal PREREF and the counter signal CNT64.

FIG. 3 shows the operation of the operation mode control circuit 12 shown in FIG.

The pseudo SRAM of this embodiment is in the normal operation mode while the CE signal is at the high level, and is in the data holding mode (low power consumption mode) while the CE signal is at the low level. Then, the shared refresh is executed at the start of the data retention mode (shared refresh mode), and the partial refresh is executed after the shared refresh (partial refresh mode).

The refresh operation during the normal operation mode is performed for one memory cell MC for each bit line BL in response to the operation of the sense amplifier SA (single cell operation). The refresh operation during the data retention mode is performed for two memory cells MC for each bit line BL (twin cell operation) corresponding to the operation of the sense amplifier SA. In other words, in the normal operation mode, one line of word lines WL is selected for one refresh operation, and in the data holding mode, two lines of word lines WL are selected for one refresh operation. The data retention mode is composed of a combination of so-called partial refresh technology and twin cell technology. For this reason, the power consumption in the data holding mode is significantly reduced as compared with the prior art.

The pseudo SRAM recognizes the normal operation mode when the mode signal MODE1 is at the high level, recognizes the shared refresh mode (data holding mode) when the mode signal MODE2 is at the high level, and the mode signal MODE3 is at the high level. In this case, the partial refresh mode (data holding mode) is recognized.

In the normal operation mode before the data holding mode, the data of the memory cells is held in the first storage mode, except in special cases. The special case is a case where the data is transferred to the data holding mode immediately after returning from the data holding mode to the normal operation mode as shown in FIG.

In the shared refresh mode, the data of the memory cells is held in the first storage mode or the second storage mode. More specifically, in the shared refresh mode, the state of the memory cells sequentially transitions from the first storage mode to the second storage mode for each refresh request.

In the partial refresh mode, the data of the memory cells is held in the second storage mode. In the normal operation mode after the partial refresh mode, the data of the memory cells is held in the second storage mode or the first storage mode. More specifically, in the normal operation mode after the partial refresh mode, the state of the memory cells sequentially transitions from the second storage mode to the first storage mode for each access (external access command or refresh command).

When the operation mode control circuit 12 receives the partial mode setting signal PRES during the normal operation mode, the operation mode control circuit 12 changes the mode signals MODE1 and MODE2 to low level and high level, respectively, and the operation mode is shared refresh in the normal operation mode. The mode shifts (Fig. 3 (a)). The reset signal RESET is deactivated in synchronization with the change of the mode signal MODE1 to the low level.

The counter 12a receives the low level of the reset signal RESET, releases the reset state, and starts the count operation in synchronization with the refresh control signal REFZ (Fig. 3 (b)). The refresh operation is executed in response to the refresh control signal REFZ. In the shared refresh mode, since all word lines WL of the memory core 34 must be selected, the refresh control signal REFZ is output 64 times. On the other hand, the operations of the refresh timer 14 and the refresh command generation circuit 18 which generate the refresh control signal REFZ will be described later with reference to FIG. 35.

The counter 12a outputs the counter signal CNT64 in synchronization with the 64th counting operation (Fig. 3 (c)). The operation mode control circuit 12 changes the mode signal MODE2 to a low level in synchronization with the counter signal CNT64, and changes the mode signal MODE3 to a high level (Fig. 3 (d)). The operation mode shifts from the shared refresh mode to the partial refresh mode. The reset signal RESET is activated in synchronization with the change of the mode signal MODE3 to the high level (Fig. 3 (e)). The counter 12a is reset by receiving the high level of the reset signal RESET. In the period in which the mode signal MODE3 is at the high level, the partial refresh is sequentially executed.

The partial mode release signal PRER is output in response to the change of the CE signal supplied through the external terminal to the high level (Fig. 3 (f)). When the operation mode control circuit 12 receives the partial mode release signal PREREF during the partial refresh mode, the operation mode control circuit 12 changes the mode signals MODE3 and MODE1 to low and high levels, respectively, and shifts the operation mode to the normal operation mode. (FIG. 3 (g)).

FIG. 4 shows the refresh timer 14 shown in FIG. 1 in detail.

The refresh timer 14 divides the oscillator 14a generating the oscillation signal OSC0 and the frequency divider 14b which divides the frequency of the OSC0 signal and generates the oscillation signals OSC1, OSC2, and OSC3, respectively. 14c and 14d and the oscillation signals OSC1, OSC2, and OSC3 are selected in accordance with the mode signals MODE1-3 and have a multiplexer 14e for outputting as the refresh request signal TREF. The dividers 14b, 14c, and 14d convert the frequency of the OSC0 signal into one eighth, one sixteenth and one thirty-two respectively.

5 shows the operation of the refresh timer 14 and the refresh command generation circuit 16.

The refresh timer 14 outputs the oscillation signals OSC1, OSC2, and OSC3 as the refresh request signal TREF when the mode signals MODE1, MODE2, and MODE3 are at high levels, respectively. The refresh command generation circuit 16 outputs the refresh request signal TREF as the refresh control signal REFZ when the mode signals MODE1 and MODE3 are each at a high level. The refresh command generation circuit 16 outputs the refresh control signal REFZ twice in synchronization with the refresh request signal TREF when the mode signal MODE2 is at a high level.

FIG. 6 shows the refresh address counter 18 shown in FIG. 1 in detail.

The refresh address counter 18 has a logic gate which controls the reset circuit 18a, the counters 18b and 18c, and the counters 18b and 18c. The reset circuit 18a includes a pulse generation circuit for generating a positive pulse in synchronization with the falling edge of the refresh control signal REFZ, and a D flip-flop for latching the mode signal MODE2 in synchronization with the output signal of the pulse generation circuit. And a NAND gate for detecting the rising edge of the mode signal MODE2.

The counter 18b counts in synchronization with the refresh control signal REFZ to generate the least significant bit R0 of the refresh address signal REFAD. The counter 18b is reset when the mode signal MODE3 is at a high level and in synchronization with the rising edge of the mode signal MODE2.

The counter 18c counts in synchronization with the refresh control signal REFZ when the mode signal MODE3 is at a high level, and updates the bit R5-1 of the refresh address signal REFAD. The counter 18c is connected to the address signal R0 output from the counter 18b when the mode signals MODE1 and MODE2 are at a high level (except for a predetermined period after the rising edge of the mode signal MODE2). A synchronous count operation is performed to update the bit R5-1.

FIG. 7 shows the operation of the reset circuit 18a shown in FIG.

The pulse generation circuit outputs a pulse signal to the node ND1 in synchronization with the falling edge of the refresh control signal REFZ (Fig. 7 (a)). The D flip-flop latches the mode signal MODE2 in synchronization with the pulse signal of the node ND1, and outputs the inversion logic of the mode signal MODE2 to the node ND2 (Fig. 7 (b)). For this reason, after the mode signal MODE2 is changed to the high level, the node ND2 is changed to the low level in synchronization with the first refresh control signal REFZ (Fig. 7 (c)). And the AND logic of the logic level of the mode signal MODE2 and the node ND2 is output to the node ND3 (FIG. 7 (d)). The counter 18b shown in FIG. 6 is reset during the first refresh operation period after the high level period of the node ND3, that is, the mode signal MODE2 is changed to the high level.

FIG. 8 shows the operation of the refresh address counter 18 shown in FIG.

The refresh address counter 18 is a six-bit refresh address signal R5- in synchronization with the refresh control signal REFZ when the mode signals MODE1, 2 are at a high level, that is, during the normal operation mode and during the shared refresh mode. 0) is counted up sequentially. The refresh address counter 18 sequentially counts the 5-bit refresh address signal R5-1 in synchronization with the refresh control signal REFZ when the mode signal MODE3 is at a high level, that is, during the partial refresh mode. Up. At this time, the refresh address signal R0 is fixed at the low level.

FIG. 9 shows the main part of the memory core 34 shown in FIG. 1 in detail.

The word decoder WDEC of the memory core 34 has a quarter word decoder 44 and a plurality of sub word decoders 46a corresponding to the main word lines MW0, MW1, ..., respectively. .

When the mode signal MODE3 and the flag detection signal FDTC are at the low level, the quarter word decoder 44 has the lower two bits X1 and X0 of the row address signal RAD2 and its inverted bits (/ X1, / X0) outputs any one of the decode signals X11, X10, X01, and X00. The quarter word decoder 44 has the low order bit X1 of the row address signal RAD2 and its inverting bit / X1 when either the mode signal MODE3 or the flag detection signal FDTC is at a high level. Therefore, two decode signals X11, X10 or X01, X00 are output. The quarter word decoder 44 operates as a control circuit for performing the operations of the first and second storage modes described later.

Each sub word decoder 46a is activated when the main word lines MW0, MW1, ... are at a high level, and according to the decode signals X11, X10, X01, X00, the sub word lines SW (SW0P). , SW1, SW2P, SW3, ...). The main word line MW is selected by a predecoder (not shown) in accordance with the upper bits of the row address signal RAD2. Then, the memory cell MC connected to the selected sub word line SW is accessed. As described above, in this embodiment, the word line WL shown in FIG. 1 is constituted by the main word line MW and the sub word line SW.

A partial region PA (memory cell group; a thick dashed line frame) is formed by memory cells connected to two adjacent sub word lines (e.g., SW0P, SW1). In the partial area PA, memory cells connected to the bit lines BL (BL0, BL1, ...) and / BL (/ BL0, / BL1, ...) are connected to different subword lines SW. .

The word "P" at the end of the sub word line SW indicates a partial word line. The data being written to the memory cells (for example, the partial memory cells C00, C01 ..., C0m) connected to the partial word line SWP is held during the data holding mode. The sub word line SW with no "P" at the end indicates a shared word line. The data of the memory cells MC (for example, the shared memory cells C10, C11, ... C1m) connected to the shared word line SW is not held during the data holding mode.

The partial word line SWP and the normal sub word line SW are alternately wired. That is, the word lines SWP and SW are wired adjacent to each other. As will be described later, the word lines SWP and SW are selected simultaneously with each other during the data retention mode so that two memory cells are simultaneously accessed (twin cell operation). For this reason, by wiring these word lines SWP and SW adjacently, the wiring layout in the word decoder WDEC is prevented from being complicated. In particular, the wiring layout design of the sub word decoder 46a becomes easy.

In this embodiment, half of the memory cells MC formed in the memory core 34 are partial memory cells. In other words, data of half of the storage capacity of the pseudo SRAM is held during the data holding mode.

The complementary bit lines BL (BL0, BL1, ...) and / BL (/ BL0, / BL1, ...) are connected to the same sense amplifier SA and precharge circuit PRE. The bit lines BL and / BL are connected to the data bus line DB through the column switch CSW. The column switch CSW is turned on by the column select signals CL (CL0, CL1, ...) which decode the column address signal CAD. The sense amplifier SA and the precharge circuit PRE will be described in detail later with reference to FIG. 11.

FIG. 10 shows the quarter word decoder 59 shown in FIG. 9 in detail.

The quarter word decoder 44 includes a decoder 44a for decoding the row address signals X0, / X0, X1, / X1 to generate the decode signals X11, X10, X01, and X00, The mask circuit 44b which masks the row address signals X0 and / X0 when the mode signal MODE3 or the flag detection signal FDTC is at a high level and outputs a high level to the decoder 44a is provided.

FIG. 11 shows the sense amplifier SA and the precharge circuit PRE shown in FIG. 9 in detail.

The sense amplifier SA includes two CMOS inverters connected to each other by an input and an output; A pMOS transistor (pMOS switch) for connecting the source of the pMOS transistor of the CMOS inverter to the power supply line VDD; An nMOS transistor (nMOS switch) for connecting the source of the nMOS transistor of the CMOS inverter to the ground line VSS is provided. The inputs (or outputs) of the CMOS inverters are connected to the bit lines BL and / BL, respectively. The pMOS switch turns on when the sense amplifier activation signal PSA is at low level, and the nMOS switch turns on when the sense amplifier activation signal NSA is at high level. By turning on the pMOS switch and the nMOS switch, the CMOS inverter is activated to differentially amplify the voltage difference between the bit lines BL and / BL.

The precharge circuit PRE has an nMOS transistor for connecting the bit lines BL and / BL to each other and an nMOS transistor for connecting the bit lines BL and / BL to the precharge voltage line VPR, respectively. The nMOS transistor is turned on when the precharge signal PREZ is at a high level, and connects the bit lines BL and / BL to the precharge voltage line VPR.

FIG. 12 shows the operation of the sense amplifier control circuit 40 and the precharge control circuit 42 shown in FIG.

The sense amplifier control circuit 40 changes the sense amplifier activation signals PSA and NSA after the delay time DLY1 from the rising edge of the RASZ signal irrespective of the logic level of the mode signal MODE2 to sense amplifier SA. (A, Fig. 12, (b)). "ON" and "OFF" in the figure indicate activation and deactivation of the sense amplifier SA, respectively. The precharge control circuit 42 changes the precharge signal PREZ to a low level in synchronization with the rising edge of the RASZ signal irrespective of the logic level of the mode signal MODE2 to stop the precharge operation (FIG. 12). (C), (d)).

The sense amplifier control circuit 40 changes the sense amplifier activation signals PSA and NSA after the delay time DLY2 from the rising edge of the RASZ signal when the mode signal MODE2 is at the low level, thereby turning the sense amplifier SA on. Deactivate (FIG. 12 (e)). The precharge control circuit 42 changes the precharge signal PREZ to a high level after the delay time DLY2 from the rising edge of the RASZ signal when the mode signal MODE2 is at the low level, and starts the precharge operation. (FIG. 12 (f)).

The sense amplifier control circuit 40, when the mode signal MODE2 is at the high level, the sense amplifier activation signal PSA, after the delay time DLY2 from the rising edge of the RASZ signal after the low address signal X0 is changed to the high level. NSA) is changed to deactivate the sense amplifier SA (Fig. 12 (g)). The precharge control circuit 42 supplies the precharge signal PREZ after the delay time DLY2 from the rising edge of the RASZ signal after the row address signal X0 is changed to the high level when the mode signal MODE2 is at the high level. The precharge operation is started by changing to a high level (Fig. 12 (h)).

That is, during the shared refresh mode, in order to write the data held in the partial memory cell C00 to the partial memory cell and the adjacent shared memory cell C10, the sense amplifier SA outputs the RASZ signal twice. Is activated, and precharge of the bit lines BL and / BL is prohibited. More specifically, the data latched in the sense amplifier SA in synchronization with the refresh control signal REFZ outputted when the row address signal X0 is even is a refresh control output after the row address signal X0 is changed to an odd number. The operation corresponding to the signal REFZ is maintained.

FIG. 13 shows the details of the flag circuit 30, flag detection circuit 28 and main parts of the word decoder WDEC shown in FIG.

The flag circuit 30 has flags FAX (F0AX, F1AX, ...) and FBX (F0BX, F1BX, ...) for each of the main word lines MW0, MW1, .... In other words, the flags FAX and FBX are formed for each partial region PA.

The flags FAX and FBX consist of a latch circuit connecting the inputs and outputs of two inverters to each other. Each flag FAX, FBX is used when each memory cell of the corresponding partial area PA independently holds data at the time of switching from the data holding mode to the normal operation mode (first storage mode, single cell operation). When the memory cell of the corresponding partial area PA holds common data (second memory mode, twin cell operation), the memory cell of the corresponding partial area PA is reset to the high level.

More specifically, the flags FAX and FBX are set to a low level in synchronization with the pulse of the partial mode release signal PRER. That is, as described later, all the flags FAX and FBX are set when returning from the data holding mode to the normal operation mode. In other words, all the flags FAX and FBX are set before the switching operation of switching all the memory cells from the second memory mode to the first memory mode. The set flags FAX and FBX indicate that the single cell operation of the memory cell of the corresponding partial area PA is prohibited. For this reason, only the twin cell operation is permitted for the partial area PA corresponding to the set flags FAX and FBX. In this way, the flag circuit 30 operates as a flag set circuit.

The flags FAX and FBX are reset to a high level in synchronization with the flag reset signals FRAX and FRBX, respectively. That is, as will be described later, each of the flags FAX and FBX is reset during the first access of the corresponding partial area PA in the switching operation of switching all the memory cells from the second storage mode to the first storage mode. .

 In addition, the flag circuit 30 changes the flag output signal S1AX to a low level in synchronization with the decode signals XDX (XD0X, XD1X, ...) when the flag FAX is set at the low level. The flag circuit 30 changes the flag output signal S1BX to the low level in synchronization with the decode signals XDX (XD0X, XD1X, ...) when the flag FBX is set at the low level.

The flag detecting circuit 28 includes a latch circuit connected to the flag output signals S1AX and S1BX, respectively, and one of the flag output signals S1AX and S1BX in accordance with the lower bit X1 of the row address signal according to the node ND6. The multiplexer MUX1, the delay circuit DELAY1, and the mask circuit MSK to be outputted to the circuit are provided. The delay circuit DELAY1 delays only the rising edge of the low activation signal RASZ by a predetermined period. The mask circuit MSK outputs the flag output signal S1AX or S1BX selected by the multiplexer MUX1 as the flag detection signal FDTC. The mask circuit MSK has a function of shortening the activation period of the flag detection signal FDTC when a write command is supplied. The flag detection circuit 28 outputs a flag detection signal FDTC when it detects that the flag FAX or FBX is set during the access of the pseudo SRAM.

 Fig. 14 shows the operation of the flag circuit 30 and the flag detection circuit 28 in the normal operation mode after the partial refresh mode. This example shows when the flag FA0X of the flag circuit 30 is set at the low level in the write operation in response to the write command. In addition, by the address signal corresponding to the write command, the lower-order second decode signal X1 is changed to low level.

First, the low activation signal RASZ is output in synchronization with the write control signal WRZ in response to the write command (Fig. 14 (a)), so that the decode signal XD0X corresponding to the row address signal RAD2 is at a low level. (Fig. 14 (b)). The flag circuit 30 shown in Fig. 13 outputs a low level flag output signal S1AX in accordance with the reset flag FA0X (Fig. 14 (c)).

The multiplexer MUX1 of the flag detection circuit 28 outputs the flag output signal S1AX to the roadway ND6 (Fig. 14 (d)). The flag detection circuit 28 activates the flag detection signal FDTC to a high level in synchronization with the falling edge of the flag output signal S1AX (Fig. 14 (e)).

The delay circuit DELAY1 of the flag detection circuit 28 changes the node ND7 to a high level after a predetermined time from the rising edge of the RASZ signal (Fig. 14 (f)). Since the node ND8 has a high level of the WRZ signal, the node ND8 changes to a high level in synchronization with the level change of the node ND7 (Fig. 14 (g)). The NOR gate of the mask circuit MSK masks the voltage of the level of the node ND6 by the high level of the node ND8. For this reason, the flag detection signal FDTC is deactivated despite the activation period of S1AX (Fig. 14 (h)).

Thereafter, the node ND8 changes to low level in synchronization with the deactivation of the WRZ signal (Fig. 14 (i)). In synchronization with the deactivation of the RASZ signal, the XD0X signal, the S1AX signal, and the nodes ND6 and ND7 return to their original levels.

FIG. 15 shows other operations of the flag circuit 30 and the flag detection circuit 28 in the normal operation mode after the partial refresh mode. Detailed description of the same operation as that of FIG. 14 will be omitted. This example shows a case where the flag FA0X of the flag circuit 30 is reset to a high level in a write operation in response to a write command. In addition, by the address signal corresponding to the write command, the decode signal X1 of the second to second bits is changed to the low level.

After the flag FA0X is reset to the high level ("H"), the NOR gate of the flag circuit 30 maintains the high level. For this reason, the flag output signal S1AX maintains the level regardless of the activation of the decode signal XD0X (Fig. 15 (a)). The high node ND6 is maintained at a high level by the flag output signal S1AX of the level. Therefore, the flag detection signal FDTC is not output (Fig. 15 (b)).

Fig. 16 shows other operations of the flag circuit 30 and the flag detection circuit 28 in the normal operation mode after the partial refresh mode. Detailed description of the same operation as that of FIG. 14 will be omitted. This example shows a case where the flag FA0X of the flag circuit 30 is set at a low level in a read operation in response to a read command or a refresh operation in response to a refresh request generated in the pseudo SRAM. The decoded signal X1 of the second to second bits is changed to the low level by the address signal or the refresh address signal corresponding to the read command.

First, the row activation signal RASZ is output in synchronization with the write control signal WRZ in response to the read command or the refresh control signal REFZ in response to the refresh request (FIG. 16 (a)), and the write control signal WRZ. ) Is not activated (Fig. 16 (b)). For this reason, the node ND8 maintains a low level (Fig. 16 (c)), and the mask circuit MSK does not function. Therefore, the flag detection signal FDTC is activated for a period corresponding to the high level period of the RASZ signal (Fig. 16 (d)).

17 shows other operations of the flag circuit 30 and the flag detection circuit 28 in the normal operation mode after partial refresh. Detailed descriptions of the same operations as those of FIGS. 14 and 15 will be omitted. This example shows a case where the flag FA0X of the flag circuit 30 is reset to a high level in a read operation in response to a read command or a refresh operation in response to a refresh request occurring inside the pseudo SRAM. The decoded signal X1 of the second to second bits is changed to the low level by the address signal or the refresh address signal corresponding to the read command.

After the flag FA0X is reset to the high level ("H"), the NOR gate of the flag circuit 30 maintains the high level. For this reason, the flag detection signal FDTC is not output like FIG.

18 shows the flag reset circuit 26 shown in FIG. 1 in detail.

The flag reset circuit 26 has a pulse generation circuit 26a, a delay circuit DELAY2 and a multiplexer MUX2. The pulse generation circuit 26a generates a low level pulse in synchronization with the rising edge of the flag detection signal FDTC. The delay circuit DELAY2 delays a low level pulse for a predetermined time and outputs it to the node ND9. The multiplexer MUX2 outputs the pulse of the node ND9 as the flag reset signal FRAX when the decode signal X1 is at the low level, and flags the pulse of the node ND9 when the decode signal X1 is at the high level. Output as a reset signal FRBX.

FIG. 19 shows the operation of the flag reset circuit 26 shown in FIG. This example shows the normal operation mode immediately after the partial refresh.

The flag detection signal FDTC is generated when the flag FA1X (or FB1X) is set, as shown in Figs. 14 to 17, and is not generated when the flag FA1X (or FBX) is reset. . All the flags FAX and FBX are set to the low level after the partial refresh in synchronization with the partial mode release signal PREF. For this reason, in each partial area PA, the flag detection signal FDTC is output in synchronization with the first access RDZ, WRZ, REFZ after partial refresh (FIG. 19 (a)).

The flag reset circuit 26 outputs a flag reset signal FRAX or FRBX in synchronization with the flag detection signal FDTC (Figs. 19 (b) and (c)). The output of the flag reset signal FRAX or FRBX is determined in accordance with the level of the decode signal X1. In FIG. 19, an example is shown in which the partial access is performed to the memory cell C00, and the next access is performed to the memory cell C01.

On the other hand, in synchronization with the pulse of the flag reset signal FRAX or FRBX, the flag (FAX (FA0X, FA1X, ...) or FBX (FB0X, FB1X, ...) corresponding to the decode signal XDX (XD0X, XD1X, ...) ) Is reset to the high level.

20 shows the operation in the normal operation mode in the first embodiment.

As a command CMD for operating the pseudo SRAM during the normal operation mode, there are an access command (read command and write command) supplied through an external terminal and a refresh command (REFZ signal) from the refresh command generation circuit 16.

For example, the partial memory cell C00 is accessed by the first command CMD, and the shared memory cell C10 is accessed by the next command CMD. The word lines SW0P and SW1 are independently selected in accordance with the row address signal RAD2. That is, in the normal operation mode, one bit of data is stored for each memory cell connected to one word line (first memory mode, single cell operation).

When the command CMD is a read command, the data amplified on the bit lines BL and / BL is output to the outside via the data bus DB. When the command CMD is a write command, the data supplied through the external terminal is amplified by the write amplifier WA and the sense amplifier SA, and rewritten in the memory cell. When the command CMD is a refresh command, the data amplified by the sense amplifier SA is rewritten to the memory cell.

Fig. 21 shows the operation during the shared refresh mode (= data holding mode, low power consumption mode) in the first embodiment. In the shared refresh mode, reception of an access command from the outside is prohibited. The pseudo SRAM operates only in response to the refresh command REF occurring internally.

In the shared refresh mode, first, the partial memory cell C00 is accessed, and data held in the partial memory cell C00 is latched in the sense amplifier SA (Fig. 21 (a)). Next, with the sense amplifier SA activated, the shared memory cell C10 is accessed, and the data (complementary data) latched in the sense amplifier SA causes the partial memory cell C00 and the shared memory. It is recorded in the cell C10 (Fig. 21 (b)). Accordingly, complementary data is held in the partial memory cell C00 and the shared memory cell C10. The above operation is performed for all partial regions PA (memory cell groups). That is, one bit of data is stored in a plurality of memory cells (for example, C00, C10) in a memory cell group connected to two word lines SW0P and SW1 (second storage mode, twin cell operation).

Fig. 22 shows the operation during the partial refresh mode (data holding mode, low power consumption mode) in the first embodiment. In the partial refresh mode, the reception of an access command from the outside is prohibited, similarly to the shared refresh mode. The pseudo SRAM operates only in response to the refresh command REF occurring internally.

In the partial refresh mode, the partial word line SW0P and the shared word line SW1 are simultaneously selected, and complementary data held in the partial memory cell C00 and the shared memory cell C10 is sense amplifier SA. Are simultaneously amplified and rewritten into cells C00 and C10 (twin cell operation). That is, one bit of data is stored in a plurality of memory cells (for example, C00, C10) in a memory cell group connected to two word lines SW0P and SW1 (second storage mode). By holding data in the partial memory cell C00 and the shared memory cell C10, the refresh interval can be significantly extended.

In the partial refresh mode, as the refresh interval is extended, the amount of charge held in one memory cell immediately before the refresh operation is smaller than during the normal operation mode. For this reason, in the normal operation mode after the partial refresh mode, there is a possibility that the data of the memory cells that have elapsed in the refresh operation cannot be read correctly (data destruction). In the present invention, as shown in Figs. 24 to 26, which will be described later, data destruction is prevented by studying the first access of each memory cell in the normal operation mode after the partial refresh mode.

FIG. 23 shows that in the normal operation mode after the partial refresh mode in the first embodiment, before all the flags FAX and FBX are reset, the CE signal is changed to the low level, and the data holding mode (low consumption) is resumed in the normal operation mode. The operation in the case of shifting to the power mode) is shown.

The flag detection circuit 28 shown in FIG. 13 outputs the flag detection signal FDTC when detecting the set state of the flags FAX and FBX, regardless of the operation mode. For this reason, also in the shared refresh mode, the flag detection signal FDTC is output (FIG. 23 (a)).

By activating the flag detection signal FDTC, the word decoder WDEC simultaneously selects the sub word line pairs SW0P and SW1 corresponding to the partial area PA as shown in Fig. 22 (Fig. 23 (b)). . The flag reset circuit shown in Fig. 18 outputs the flag reset signal FRAX in response to the flag detection signal FDTC, and resets the flag F0AX to a high level (Fig. 23 (c)).

For the refresh operation in the shared refresh mode, while the sense amplifier SA is active, the sub word line SW1 is reselected so that data latched in the sense amplifier SA is written to the memory cell C10. (FIG. 23 (d)). This operation is redundant and unnecessary. However, there is no problem in operation, and since the circuit can be prevented from being complicated, redundant operation is recognized.

24 to 26 show the operation in the normal operation mode after the low power consumption mode is released. The amount of charge held in each memory cell of the memory cell pair refreshed by the twin cell operation during the low power consumption mode may not be sufficient for the single cell operation. For this reason, when returning from the low power consumption mode to the normal operation mode (when switching the operation mode), it is necessary to operate all the partial memory cells once and compensate for the amount of charge held in the memory cell capacitor.

Prior to the present invention, a switching period for all twin memory cells to operate once is required. For this reason, the external system has not been able to access the pseudo SRAM in the meantime. In the present invention, after switching the operation mode, the first accessed memory cell for each partial area PA is operated using the flags FAX and FBX, so that the switching period is unnecessary. For this reason, the external system can read and write access to the pseudo SRAM immediately after returning to the normal operation mode without recognizing the twin cell operation. The solution will be described below.

Fig. 24 shows an example in which the refresh requests REF occur sequentially after returning to the normal operation mode.

First, the command decoder 10 shown in FIG. 1 receives the release command PEXIT in the data holding mode (low power consumption mode) from the outside of the pseudo SRAM, and outputs a partial mode release signal PRER (Fig. 24 (a). )). By outputting the partial mode release signal PRER, the pseudo SRAM returns from the low power consumption mode to the normal operation mode. The flag circuit 30 shown in FIG. 13 sets the flags FAX (F0AX, F1AX, ...) and FBX (F0BX, F1BX, ...) to a low level in synchronization with the pulse of the partial mode release signal PREF. (Figure 24 (b)).

Next, a refresh command REF (REFZ signal) is generated in the pseudo SRAM, and the timing control circuit 38 shown in FIG. 1 outputs the RASZ signal (FIG. 24 (c)). At this time, the refresh address counter 18 outputs the refresh address signal REFAD for selecting the memory cell C00. Specifically, the lower two bits X1 and X0 of the row address signal are together at the low level (Fig. 24 (d)). The word decoder WDEC shown in Fig. 13 outputs the decode signal XD0X and the main word line signal MW0 corresponding to the memory cell C00 in response to the RASZ signal (Fig. 24 (e, f)).

The flag circuit 30 outputs the contents of the flags F0AX and F0BX as flag output signals S1AX and S1BX in synchronization with the decode signal XD0X (Fig. 24 (g)). The flag detection circuit 28 selects the flag output signal S1AX in accordance with the bit X1 of the row address signal and outputs it as the flag detection signal FDTC (Fig. 24 (h)). The quarter word decoder 44 shown in Fig. 9 receives the flag detection signal FDTC and changes the two-bit decode signals X00 and X01 to a high level. Then, the sub word lines SW0P and SW1 of two lines are selected at the same time (Fig. 24 (i)), and the twin cell refresh operation for the memory cells C00 and C10 is executed (Fig. 24 (j)). The data is rewritten to the memory cells C00 and C10 that have read common data. For this reason, the data held in the memory cell C00 during the low power consumption mode is prevented from being lost. "ON" and "OFF" of the sense amplifier activation signals PSA and NSA indicate activation and deactivation of the sense amplifier SA, respectively.

On the other hand, the internal refresh cycle time IREF, which is the operation time of the memory core 34 in the refresh operation, is set equal to the internal refresh cycle time IREF in the normal operation mode.

The flag reset circuit 26 shown in Fig. 18 outputs the flag reset signal FRAX corresponding to the bit X1 in synchronization with the flag detection signal FDTC (Fig. 24 (k)). The flag circuit 30 shown in Fig. 13 resets the flag F0AX corresponding to the decode signal XD0X to a high level in response to the flag reset signal FRAX (Fig. 24 (l)). By resetting the flag F0AX, the memory cells of the corresponding partial area PA are subsequently accessed in the first storage mode (single cell operation).

By deactivating the RASZ signal, the decode signal XD0X is deactivated, and the flag output signals S1AX and S1BX are precharged to a high level (Figs. 24 (m) and (n)). By the precharge of the flag output signals S1AX and S1BX, the flag detection signal FDTC is deactivated to a low level (Fig. 24 (o)). By deactivation of the flag detection signal FDTC, the main word line MW0 and the sub word lines SW0P and SW1 become unselected (Fig. 24 (p)).

Next, a refresh command REF (REFZ signal) is generated (Fig. 24 (q)). The refresh address counter 18 is incremented to output the refresh address signal REFAD for selecting the memory cell C10. For this reason, the bit X0 of the row address signal is changed to the high level (Fig. 24 (r)).

The flag FA0X corresponding to the memory cell C10 is reset to the high level in the previous refresh operation. For this reason, when the decode signal XD0X is activated, the flag circuit 30 changes only the flag output signal S1BX to a low level, so that the flag output signal S1AX remains at a high level (Fig. 24 (s)). ). Since the flag output signal S1AX corresponding to the refresh address X1 = " 0 " is at a high level, the flag detection signal FDTC is not output (Fig. 24 (t)). For this reason, only the sub word line SW1 of one line is selected, and the normal refresh operation (single cell operation) by a 1st storage mode is performed. On the other hand, the data of the memory cell C10 is not compensated during the low power consumption mode. For this reason, only in the example of FIG. 24, the data held by this refresh operation does not have a special meaning.

The refresh cycle time IREF of the single cell refresh operation is set equal to the refresh cycle time IREF of the twin cell refresh operation. By setting the refresh cycle time IREF to the same length, the configuration of the timing control circuit 38 of the core control circuit 32 can be simplified.

Next, the refresh command REF (REFZ signal) is generated (Fig. 24 (u)). The refresh address counter 18 is incremented to output the refresh address signal REFAD for selecting the memory cell C20. For this reason, the bit X1 of the row address signal is changed to the high level (Fig. 24 (v)).

The flag FB0X is set at the low level. For this reason, as described above, the flag output signal SlBX changes to the low level (Fig. 24 (w)). The flag detection circuit 28 selects the flag output signal S1BX in accordance with the bit X1 of the row address signal and outputs it as the flag detection signal FDTC (Fig. 24 (x)). Then, the sub word lines SW2P and SW3 of two lines are selected at the same time, and the twin cell refresh operation for the memory cells C00 and C10 is executed (Fig. 24 (y)). Thereafter, in synchronization with the flag detection signal FDTC, the flag reset signal FRBX is output, and the flag F0AX is reset to a high level ((z1, z2) in FIG. 24).

Fig. 25 shows an example in which the read command RD is supplied before the first refresh request REF after returning to the normal operation mode. Corresponding to the read command RD, the operations until the data on the bit lines BL and / BL are amplified (Figs. 25 (a) to 25 (p)) are the same as in Fig. 24 described above. Attaching.

After the data held in the memory cells C00 and C10 is amplified by the sense amplifier SA by the twin cell operation, the column decoder CDEC shown in FIG. 1 decodes the column address signal CAD. The column select signal CL0 corresponding to the memory cell C00 shown in Fig. 9 is activated for a predetermined period (Fig. 25 (q)). The column select signal CL0 turns on the corresponding column switch CSW, and the complementary bit lines BL and / BL are selectively connected to the data bus line DB. The data held in the memory cell C00 is amplified by the sense buffer SB and then output from the data input / output terminal DQ via the common data bus line CDB (Fig. 25 (r)).

The operating time of the memory core 34 in the read operation is represented by the internal read cycle time IRD. The internal read cycle time (IRD) is the same in the data hold mode and normal operation mode. Further, the internal read cycle time IRD is the internal refresh cycle time IREF, which is the operation time of the memory core 34 in the refresh operation, and the internal write cycle time, which is the operation time of the memory core 34 in the write operation. It is the same as (IWR1) (FIG. 28 to be described later). The internal write cycle time IWR1 is a write operation time that does not accompany the twin cell operation and is the same in the data retention mode and the normal operation mode. The write operation time involving the twin cell operation is represented by the internal write cycle time IWR2 (Fig. 26 to be described later).

After the read command RD, the refresh command REF corresponding to the memory cell C00 is generated (Fig. 25 (s)). The flag F0AX is reset to the high level by the twin cell operation corresponding to the read operation. For this reason, the single cell operation by a 1st storage mode is performed similarly to FIG. 24 (q)-(t) (FIG. 25 (t)). Similarly, the refresh operation corresponding to the memory cell C10 also becomes a single cell operation (Fig. 25 (u)).

Fig. 26 shows an example in which the write command WR is supplied before the first refresh request REF after returning to the normal operation mode. In other words, Fig. 26 shows a write operation in the partial area PA corresponding to the set flags flags FAX (F0AX, FAX, ...) and FBX (F0BX, F1BX, ...).

When the flags FAX and FBX are set, the write operation is executed with the internal write cycle time IWR2. In the internal write cycle time IWR2, the activation period of the RASZ signal is set longer than the internal write cycle time IWR1 (Fig. 26 (a)). Corresponding to the activation period of the RASZ signal, the output periods of the decode signal XD0X and the flag output signals S1AX and S1BX also increase (Figs. 26 (b) and (c)).

The internal write cycle time IWR2 includes one refresh cycle and one write cycle, as shown below. The sense amplifier SA continues to activate during the refresh cycle and the write cycle. For this reason, the activation frequency of the sense amplifier can be lowered, and the internal write cycle time IWR2 can be made shorter than the sum of the refresh cycle time IREF and the write cycle time IWR1. For example, the internal write cycle time IWR2 can be 1.5 to 1.7 times the write cycle time IWR1.

Flag output signals S1AX and S1BX are outputted by the decode signal XD0X (Fig. 26 (d)) to activate the flag detection signal FDTC (Fig. 26 (e)), and the flag detection signal FDTC In response to the activation of), the flag reset signal FRAX is outputted (Fig. 26 (f)), and the operation of resetting the flag FA0X (Fig. 26 (g)) is the same as in Fig. 24 described above. Further, by activation of the flag detection signal FDTC, the sub word lines SW0P and SW1 are simultaneously activated (Fig. 26 (h)), and the twin cell operation is started (Fig. 26 (i)). The data is rewritten to the memory cells C00 and C10 that have read common data.

The flag detection circuit 28 shown in FIG. 13 changes the node ND8 to a high level after the delay time of the delay circuit DELAY1 from the activation of the RASZ signal, thereby converting the flag detection signal FDTC into the flag output signal S1AX. Regardless, it is deactivated (Fig. 26 (j)). The quarter word decoder 44 shown in Fig. 10 makes the decode signal X00 non-selective in response to the deactivation of the flag detection signal FDTC. For this reason, the sub word line SW0P (X0 = " 0 ") is unselected (Fig. 26 (k)). As a result, the twin cell operation is terminated, and only the sub word line SW1 (X0 = " 1 ") is continuously selected (Fig. 26 (l)). In this manner, the 1/4 word decoder 44 disconnects the sub word line SW0P connected to the memory cell C00 to which the writing in the partial area PA is not instructed during the activation of the sense amplifier SA. It operates as a word control circuit to be unselected. The sense amplifier SA continues to be activated during the period during which the sub word line SW1 is selected.

Thereafter, the write data DT is supplied to the bit lines BL and / BL through the data bus line DB, and data is written only to the memory cell C10 connected to the selected sub word line SW1. (FIG. 26 (m)). That is, the write operation is performed in response to the write command WR, and new data is written to the memory cell C10 in which writing is instructed. On the other hand, the write data DT is supplied to the data input / output terminal DQ in synchronization with the write command WR (Fig. 26 (n)).

In this manner, after the data held in the memory cell C00 is refreshed by the twin cell operation, the data is written to the memory cell C10 so that the data of the memory cell C00 is normally lost in the low power consumption mode. You can go directly to the operating mode. Thereafter, as shown in FIG. 25, single cell refresh operations corresponding to the memory cells C00 and C10 are sequentially executed ((o) and (p) of FIG. 26).

27 to 29 show a solution for executing the refresh operation without the external system recognizing in the normal operation mode. By this solution, the pseudo SRAM having the memory core of the DRAM operates as the SRAM.

Fig. 27 shows the relationship between the external command cycle time EXTC and the internal read cycle time IRD.

The external command cycle time EXTC is a supply interval of an operation command (read command RD in this example) supplied from the outside of the pseudo SRAM. In this embodiment, the external command cycle time EXTC is set to a value obtained by adding the internal refresh cycle time IRF to the internal read cycle time IRD (or the write cycle time IWR1). For this reason, even if the read command RD is continuously supplied at the minimum cycle time, the internal refresh cycle time IREF can always be inserted between the internal read cycle times IRD.

Fig. 28 shows the relationship between the external command cycle time EXTC and the internal write cycle time IWR1.

Since the internal write cycle time IWR1 is equal to the internal read cycle time IRD, the external command cycle time EXTC is set to the value obtained by adding the internal refresh cycle time IREF1 to the internal write cycle time IWR1. For this reason, even if the write command WR is supplied continuously in minimum cycles, the internal refresh cycle IREF can be inserted between the internal write cycles IWR1.

Fig. 29 shows the relationship between the external command cycle time EXTC and the internal write cycle time IWR2.

The external command cycle time EXTC is set shorter than the internal write cycle time IWR2 plus the internal refresh cycle time IREF. As described in Fig. 26, the internal write cycle time IWR2 accompanied by the twin cell refresh operation is longer than the internal write cycle time IWR1. For this reason, when the internal refresh cycle IREF is inserted between the write commands WR continuously supplied in the minimum cycle, the internal write cycle IWR2 is temporarily delayed. However, while the internal write cycle IWR2 is executed several cycles, the deviation with respect to the write command WR is eliminated. As a result, even when the internal write cycle IWR2 accompanying the twin cell operation occurs continuously, the refresh operation can be executed without being recognized by the external system.

30 shows the operation of the pseudo SRAM of the first embodiment. The timing diagram at the bottom of the figure shows the continuation of the timing diagram at the top of the figure.

In the normal operation mode, the sub word line SW of one line is selected in response to the refresh control signal REFZ (single cell operation). When the CE signal changes to the low level and transitions from the normal operation mode to the shared refresh mode, the reset circuit of the refresh address counter 18 shown in Fig. 33 is selected in order to first select the partial word line SWP. 54a resets the counter 54b which generates the least significant bit X0 of the row address signal RAD2 in synchronization with the rising edge of the mode signal MODE2.

After all partial word lines (SWPs) are selected, the operation mode shifts from the shared refresh mode to the partial refresh mode. In the partial refresh mode, a twin cell operation (refresh operation) for selecting two adjacent sub word lines SW with one refresh control signal REFZ is performed.

 If the CE signal changes to a high level during the partial refresh mode, the operation mode shifts directly to the normal operation mode. After switching to the normal operation mode, the twin cell operation or the single cell operation is executed according to the flags FAX and FBX.

As described above, in the present embodiment, the data holding time can be made longer than the first storage mode by holding the data in a plurality of memory cells in the second storage mode in which the so-called partial technology and the twin cell technology are fused during the data holding mode. have. As a result, the refresh frequency of the memory cells can be greatly reduced, and the power consumption in the data holding mode can be significantly reduced.

Flags FAX and FBX indicating the memory modes of the memory cells are formed for each partial area PA, and the first access is always performed in the second storage mode for each partial area PA. For this reason, the data of the memory cell to be accessed can be prevented from being lost.

Flags FAX and FBX indicative of the memory mode of the memory cells are formed for each partial area PA, and the memory cells are moved in the mode corresponding to the flags FAX and FBX at the time of switching from the data retention mode to the normal operation mode. Access. For this reason, the system managing the pseudo SRAM can freely access the memory cells even during the switching operation. The actual switch time is zero. As a result, the system managing the pseudo SRAM can access the pseudo SRAM immediately after returning from the data holding mode to the normal operation mode. For example, when the pseudo SRAM is used as the work memory of the cellular phone, it can immediately return to the operation mode from the standby state.

The flag circuit 30 sets all the flags FAX and FBX immediately before the switching operation from the data holding mode to the normal operation mode. For this reason, the memory cells of all the partial regions PA can be reliably shifted from the second storage mode to the first storage mode.

By detecting the states of the flags FAX and FBX by the flag detecting circuit 28, it is possible to easily control the operation of the quarter word decoder 44 of the word decoder WDEC, thereby simplifying the circuit configuration. Can be.

When the first access after returning to the normal operation mode is a write operation, refresh is performed in the twin cell operation, and then data is recorded in the single cell operation. For this reason, data of the memory cell in which writing in the partial area PA is not performed can be reliably held, and data can be reliably written in a predetermined memory cell. The external system can execute the write operation on the pseudo SRAM immediately after returning to the normal operation mode. That is, the system can operate at high speed.

When the first access after returning to the normal operation mode is the write operation, the sense amplifier SA is continuously activated to execute the twin cell refresh operation and the single cell write operation. For this reason, the activation frequency of the sense amplifier SA can be reduced, and the internal write cycle time IWR2 can be shortened.

In the first write operation after returning to the normal operation mode, the word amplifier connected to the memory cell to which no write is instructed is made non-selective while the sense amplifier SA is continuously activated. For this reason, while activating the sense amplifier SA, the twin cell operation (operation for rewriting data in the second storage mode) and the single cell operation (operation for recording data in the first storage mode) are executed with simple control. Can be.

When the first access after the return to the normal operation mode is the read operation, the refresh operation is performed in the twin cell operation, and the amplified read data is output to the data input / output terminal DQ. For this reason, the external system can perform a read operation on the pseudo SRAM immediately after returning to the normal operation mode. That is, the system can operate at high speed.

When the first access after returning to the normal operation mode is the refresh operation, the refresh is performed in the twin cell operation. By the data rewrite refresh operation, data is strongly written to each memory cell that has been refreshed. Therefore, after that, even when each memory cell is operated in a single cell (access in the first storage mode), it is possible to reliably read or refresh data.

In the transition from the normal operation mode to the data retention mode, the data stored in the partial memory cell is read out for each refresh command until all partial areas PA are in the second storage mode state, and the read data is partial. The shared refresh operation for writing to all memory cells in the area PA is executed. By the shared refresh operation, data stored in the first memory mode in the partial memory cells can be stored in the second memory mode in each memory cell of the memory cell group. By changing the memory cells in the first storage mode to the second storage mode for each refresh operation, it is possible to efficiently switch from the normal operation mode to the data retention mode.

Fig. 31 shows a second embodiment of the semiconductor memory of the present invention. The same code | symbol is attached | subjected about the element same as the element demonstrated in 1st Embodiment, and detailed description is abbreviate | omitted about these.

In this embodiment, the refresh timer 14, the refresh command generation circuit 16, the refresh address counter 18, the flag reset circuit 26, the flag detection circuit 28, and the flag circuit 30 of the first embodiment. Instead of the core control circuit 32 and the memory core 34, the refresh timer 14A, the refresh command generation circuit 16A, the refresh address counter 18A, the flag reset circuit 26A, and the flag detection circuit 28A The flag circuit 30A, the core control circuit 32A, and the memory core 34A are formed. The sense amplifier control circuit 40A and the precharge control circuit 42A of the core control circuit 32A receive the lower two bits X1 and X0 of the row address signal RAD output from the multiplexer 24. The rest of the configuration is almost the same as in the first embodiment.

FIG. 32 shows the refresh timer 14A shown in FIG. 31 in detail.

The dividers 14b, 14c, and 14f of the refresh timer 14 convert the frequency of the OSC0 signal into one eighth, sixteenth, and one sixth and sixteenth respectively.

33 shows the operation of the refresh timer 14A and the refresh command generation circuit 16A.

The refresh timer 14A outputs the oscillation signals OSC1, OSC2, and OSC3 as the refresh request signal TREF when the mode signals MODE1, MODE2, and MODE3 are at high levels, respectively. The refresh command generation circuit 16A outputs the refresh request signal TREF as the refresh control signal REFZ when the mode signals MODE1 and MODE3 are each at a high level. The refresh command generation circuit 16A outputs the refresh control signal REFZ four times in synchronization with the refresh request signal TREF when the mode signal MODE2 is at a high level.

34 shows details of the refresh address counter 18A shown in FIG.

The refresh address counter 18A has a logic gate for controlling the reset circuit 18a, the counters 18d and 18e, and the counters 18d and 18e. The counter 18d counts in synchronization with the refresh control signal REFZ to generate the lower two bits R1 and R0 of the refresh address signal REFAD. The counter 18d is reset in synchronization with the rising edge of the mode signal MODE2 and when the mode signal MODE3 is at the high level.

The counter 18e counts in synchronization with the refresh control signal REFZ when the mode signal MODE3 is at a high level, and updates the upper four bits R5-2 of the refresh address signal REFAD. The counter 18e is applied to the address signal R1 output from the counter 18d when the mode signals MODE1 and MODE2 are at a high level (except for a predetermined period after the rising edge of the mode signal MODE2). A synchronous count operation is performed to update the bit R5-2.

FIG. 35 shows the operation of the refresh address counter 18A shown in FIG.

The refresh address counter 18A sequentially counts up the 6-bit refresh address signal R5-0 in synchronization with the refresh control signal REFZ when the mode signals MODE1 and 2 are at the high level. The refresh address counter 18A sequentially counts up the 4-bit refresh address signal R5-2 in synchronization with the refresh control signal REFZ when the mode signal MODE3 is at a high level. At this time, the refresh address signals R1 and R0 are fixed at the low level.

36 shows details of main parts of the memory core 34A shown in FIG.

The word decoder WDEC of the memory core 34A has a quarter word decoder 44A and a plurality of sub word decoders 46a corresponding to the main word lines MW0, MW1, ..., respectively. . The 1/4 word decoder 44A decodes the signal according to the lower two bits (X1, X0) of the row address signal MD2 and its inverted bits (/ X1, / X0) when the mode signal MODE3 is at the low level. Outputs any one of (X11, X10, X01, X00). The 1/4 word decoder 44A sets all of the decode signals X11, X10, X01, and X00 to a high level when the mode signal MODE3 is at a high level.

In this embodiment, the partial region PA is formed by memory cells C00, C10, C20, C30, ... connected to four adjacent sub word lines (e.g., SW0P, SW1, SW2, SW3). have. For example, the sub word line SWP0 is a partial word line connected to the partial memory cell C00 in which data is held during the data holding mode. The sub word lines SW1, SW2, and SW3 are shared word lines connected to shared memory cells C10, C20, and C30 in which data is not held during the data holding mode.

The partial memory cell C00 and the shared memory cell C20 are connected to the bit line BL0, and the shared memory cells C10 and C30 are connected to the bit line / BL0. The partial word line SWP0 and the shared word lines SW1, SW2, and SW3 are selected in synchronization with each other during the data retention mode so that four memory cells are accessed simultaneously (second memory mode, quad cell operation). The data held in the partial memory cell C00 during the normal operation mode is held by the four memory cells C00, C10, C20, and C30 during the data retention mode.

In this embodiment, one quarter of the memory cells MC formed in the memory core 34A are partial memory cells. In other words, data of one quarter of the storage capacity of the pseudo SRAM is held during the data holding mode.

FIG. 37 shows the quarter word decoder 44A shown in FIG. 36 in detail.

The 1/4 word decoder 44A is a decoder 44a for decoding the row address signals X0, / X0, X1, / X1 to generate the decode signals X11, X10, X01, and X00, and the mode signal ( The mask circuit 44c which masks the row address signals X0, / X0, X1 and / X1 when the mode 3 or the flag detection signal FDTC is at the high level and outputs the high level to the decoder 44a is provided. .

FIG. 38 shows the operation of the sense amplifier control circuit 40A and the precharge control circuit 42A shown in FIG. The operation when the mode signal MODE2 is at the low level and the operation when the mode signal MODE2 is changed to the high level are the same as in the first embodiment (Fig. 12).

The sense amplifier control circuit 40A has a sense amplifier activation signal after a delay time DLY2 from the rising edge of the RASZ signal after the row address signals X1 and X0 are both changed to the high level when the mode signal MODE2 is at the high level. (PSA, NSA) is changed to deactivate the sense amplifier SA (Fig. 38 (a)). When the mode signal MODE2 is at the high level, the precharge control circuit 42A receives the precharge signal after the delay time DLY2 from the rising edge of the RASZ signal after the row address signals X1 and X0 are changed to the high level together. PREZ) is changed to the high level to start the precharge operation (Fig. 38 (b)).

That is, during the shared refresh mode, while the RASZ signal is output four times to write data held in the partial memory cell C00 to the partial memory cell and the adjacent shared memory cells C10, C20, and C30, the sense is sensed. The amplifier SA is activated, and precharging of the bit lines BL and / BL is prohibited.

39 shows details of the flag circuit 30A, the flag detection circuit 28A, and main parts of the word decoder WDEC shown in FIG. The word decoder WDEC is the same as in the first embodiment (Fig. 13).

The flag circuit 30A is formed for each of the main word lines MW0, MW1, .... The flag circuit 30A has the same flag FAX (F0AX, F1AX, ...) as the flag circuit 30 of the first embodiment. The function of the flag FAX is the same as that of the first embodiment. That is, the flag FAX is set to a low level in synchronization with the pulse of the partial mode release signal PRER, and is reset to a high level in synchronization with the flag reset signal FRAX, respectively. The state of the flag FAX is output as the flag output signal S1AX in synchronization with the decode signals XDX (XD0X, XD1X, ...).

The flag detection circuit 28A has a latch circuit connected to the flag output signal S1AX, a delay circuit DELAY1, and a mask circuit MSK. The mask circuit MSK outputs the flag output signal S1AX as the flag detection signal FDTC, and has a function of shortening the activation period of the flag detection signal FDTC when a write command is supplied.

Since the operation of the flag circuit 30A and the flag detection circuit 28A is the same as the operation corresponding to the flag F0AX of the first embodiment, description thereof is omitted.

40 shows the flag reset circuit 26A shown in FIG. 31 in detail.

The flag reset circuit 26A has a buffer circuit 26b instead of the multiplexer MUX2 of the flag reset circuit 26 (FIG. 18) in the first embodiment. The rest of the configuration is the same as the flag reset circuit 26. The flag reset circuit 26A outputs the flag reset signal FRAX after a predetermined time from the rising edge of the flag detection signal FDTC.

Fig. 41 shows the operation during the normal operation mode in the second embodiment.

In the normal operation mode, like the seventh embodiment (Fig. 20), the word lines SW0P, SW1, SW3, and SW4 are independently selected in accordance with the row address signal RAD2. Then, in response to a read command or a write command from the outside, a read operation or a write operation is executed. The refresh operation is executed in response to the refresh command generated inside the pseudo SRAM.

Fig. 42 shows the operation during the shared refresh mode in the second embodiment.

In the shared refresh mode, first, data held in the partial memory cell C00 is latched in the sense amplifier SA (Fig. 42 (a)). Next, while the sense amplifier SA is activated, the shared memory cells C10, C20, and C30 are sequentially accessed, and the data (complementary data) latched in the sense amplifier SA is stored in these memory cells ( C10, C20, C30) (FIG. 42 (b), (c), (d)). Accordingly, complementary data is held in the partial memory cell C00 and the shared memory cells C10, C20, and C30. The operation is performed for all partial regions PA.

Fig. 43 shows the operation during the partial refresh mode in the second embodiment.

In the partial refresh mode, the partial word line SW0P and the shared word lines SW1, SW2, and SW3 are selected at the same time, and the complementary memories held in the partial memory cells C00 and the shared memory cells C10, C20, and C30 are selected. The data is amplified at the same time by the sense amplifier SA and rewritten in the cells C00, C10, C20, and C30 (quad cell operation). By holding data in the partial memory cell C00 and the shared memory cells C10, C20, and C30, the refresh interval can be further extended than in the seventh embodiment.

As mentioned above, also in this embodiment, the same effect as the above-mentioned 1st Embodiment can be acquired. In this embodiment, the data held in one partial memory cell C00 is held in the partial memory cell C00 and the shared memory cells C10, C20, and C30 during the data holding mode. The holding time which can be maintained can be made longer. For this reason, the frequency of refresh operation can be further reduced, and the power consumption in the data holding mode can be significantly reduced.

In the above-described embodiment, an example in which the present invention is applied to a pseudo SRAM has been described. The present invention is not limited to this embodiment. For example, the present invention may be applied to a DRAM having a self refresh function.

In the above-described embodiment, an example in which the CE signal, the / WE signal, and the / OE signal is used as the command signal has been described. The present invention is not limited to this embodiment. For example, as in DRAM, the row address strobe signal / RAS and the column address strobe signal / CAS may be used for the command signal.

In the above-described embodiment, an example in which the operation mode is set to the data holding mode (low power consumption mode) when the chip enable signal CE is at the low level has been described. The present invention is not limited to this embodiment. For example, by receiving two chip enable signals / CE1 and CE2 through external terminals, when the / CE1 signal is at a low level and the CE2 signal is at a high level, the normal read operation and the write operation can be executed. When the CE2 signal is at the low level, the operation mode may be the data hold mode.

As mentioned above, although this invention was demonstrated in detail, above-mentioned embodiment and its modification are only an example of invention, and this invention is not limited to this. It is apparent that modifications can be made without departing from the invention.

In the semiconductor memory of the present invention, in the switching operation of switching from the state of the second storage mode to the state of the first storage mode, the data of the accessed memory cell is lost by executing the first access in the second storage mode. You can prevent it.

By using the flag, memory cells holding data in the second storage mode and memory cells holding data in the first storage mode can be mixed during the switching operation. By accessing the memory cells in the mode corresponding to the flag when transitioning from the second storage mode to the first storage mode, the system managing the semiconductor memory can freely access the memory cells even during the switching operation. As a result, substantial switching time can be eliminated.

In the semiconductor memory of the present invention, by setting all the flags by the flag set circuit before the switching operation, the memory cells of all the memory cell groups can be reliably shifted from the second storage mode to the first storage mode.

In the semiconductor memory of the present invention, by detecting the state of the flag by the flag detection circuit, the operation of the control circuit can be simplified, and the circuit configuration can be simplified.

In the semiconductor memory of the present invention, when the first access is a write operation, the data held in the second storage mode is rewritten to the plurality of memory cells again in the second storage mode, and then the data is stored in the memory cell instructed to write. Is recorded. Therefore, even when a write instruction is given to one of the memory cells holding the data in the second storage mode, the new write data can be held in the predetermined memory cell without destroying the original data. As a result, the system can execute the write operation without waiting even during the switching operation.

In the semiconductor memory of the present invention, the activation frequency of the sense amplifier can be lowered by continually activating the sense amplifier during reading, rewriting, and writing of data to the memory cells, thereby reducing the write operation time.

In the semiconductor memory of the present invention, since the write data is not transmitted to the memory cells connected to the non-selected word lines, the operation of rewriting the data in the second storage mode while activating the sense amplifier and in the first storage mode is performed. The operation of recording data can be executed with simple control.

In the semiconductor memory of the present invention, when the first access is a read operation, the system can execute the read operation without waiting even during the switching operation.

In the semiconductor memory of the present invention, when the first access is a refresh operation, the data held in the second storage mode is rewritten to the plurality of memory cells again in the second storage mode, whereby each memory cell stores the first memory thereafter. Even when the mode is accessed, data can be read or refreshed reliably.

In the semiconductor memory of the present invention, the system can immediately access the semiconductor memory even when the memory cells of the first storage mode and the memory cells of the second storage mode are mixed after switching from the data holding mode to the normal operation mode. That is, the system can operate at high speed.

In the semiconductor memory of the present invention, by the shared refresh operation, the memory cell of the first storage mode is converted into the second storage mode for each refresh operation, thereby efficiently switching from the normal operation mode to the data retention mode.

In the semiconductor memory of the present invention, the memory cells can be easily accessed in the first storage mode or the second storage mode by selecting one or a plurality of word lines.

Claims (11)

A plurality of volatile memory cells; A plurality of word lines respectively connected to the memory cells; A plurality of memory cell groups constituted by the memory cells respectively connected to a predetermined number of word lines; A control circuit for performing an operation of a first storage mode for holding data for each of said memory cells and an operation of a second storage mode for holding the same data in said memory cells of each group of memory cells; A plurality of flags respectively formed in correspondence with the memory cell group and indicating that the memory cell stores data in the second storage mode as a set state; And a flag reset circuit for resetting the respective flags in accordance with the first access of the corresponding memory cell group in the switching operation of switching all the memory cells from the state of the second memory mode to the state of the first memory mode. Semiconductor memory comprising a. 2. The semiconductor memory according to claim 1, further comprising a flag set circuit for setting all the flags before the switching operation. The apparatus of claim 1, further comprising a flag detecting circuit that detects whether or not the corresponding flag is set when the memory cell is accessed. And the control circuit executes the operation of the first storage mode or the operation of the second storage mode in accordance with the detection result of the flag detection circuit. 2. The control circuit according to claim 1, wherein the control circuit reads data from all memory cells of the memory cell group when the first access is a write operation, rewrites the read data into these memory cells, and write is instructed. And writing data into the completed memory cell. The semiconductor device of claim 4, further comprising: a bit line connected to the memory cell; And a sense amplifier connected to said bit line, And the control circuit continuously activates the sense amplifier during reading, rewriting, and writing of data to the memory cell. 6. The word control circuit according to claim 5, further comprising a word control circuit for non-selecting word lines connected to memory cells except for memory cells to which writing in the memory cell group is instructed during activation of the sense amplifier. Semiconductor memory. 2. The control circuit according to claim 1, wherein the control circuit reads data from all memory cells of the memory cell group when the first access is a read operation, outputs the read data to the outside of the semiconductor memory, and reads the read data. And write data back into the memory cell. The semiconductor device according to claim 1, wherein the control circuit reads data from all memory cells of the memory cell group when the first access is a refresh operation, and rewrites the read data into the memory cells. Memory. The apparatus of claim 1, further comprising a normal operation mode operating in accordance with an access command supplied from the outside and a refresh command generated therein, and a data holding mode operating only in accordance with the refresh command. Data is stored in the first storage mode during the normal operation mode, stored in the second storage mode during the data retention mode, And a memory cell of the first storage mode and a memory cell of the second storage mode are mixed in the switching operation from the data holding mode to the normal operation mode. 10. The memory cell of claim 9, wherein the memory cells of the memory cell group include partial memory cells that store data held during the second storage mode. The control circuit stores data stored in the partial memory cell for each refresh command until the memory cell group is in the second storage mode state after the transition from the normal operation mode to the data retention mode. And a shared refresh operation for reading the read data into all the memory cells of the memory cell group. The memory device of claim 1, wherein in the first storage mode, one memory cell connected to the word line of one line holds one bit of information. In the second storage mode, all the memory cells of the memory cell group hold the information.