KR20050073297A - Method of discharging bit line in flash memory device - Google Patents

Abstract

The present invention relates to a bit line discharging method of a flash memory device. The present invention provides a step pulse by applying a voltage applied to a drain select transistor, a bit line select transistor, and a gate terminal of a transistor for data loading. It is possible to stably maintain the bias level of unselected bit lines during the program operation of the flash device, to significantly reduce the program disturbance caused by the bit line loading, and to improve the bit time charging capability during programming. It provides a method for bit line discharging of a flash memory device that can reduce the cost and, in the case of a low voltage device can reduce the burden of the bit line pump and ultimately lower the production cost.

Description

Method of discharging bit line in flash memory device

The present invention relates to a bit line discharging method of a flash memory device, and more particularly, to a method of controlling the discharge level of a bit line during a program operation of a NAND flash device.

In case of NAND type flash cell, since string structure is used, '0' cell is written after precharging bias to bit line to write data during program. Erases the charge of the bit line and, in the case of a '1' cell, leaves the charge of the bit line to prevent the self-boosting effect from being programmed.

In this case, the capacitance between the bit lines is not a problem because the space between adjacent bit lines is relatively large in the case of the existing low density device, but in the case of the high density device, the design rule If the design rule becomes smaller and the cap value between the bit lines is very small and the bias between the bit lines is different, the influence on the adjacent bit lines becomes very large according to the change.

1A and 1B are graphs of changes in bit line voltage during page programming for explaining a conventional problem.

1A and 1B, after precharging all bit lines during a program or read operation, selectively biasing the bit lines of adjacent cells when '0' cells are written is forced. FIG. 1 monitors the time and bias level at which adjacent bit lines rise back to their original level when all pages are programmed, when all bit lines are discharged, and FIG. 1B monitors only half a page. Although there is a difference in both sides, it can be seen that it takes a considerable time (about 20 usec) to return to the original bit line level. This raises the bias of the bit line up to 4.5V from the supply voltage at ground supply (GND) at once. In this case, the bias of the bit line is lowered to the ground power supply. At this time, the bias level of the adjacent bit line is moved to a level similar to the ground power supply as if the capacitance moves in the negative direction due to the bit line capacitance.

Therefore, it takes a certain amount of time to recover this problem, which causes a problem of increasing program time, and if it is not sufficiently compensated for, a program disturb characteristic due to a decrease in the channel booting level. This gets worse.

An object of the present invention is to provide a bit line discharging method of a flash memory device capable of reducing the charging burden of unselected bit lines by adjusting the amount of discharge of the bit lines.

A bit line discharging method of a flash memory device according to the present invention includes a plurality of cell strings, a plurality of word lines and bit lines for selecting cells in the cell string, and a drain terminal between the cell strings and the bit lines. A drain select transistor connected to and driven in accordance with a drain select signal, a source select transistor connected between a source terminal of the cell string and a common source line and driven according to a source select signal, and a cell in the cell string connected to the bit line In a flash memory device including a page buffer for controlling the information of the information, the drain selection signal is applied as a step pulse waveform or a waveform having a predetermined slope to discharge the bit line during a program operation.

In addition, a bit line discharging method of a flash memory device according to an exemplary embodiment of the present invention may include first and second cell strings, first and second bit lines connected to drain terminals of the first and second cell strings, respectively, A page buffer for controlling information of cells in the first and second cell strings, a first NMOS transistor and the second cell connected between the first cell string and the page buffer and driven according to a first bit line selection signal A flash memory device comprising a second NMOS transistor connected between a string and the page buffer and driven according to a second bit line selection signal, the flash memory device comprising: the first memory device for discharging the first or second bit line during a program operation; The first or second bit line selection signal is applied as a step pulse waveform or as a waveform having a predetermined slope.

Further, the bit line discharging method of a flash memory device according to the present invention includes a plurality of cell strings in which a plurality of cells are connected in series, a plurality of bit lines connected to a drain terminal of the cell string, and a source terminal of the cell string. A common source line connected to the plurality of word lines, a plurality of word lines intersecting the bit lines, for selecting each of the cells, a precharge node, the bit line and the precharge node, and connected to a bit line selection signal. A third NMOS transistor to be driven along with it, a PMOS transistor applying a precharge voltage to the precharge node according to a precharge enable signal, a latch unit for storing predetermined information according to the precharge node and a latch control signal; And a fourth NMOS transistor for loading information of the latch unit in the precharge node according to a data loading signal. In the flash memory element, it is applied to the step waveforms for the data load signal to the program operation to charge the bit line discharge, or applied with a waveform having a predetermined slope.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a circuit diagram of a flash memory device according to the present invention.

A plurality of cell strings 100e and 100o, wordlines (W / L) and bitlines (B / L) for selecting respective cells in the cell strings 100e and 100o, and cell strings 100e and 100o. Drain select transistors T1 and T2, which are connected between the drain terminal and the bit line B / L and are driven in accordance with the drain select signal DSLs, between the source terminals of the cell strings 100e and 100o and the common source line. Source information transistors T3 and T4 connected to the source selection signals SSLs and driven according to source selection signals SSLs, and connected to the bit lines B / L to sense information of cells in the cell strings 100e and 100o, or And a page buffer 200 for programming information, wherein the drain select signal DSLs are applied as a step pulse waveform or a waveform having a predetermined slope to discharge the bit line during the program operation. The discharge burden can be reduced.

The first and second cell lines 100e and 100o, the first and second bit lines B / L connected to the drain terminals of the first and second cell strings 100e and 100o, respectively, and the first and second cells. A page buffer 200 for controlling information of cells in the two cell strings 100e and 100o, and is connected between the first cell string 100e and the page buffer 200 to the first bit line selection signal BSLe. The first NMOS transistor N1 and the second NMOS transistor N2 are connected between the second cell string 100o and the page buffer 200 and driven according to the second bit line selection signal BSLo. Including, but not including the first or second bit line selection signal (BSLe and BSLo) as a step waveform to discharge the first or second bit line (B / L) in the program operation, or a waveform having a predetermined slope In this case, the discharge burden of the first and second bit lines B / L may be reduced.

A word line (W / L) for selecting respective cells in the first and second cell strings 100e and 100o, and a common source line connected to the source terminals of the first and second cell strings 100e and 100o. (CSL) may further include. It is connected in series between the first and second bit lines B / L and driven according to external first and second charging control signals DSCe and DSCo, respectively, to the first or second bit lines B / L. The device may further include third and fourth NMOS transistors N3 and N4 for applying a predetermined virtual voltage voltage VIR.

A plurality of cell strings 100 in which a plurality of cells are connected in series, a plurality of bit lines B / L connected to a common drain terminal of the cell string 100, and a common source terminal of the cell string 100. A common source line CSL, a plurality of word lines W / L for selecting each of the cells and intersecting the bit lines B / L, a precharge node Q1, and a bit line B / L) and a first NMOS transistor N1 connected between the precharge node Q1 and driven according to the bit line selection signal BSL, and the precharge node Q1 according to the precharge enable signal PREch. To the PMOS transistor P1 for applying the precharge voltage to the preload voltage, the latch unit 210 for storing predetermined information according to the precharge node Q1 and the latch control signal LATCH, and the data loading signal PGM. Accordingly, a tenth NMOS transistor N10 for loading the information of the latch unit 210 into the precharge node Q1 is included in the program operation. In order to discharge the line B / L, the data loading signal PGM may be applied as a step pulse waveform or a waveform having a predetermined slope to reduce the discharge burden of the bit line B / L. .

The third NMOS transistor N3 may further include a third NMOS transistor N3 which is driven according to an external charging control signal DSC to apply a predetermined virtual voltage voltage VIR to the bit line B / L.

The latch unit 210 is connected between the first latch L1 for latching predetermined data and one input terminal of the first latch L1 and the first node Q10 to be driven according to the latch control signal LATCH. A thirtieth NMOS transistor N20, a thirtieth NMOS transistor N30 connected between the other input terminal of the first latch L1 and the first node Q10, and driven according to a predetermined control signal; And a 40th NMOS transistor N40 connected between the first node Q10 and the ground power source and driven according to the precharge node Q1.

Referring to the program operation of the flash device according to the present invention configured as described above are as follows.

3 is a conceptual diagram illustrating a bias voltage application according to the present invention.

2 and 3, the first and second NMOS transistors N1 and N2 are driven according to the bit line selection signal BSL to select one bit line among the first or second bit lines. Predetermined information is input to the latch unit L1 whether to program '0' data or '1' data. Precharge all bit lines in the cell to the virtual voltage (VIR) level. When programming with '0' data, the selected bit line is discharged to the ground power supply. When programming with '1' data, the discharge is hardly generated since the bit line maintains the power supply voltage level. That is, the unselected bit lines maintain the virtual voltage VIR level. After that, the word line bias is applied to the program. When the selected bit line is discharged, the gate of at least one of the drain select transistors T1 and T2, the first NMOS transistors N1 and N2, and the tenth NMOS transistor N10 connected to the bit line is discharged. The voltage applied to the terminal is controlled to adjust the level of the discharged voltage. That is, by applying a voltage in the form of a step pulse to the gate terminal to the above-described transistor or by applying a voltage having a predetermined slope instead of a vertical voltage, the voltage of the bit line discharged is controlled to control the voltage of the adjacent bit line. This prevents the voltage level from decreasing. The step pulse waveform can be implemented in various ways depending on the discharge time and the characteristics of the device, and it is preferable to apply the step pulse waveform to the device's separation mode. It is also desirable to apply a sloped bias with a gentle curve rather than a discharge time. Slope waveforms can have various inclinations and shapes, and step pulse waveforms can be adjusted in various ways.

At this time, if the cell of the selected bit line is programmed, but the cell of the non-selected bit line or '1' data is programmed, the program is not performed and only the disturb (Disturb) is received.

According to the present invention, when the bias of the drain select signal applied to the train select transistor of the cell is increased to a step pulse, the discharge of the selected bit line is not performed at once, so that the bias of the adjacent bit line is quickly recovered. To maintain the level. Of course, the bias of the bit line selection signal of the first NMOS transistor or the data loading signal applied to the tenth NMOS transistor is also preferably applied in a step waveform of various steps.

After that, since the discharge in the next step is discharged after the bias difference between the bit lines is maintained, the discharge is changed only by the amount of change of the selected bit line in the change in the original virtual voltage or power supply voltage level, so that only the amount of the bias drop is reduced. This will ultimately reduce the burden of recharging.

For example, if the bias of the selected bit line is discharged by 1V by increasing the gate bias of the drain select transistor in the first step, the unselected bit line is biased by virtual voltage minus 1V and then recharged only by 1V. That's it. Also, if the discharge is discharged by 1V in the next step, the selected bit line drops by the voltage of virtual voltage-2V, but the unselected bit lines are charged back to the virtual voltage and then drop by only 1V because the change amount is 1V. Only 1V needs to be charged. In this case, if the gate bias of the drain select transistor is increased until the selected bit line becomes the ground power supply, the unselected amount will not exceed the enhancement 1V or more. Therefore, the level of unselected bit lines can be maintained stably, and the recharging time can be shortened, thereby reducing program time. In addition, in the case of low voltage devices, a pump using many caps was required for bit line charging. In this case, only 1V charging needs to be considered, thereby greatly reducing the cap capacity.

As described above, according to the present invention, a voltage applied to the drain selection transistor, the bit line selection transistor, and the gate terminal of the transistor for data loading is applied in the form of a step pulse so that the bit line is not selected during the program operation of the flash device. The bias level can be maintained stably, and the program disturb work caused by bit line loading can be significantly reduced. In addition, the programming time can be reduced by improving the bit line charging capability during programming, and in the case of low voltage devices, the burden on the bit line pump can be reduced, thereby ultimately lowering the production cost.

1A and 1B are graphs of changes in bit line voltage during page programming for explaining a conventional problem.

2 is a circuit diagram of a flash memory device according to the present invention.

3 is a conceptual diagram illustrating a bias voltage application according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: cell string 200: page buffer

210: latch portion

Claims (3)

Multiple cell strings; A plurality of word lines and bit lines for selecting cells in the cell string; A drain select transistor connected between the drain terminal of the cell string and the bit line and driven according to a drain select signal; A source select transistor connected between a source terminal of the cell string and a common source line and driven according to a source select signal; And A flash memory device comprising a page buffer connected to the bit line to control information of a cell in the cell string. And applying the drain select signal as a step pulse waveform to discharge the bit line during a program operation, or as a waveform having a predetermined slope. First and second cell strings; First and second bit lines connected to drain terminals of each of the first and second cell strings; A page buffer for controlling information of cells in the first and second cell strings; A first NMOS transistor connected between the first cell string and the page buffer and driven according to a first bit line selection signal; And A flash memory device comprising a second NMOS transistor connected between the second cell string and the page buffer and driven according to a second bit line selection signal. Bit line display of a flash memory device which applies the first or second bit line selection signal as a step pulse waveform to discharge the first or second bit line during a program operation, or applies the waveform as a waveform having a predetermined slope. Charging method. A plurality of cell strings in which a plurality of cells are connected in series; A plurality of bit lines connected to the drain terminals of the cell strings; A common source line connected to the source terminal of the cell string; A plurality of word lines crossing each of the bit lines and for selecting each of the cells; Precharge node; A third NMOS transistor connected between the bit line and the precharge node and driven according to a bit line selection signal; A PMOS transistor applying a precharge voltage to the precharge node according to a precharge enable signal; A latch unit for storing predetermined information according to the precharge node and a latch control signal; And A flash memory device comprising a fourth NMOS transistor for loading information of the latch unit in the precharge node according to a data loading signal, The method of claim 1, wherein the data loading signal is applied as a step waveform or a waveform having a predetermined slope to discharge the bit line during a program operation.