KR20050068763A - Method for manufacturing semiconductor devices - Google Patents
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- KR20050068763A KR20050068763A KR1020030100568A KR20030100568A KR20050068763A KR 20050068763 A KR20050068763 A KR 20050068763A KR 1020030100568 A KR1020030100568 A KR 1020030100568A KR 20030100568 A KR20030100568 A KR 20030100568A KR 20050068763 A KR20050068763 A KR 20050068763A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 18
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000004140 cleaning Methods 0.000 abstract description 6
- 238000003860 storage Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 반도체기판 상에 오엔오(ONO)막을 형성하는 단계와; 상기 오엔오막 상에 게이트전극을 형성하고 상기 반도체기판의 나머지 영역의 오엔오막을 제거하는 단계와; 상기 게이트전극과 상기 반도체기판의 나머지 영역에 게이트산화막을 형성하는 단계; 상기 게이트산화막 상에 게이트전극을 형성하는 단계와; 상기 게이트전극에 캡산화막을 형성하는 단계를 포함하는 것을 특징으로 한다. 이에 의해, ONO층 중 전하 저장층인 질화막 형성 시 H2 어닐링으로 인하여 발생한 열이력(Thermal budget)을 최소화할 뿐 아니라, Pre-furnace세정으로 인한 Top oxide를 최소 하고 게이트 식각 후 발생 가능성이 높은 게이트표면 잔여물 문제를 해소하여 소자의 특성을 향상시킬 수 있다.The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of: forming an ONO film on a semiconductor substrate; Forming a gate electrode on the oho film and removing the oho film of the remaining area of the semiconductor substrate; Forming a gate oxide film on the gate electrode and the remaining regions of the semiconductor substrate; Forming a gate electrode on the gate oxide film; And forming a cap oxide film on the gate electrode. This not only minimizes the thermal budget generated by H2 annealing during formation of the nitride film, which is the charge storage layer in the ONO layer, but also minimizes the top oxide due to pre-furnace cleaning and is more likely to occur after gate etching. Residual problems can be eliminated to improve device characteristics.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더욱 상세하게는 소노스(SONOS: silicon-oxide-nitride-oxide-silicon)구조를 갖는 비휘발성 메모리소자를 제조함에 있어서, ONO층 중 전하 저장층인 질화막 형성 시 H2 어닐링으로 인하여 발생한 열이력(Thermal budget)을 최소화 하는 한편, Pre-furnace세정으로 인한 Top oxide를 최소 하고 게이트 식각 후 발생 가능성이 높은 게이트 표면의 잔여물 문제를 해소하여 소자의 특성을 향상시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a nonvolatile memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure, which is a charge storage layer in an ONO layer. While minimizing the thermal budget caused by H2 annealing when forming the nitride film, it minimizes the top oxide caused by pre-furnace cleaning and solves the problem of the residue on the gate surface that is more likely to occur after gate etching. The manufacturing method of the semiconductor element which can be improved.
반도체 메모리소자들 중에 비휘발성 메모리소자는 전원이 공급되지 않을지라도 전상태의 정보(previous data)가 소멸되지 않는 특징을 갖는다. 이러한 비휘발성 반도체 메모리(Nonvolatile Semiconductor Memories; NVSM) 기술은 크게 플로팅 게이트(floating gate) 계열과 두 종류 이상의 유전막이 2중 혹은 3중으로 적층된 적층게이트 계열로 구분되며, 일반적으로, 적층게이트 구조(stacked gate structure)가 비휘발성 메모리소자의 셀 트랜지스터에 널리 채택되고 있다.Among the semiconductor memory devices, nonvolatile memory devices are characterized in that their previous data does not disappear even when power is not supplied. Nonvolatile Semiconductor Memories (NVSM) technology is largely divided into a floating gate series and a stacked gate series in which two or more dielectric layers are stacked in double or triple layers, and in general, a stacked gate structure. Gate structures are widely adopted in cell transistors of nonvolatile memory devices.
적층게이트 구조는 셀 트랜지스터의 채널 영역 상에 차례로 적층된 터널산화막, 부유게이트, 게이트층간 유전체막 및 제어게이트 전극을 포함하는데, 특히, 고집적 비휘발성 메모리소자의 경우에, 부유게이트의 표면적을 증가시키기 위한 방법으로 소노스(SONOS: silicon-oxide-nitride-oxide-silicon)게이트 구조를 갖는 셀 트랜지스터가 제안된 바 있다. The stacked gate structure includes a tunnel oxide film, a floating gate, an inter-gate dielectric film, and a control gate electrode sequentially stacked on the channel region of the cell transistor. In particular, in the case of highly integrated nonvolatile memory devices, the surface area of the floating gate may be increased. As a method, a cell transistor having a silicon-oxide-nitride-oxide-silicon (SONOS) gate structure has been proposed.
SONOS구조를 가진 SONOS플래쉬 소자는 비휘발성 메모리 소자와 유사하게 읽기(read), 쓰기(program) 및 소거(erase)의 세가지 동작으로 구분된다. 쓰기 동작의 경우, 셀의 트랜지스터의 게이트와 드레인에 프로그램 전압을 인가시켜 핫 전자(hot electron)를 형성한 후 게이트 절연막의 터널링(tunneling)에 의해 드레인의 인접 영역의 질화막에 포획함으로써 데이터의 쓰기가 이루어진다. 한편, 소거 동작의 경우, 게이트와 드레인 및 소스를 오픈시켜 반도체 기판에 소거 전압을 인가시킴으로써, 질화막에 포획되었던 전자를 반도체 기판 측으로 밀어냄으로써 데이터의 소거가 이루어진다. A SONOS flash device having a SONOS structure is divided into three operations, read, write, and erase, similar to nonvolatile memory devices. In the write operation, a program voltage is applied to the gate and the drain of the cell transistor to form hot electrons, and then the data is written by trapping the nitride film in the adjacent region of the drain by tunneling the gate insulating film. Is done. In the erase operation, on the other hand, the gate, the drain, and the source are opened to apply an erase voltage to the semiconductor substrate, thereby erasing data by pushing electrons trapped in the nitride film toward the semiconductor substrate.
종래의 SONOS 구조를 갖는 비휘발성 메모리 소자는 도 1에 도시된 바와 같이, P형 반도체기판(10)의 액티브 영역의 셀(cell) 영역이 반도체기판(10)의 필드 영역의 트렌치(11) 내의 소자 분리막(13)에 의해 정의된다. 셀 영역의 반도체기판(10) 상에는 전체적으로 게이트산화막(15)이 형성되고, 게이트산화막(15) 상에 소정 이격 간격을 가지고 제1, 2게이트전극(21),(23)이 형성되며, 제1게이트전극(21)과 제2게이트전극(23) 사이에는 제3게이트전극(35)이 형성되는데, 제3게이트전극(35)은 게이트산화막(15) 상에 질화막(31)과 산화막(33)을 증착시킨 후 형성된다. In the conventional nonvolatile memory device having a SONOS structure, as shown in FIG. 1, a cell region of an active region of a P-type semiconductor substrate 10 is formed in a trench 11 of a field region of the semiconductor substrate 10. It is defined by the element isolation film 13. The gate oxide film 15 is entirely formed on the semiconductor substrate 10 in the cell region, and the first and second gate electrodes 21 and 23 are formed on the gate oxide film 15 at predetermined intervals. A third gate electrode 35 is formed between the gate electrode 21 and the second gate electrode 23, and the third gate electrode 35 is formed on the gate oxide film 15 and the nitride film 31 and the oxide film 33. It is formed after depositing.
제3게이트전극(35)의 게이트산화막(15)과 질화막(31) 및 산화막(33)은 ONO(oxide-nitride-oxide)막(30)을 구성하는데, 여기서, 게이트산화막(15)은 ONO막(30)의 하부 턴널링 산화막으로 작용하고, 그 위에 증착된 질화막(31)은 ONO막(30)의 트랩(trap) 질화막으로 작용하며, 산화막(33)은 제3게이트전극(35)과 직접 접촉되어 ONO막(30)의 상부 산화막으로서 역할을 담당한다. The gate oxide film 15, the nitride film 31, and the oxide film 33 of the third gate electrode 35 constitute an oxide-nitride-oxide (ONO) film 30, where the gate oxide film 15 is an ONO film. It acts as a lower tunneling oxide film of 30, and the nitride film 31 deposited thereon serves as a trap nitride film of the ONO film 30, and the oxide film 33 is directly connected to the third gate electrode 35. It comes into contact with and serves as an upper oxide film of the ONO film 30.
그런데, 종래의 SONOS 구조를 갖는 비휘발성 메모리 소자를 제조하는 경우, 상기 반도체 기판(10)의 셀 영역 상에 게이트 절연막(15)을 형성하고, 상기 게이트 절연막(15) 상에 제 1, 2 게이트 전극(21),(23)을 위한 다결정 실리콘층을 적층하고, 사진식각공정을 이용하여 상기 다결정 실리콘층의 불필요 부분을 제거시킴으로써 상기 제 1, 2 게이트 전극(21),(23)을 형성한다. However, when manufacturing a nonvolatile memory device having a conventional SONOS structure, a gate insulating film 15 is formed on a cell region of the semiconductor substrate 10, and first and second gates are formed on the gate insulating film 15. The first and second gate electrodes 21 and 23 are formed by stacking polycrystalline silicon layers for the electrodes 21 and 23 and removing unnecessary portions of the polycrystalline silicon layer using a photolithography process. .
그런 다음, 상기 게이트 절연막(15)과 제 1, 2 게이트 전극(21),(23) 상에 상기 질화막(31)과 산화막(33)을 순차적으로 적층하고, 상기 산화막(33) 상에 상기 제 3 게이트 전극(35)을 위한 다결정 실리콘을 적층하고, 사진식각공정을 이용하여 상기 다결정 실리콘층과 산화막(33) 및 질화막(31)을 제거시킴으로써 상기 제 3 게이트 전극(35)을 형성한다.Thereafter, the nitride film 31 and the oxide film 33 are sequentially stacked on the gate insulating film 15 and the first and second gate electrodes 21 and 23, and the first and second gate films are stacked on the oxide film 33. The third gate electrode 35 is formed by stacking polycrystalline silicon for the three gate electrode 35 and removing the polycrystalline silicon layer, the oxide layer 33, and the nitride layer 31 using a photolithography process.
이러한 종래의 반도체 소자 제조방법은 ONO층 중 전하 저장층인 질화막 형성 시의 H2어닐링으로 인한 열이력(Thermal budget)이 크기 때문에 트렌지스터의 특성을 저하시키는 문제점이 있었다.The conventional method of manufacturing a semiconductor device has a problem of degrading the characteristics of the transistor because the thermal budget due to H 2 annealing during formation of a nitride film, which is a charge storage layer, is large in the ONO layer.
따라서, 본 발명의 목적은 소노스(SONOS: silicon-oxide-nitride-oxide-silicon)구조를 갖는 비휘발성 메모리소자를 제조함에 있어서, ONO층 중 전하 저장층인 질화막 형성 시 H2 어닐링으로 인하여 발생한 열이력(Thermal budget)을 최소화 하는 한편, Pre-furnace세정으로 인한 Top oxide를 최소 하고 게이트 식각 후 발생 가능성이 높은 게이트 표면의 잔여물 문제를 해소하여 소자의 특성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 있다. Accordingly, an object of the present invention is to produce a non-volatile memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure, the heat generated due to H2 annealing during the formation of a nitride film as a charge storage layer of the ONO layer A method of manufacturing a semiconductor device that can improve device characteristics by minimizing thermal budget, minimizing top oxide due to pre-furnace cleaning, and eliminating the problem of gate surface residues that are more likely to occur after gate etching. To provide.
이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조 방법은, 반도체기판 상에 오엔오(ONO)막을 형성하는 단계와; 상기 오엔오막 상에 게이트전극을 형성하고 상기 반도체기판의 나머지 영역의 오엔오막을 제거시키는 단계와; 상기 게이트전극과 상기 반도체기판의 나머지 영역에 게이트산화막을 형성하는 단계; 상기 게이트산화막 상에 게이트전극을 형성하는 단계와; 상기 게이트전극에 캡산화막을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of: forming an ONO film on a semiconductor substrate; Forming a gate electrode on the oho film and removing the oho film of the remaining area of the semiconductor substrate; Forming a gate oxide film on the gate electrode and the remaining regions of the semiconductor substrate; Forming a gate electrode on the gate oxide film; And forming a cap oxide film on the gate electrode.
여기서, 상기 오엔오막은 습식식각공정 및 건식식각공정 중 적어도 어느 하나를 통해 형성하는 것도 무방하다.Here, the ohio film may be formed through at least one of a wet etching process and a dry etching process.
그리고, NLDD 이온주입에 따른 상기 게이트전극의 손상을 방지하기 위해 다결정산화막을 20~100Å으로 성장 시키고 이온 주입 후 어닐링하는 단계를 더 포함하는 것이 바람직 하다.Further, in order to prevent damage to the gate electrode due to NLDD ion implantation, it is preferable to further include a step of growing a polycrystalline oxide film to 20 to 100 microns and annealing after ion implantation.
또한, PLDD 이온주입에 따른 상기 게이트전극의 손상을 방지하기 위해, 상기 캡산화막을 LPCVD 방법으로 TEOS를 50~250Å으로 성장 시키는 단계를 더 포함하는 것이 바람직 하다.In addition, in order to prevent damage to the gate electrode due to PLDD ion implantation, it is preferable to further include the step of growing the TEOS to 50 ~ 250 50 by the cap oxide film LPCVD method.
이하, 본 발명에 의한 반도체 소자의 제조 방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다. 종래의 부분과 동일한 구성 및 동일한 작용을 갖는 부분에는 동일 부호를 부여한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part which has the same structure and the same action as the conventional part.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 단면 공정도이다.2A to 2D are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.
도 2a를 참조하면, 먼저, 단결정실리콘기판과 같은 반도체기판(10)의 전역 상에 ONO막(40)을 위한 하부산화막(41)과 질화막(43)과 상부산화막(45)을 순차적으로 형성하고 다결정실리콘층(65)을 적층한다. Referring to FIG. 2A, first, a lower oxide film 41, a nitride film 43, and an upper oxide film 45 for the ONO film 40 are sequentially formed on the entire semiconductor substrate 10 such as a single crystal silicon substrate. The polysilicon layer 65 is laminated.
여기서, 하부산화막(41)은 예컨대, 습식산화 공정을 통해 50~100Å의 두께로 성장시키고, 질화막(43)을 저압화학기상증착 공정을 통해 20~50Å의 두께로 적층한 후, 상부산화막(45)을 고온산화(HTO: high temperature oxidation) 공정을 통해 형성함으로써, ONO막을 형성한다. 이에, 하부산화막(41)은 턴널링 산화막으로서의 역할을 담당하고, 질화막(43)은 트랩 질화막으로서의 역할을 담당한다. 이렇게 ONO막(40)을 형성한 후, 그 위에 다결정실리콘층(65)을 적층한다. Here, the lower oxide film 41 is grown to a thickness of 50 to 100 kPa through, for example, a wet oxidation process, and the nitride film 43 is laminated to a thickness of 20 to 50 kPa through a low pressure chemical vapor deposition process, and then the upper oxide film 45 is formed. ) Is formed through a high temperature oxidation (HTO) process to form an ONO film. Accordingly, the lower oxide film 41 plays a role as a tunneling oxide film, and the nitride film 43 plays a role as a trap nitride film. After the ONO film 40 is formed in this manner, the polysilicon layer 65 is laminated thereon.
이러한 과정 중에, 다결정실리콘층(65) 상에 N형불순물 이온주입영역을 노출하는 이온주입 마스크층으로서 감광막(미도시)의 패턴을 형성하여 다결정실리콘층(65)에 N형 불순물, 예를 들어 인(P)을 이온주입할 수 있으며. 반도체기판(10)의 SONOS구조 형성 영역에는 이온주입공정을 이용하여 문턱전압을 조절하기 위한 이온주입영역(미도시)을 형성할 수 있다.During this process, a pattern of a photoresist film (not shown) is formed as an ion implantation mask layer exposing the N-type impurity ion implantation region on the polysilicon layer 65 to form N-type impurities, for example, in the polysilicon layer 65. Phosphorus (P) can be ion implanted. An ion implantation region (not shown) for adjusting the threshold voltage may be formed in the SONOS structure formation region of the semiconductor substrate 10 using an ion implantation process.
도 2b를 참조하면, 다결정실리콘층(65)의 증착 후, 사진식각공정을 이용하여 도 2a의 다결정실리콘층(65) 및 ONO막(40)을 SONOS구조 형성영역 상에 남김으로써 제3게이트전극(75)을 형성한다. 이에 따라, 반도체기판(10)의 SONOS구조 형성영역 상에는 ONO막(40) 위에 제3게이트전극(75)이 형성되고, 나머지 영역의 ONO막(40)이 모두 제거되어 제3게이트전극(75)의 외측의 반도체 기판(10)의 액티브 영역의 표면이 노출된다. Referring to FIG. 2B, after the deposition of the polysilicon layer 65, the third gate electrode is formed by leaving the polysilicon layer 65 and the ONO film 40 of FIG. 2A on the SONOS structure forming region by using a photolithography process. Form 75. Accordingly, the third gate electrode 75 is formed on the ONO film 40 on the SONOS structure formation region of the semiconductor substrate 10, and all of the ONO film 40 in the remaining areas is removed to form the third gate electrode 75. The surface of the active region of the semiconductor substrate 10 on the outside of the substrate is exposed.
그런 다음, 이온주입공정을 이용하여 반도체기판(10)의 셀 영역 내에 예를 들어 NMOS 트랜지스터를 위한 P웰 영역을 형성한다. 물론, 도면에 도시하지 않았지만, 이온주입공정을 이용하여 상기 ONO막(40)의 패턴을 형성하기 전 또는 후에 반도체기판(10)의 고압로직영역과 저압로직영역에 N웰 및 P웰 영역을 형성시킴은 자명한 사실이다. 설명의 편의상, 이에 대한 부분은 본 발명의 요지에 관한 관련성이 적으므로 설명을 생략하기로 한다.Then, a P well region, for example, an NMOS transistor, is formed in the cell region of the semiconductor substrate 10 using an ion implantation process. Of course, although not shown, N wells and P well regions are formed in the high voltage logic region and the low pressure logic region of the semiconductor substrate 10 before or after forming the pattern of the ONO film 40 using an ion implantation process. Sikkim is self-evident. For convenience of description, parts thereof are not related to the gist of the present invention and thus description thereof will be omitted.
이렇게, 제3게이트전극(75)이 형성되면 열산화공정을 통해 게이트산화막(63)을 적층한다. 게이트산화막(63)은 예컨대, 열산화공정에 의해 20~50Å의 두께로 형성할 수 있다. As such, when the third gate electrode 75 is formed, the gate oxide layer 63 is laminated through a thermal oxidation process. The gate oxide film 63 can be formed to a thickness of, for example, 20 to 50 kPa by a thermal oxidation process.
도 2c를 참조하면, 게이트산화막(63)위에 다결정실리콘층(66)을 적층하고, 마스크층으로서 감광막(미도시)의 패턴을 형성하여 셀 영역의 다결정실리콘층(66)에 N형 불순물, 예를 들어 인(P)을 이온주입한다. 그 다음에, 상기 감광막의 패턴을 제거하고 나서 상기 반도체기판(10)을 예를 들어 세정액에 세정시킨다.Referring to FIG. 2C, a polysilicon layer 66 is laminated on the gate oxide layer 63, and a pattern of a photoresist layer (not shown) is formed as a mask layer to form N-type impurities, for example, in the polysilicon layer 66 in the cell region. For example, phosphorus (P) is ion implanted. Then, after removing the pattern of the photosensitive film, the semiconductor substrate 10 is washed with, for example, a cleaning liquid.
도 2d를 참조하면, 이후, 사진식각공정을 통해 도 2c의 다결정실리콘층(65)을 게이트산화막(63)의 게이트전극 형성 영역 상에 남김으로써 제 1, 2 게이트 전극(71),(73)을 각각 형성한 후, 도 2e에 도시 된 바와 같이, 캡산화막(80)을 증착시킨 후, 다결정실리콘을 이용하여 각 전극(71, 73, 75)에 사이드 웰(side-well)(82)을 형성하여 반도체 소자를 완성한다.Referring to FIG. 2D, the first and second gate electrodes 71 and 73 are left on the gate electrode forming region of the gate oxide film 63 by leaving the polysilicon layer 65 of FIG. 2C through a photolithography process. After the formation of each, as shown in Figure 2e, after depositing the cap oxide film 80, using a polycrystalline silicon side-well (side-well) 82 to each electrode (71, 73, 75) To form a semiconductor device.
이와 같이, 본 발명은 ONO구조를 갖는 게이트전극을 먼저 형성하고 이 후 게이트산화막을 형성하여 게이트전극을 형성함으로써, ONO층 중 전하 저장층인 질화막 형성 시 H2 어닐링으로 인하여 발생한 열이력(Thermal budget)을 최소화할 뿐 아니라, Pre-furnace세정으로 인한 Top oxide를 최소 하고 게이트 식각 후 발생 가능성이 높은 게이트 표면 잔여물 문제를 해소하여 소자의 특성을 향상시킬 수 있다.As described above, the present invention forms a gate electrode having an ONO structure first and then forms a gate oxide film to form a gate electrode, thereby generating a thermal budget generated by H2 annealing during formation of a nitride film, which is a charge storage layer among the ONO layers. In addition, the device's characteristics can be improved by minimizing top oxide due to pre-furnace cleaning and eliminating the problem of gate surface residues that are more likely to occur after gate etching.
한편, 본 발명은 도시된 도면과 상세한 설명에 기술된 내용에 한정하지 않으며 본 발명의 사상을 벗어나지 않는 범위 내에서 다양한 형태의 변형도 가능함은 이 분야에 통상의 지식을 가진 자에게는 자명한 사실이다.On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .
이상에서 상세히 설명한 바와 같이, 본 발명에 의한 반도체 소자의 제조 방법은 ONO구조를 갖는 게이트전극을 먼저 형성하고 이 후 게이트산화막을 형성하여 게이트전극을 형성함으로써, ONO층 중 전하 저장층인 질화막 형성 시 H2 어닐링으로 인하여 발생한 열이력(Thermal budget)을 최소화할 뿐 아니라, Pre-furnace세정으로 인한 Top oxide를 최소 하고 폴리실리콘 식각 후 발생 가능성이 높은 폴리실리콘 잔여물 문제를 해소하여 소자의 특성을 향상시킬 수 있다. As described in detail above, in the method of manufacturing a semiconductor device according to the present invention, a gate electrode having an ONO structure is formed first, and then a gate oxide film is formed to form a gate electrode, thereby forming a nitride film as a charge storage layer in the ONO layer. In addition to minimizing the thermal budget due to H2 annealing, it is possible to minimize top oxides due to pre-furnace cleaning and to solve the problem of polysilicon residues that are more likely to occur after polysilicon etching. Can be.
도 1은 종래의 소노스(SONOS: silicon-oxide-nitride-oxide-silicon) 구조의 비휘발성 메모리 소자의 셀 영역을 나타낸 단면 구조도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional structural view showing a cell region of a non-volatile memory device having a conventional silicon-oxide-nitride-oxide-silicon (SONOS) structure.
도 2a 내지 도 2e는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 단면 공정도.2A to 2E are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.
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