KR20050068295A - An array substrate for lcd and the fabrication method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same.

The present invention provides an array substrate for a liquid crystal display device in which a gate wiring and a data wiring intersect an upper portion of the substrate, and a thin film transistor is formed at an intersection point of the gate wiring and the data wiring. A light shield bar is formed in between.

Therefore, the present invention can reduce the parasitic capacitance value by changing the pattern of the light blocking bar to improve the poor image quality and improve the image quality of the liquid crystal display.

Description

An array substrate for a liquid crystal display and a method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. Among them, a liquid crystal display having excellent color reproducibility, etc. displays are actively being developed.

In general, a liquid crystal display device is formed by arranging two substrates having electrodes formed on one surface thereof so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

Liquid crystal displays may be formed in various forms. Currently, an active matrix LCD (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistors arranged in a matrix manner has excellent resolution and video performance. It is most noticed.

The liquid crystal display has a structure in which a pixel electrode is formed on a lower array substrate and a common electrode is formed on a color filter substrate, which is an upper substrate, and drives liquid crystal molecules by an electric field in a direction perpendicular to an up and down substrate. to be. This is excellent in characteristics such as transmittance and aperture ratio, and the common electrode of the upper plate serves as a ground, thereby preventing the destruction of the liquid crystal cell due to static electricity.

Here, the upper substrate of the liquid crystal display further includes a black matrix to prevent light leakage occurring in portions other than the pixel electrode.

On the other hand, the array substrate, which is the lower substrate of the liquid crystal display, is formed by repeatedly depositing a thin film and performing a photolithography process using a mask several times. Typically, 4 to 5 masks are used, and the number of masks is an array substrate. It represents the number of etching process to prepare.

Hereinafter, a conventional array substrate for a liquid crystal display device and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a plan view of a conventional array substrate for a liquid crystal display, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, in an array substrate for a liquid crystal display device, a gate wiring 121 having a horizontal direction and a gate electrode 122 extending from the gate wiring 121 are disposed on a transparent insulating substrate 110. Formed.

An active layer 141 is formed on the gate line 121 and the gate electrode 122.

The data line 161 orthogonal to the gate line 121, the source electrode 162 extending from the data line 161, and the drain facing the source electrode 162 around the gate electrode 122. The electrode 163 is formed.

In this case, as shown in FIG. 2, since the active layer 141 and the data line 161 are sequentially stacked and collectively formed by diffraction exposure, an active layer (below the data line 161 is formed). 141) A pattern is formed.

A light shield bar 195 is formed below the data line 161 with the gate insulating layer 130 interposed therebetween.

At this time, the width of the light blocking bar 195 is formed to be wider than the width of the data line 161 to block the light.

Here, the data line 161 and the source and drain electrodes 162 and 163 are covered with a protective layer (not shown in FIG. 1, 170 of FIG. 2), and the protective layer is a drain exposing the drain electrode 163. It has a contact hole 171.

The pixel electrode 181 is formed on the passivation layer 170 of the pixel area defined by the gate line 121 and the data line 161 intersecting, and the pixel electrode 181 forms a drain contact hole 171. It is connected to the drain electrode 162 through each.

As illustrated in FIG. 2, parasitic capacitors C ₁ , C ₂ , C ₃ , and C ₄ are formed between the light blocking bar 195, the pixel electrode 181, and the data line 161.

3 is a cross-sectional view illustrating a pattern shift in the data line unit illustrated in FIG. 2.

As shown in FIG. 3, when the pixel electrode 181 pattern is shifted, a capacitance difference inside the panel is generated due to a difference in an overlay between the light blocking bar 195 and the pixel electrode 181 pattern, and accordingly, a screen is displayed. There is a problem that the stain occurs.

That is, the mask for forming the light blocking bar 195, the process for forming the data line 161, and the process for forming the pixel electrode 181 use different masks.

Accordingly, the pattern of the pixel electrode 181 is shifted due to various problems occurring during misalignment or exposure of the mask.

Accordingly, a difference in parasitic capacitance between the light blocking bar 195, the data line 161, and the pixel electrode 181 occurs, which causes one to cause uneven display and uneven brightness. This will cause a check stain.

That is, the capacitance C ₃ induced between the light blocking bar pattern and the pixel electrode is changed, and the capacitance value C ₁ between the data line and the pixel electrode is changed to cause a difference in the total capacitance value inside the panel. There is a problem that a poor image quality occurs.

The present invention provides an array substrate for a liquid crystal display device and a method of manufacturing the same, which may improve image quality defects by changing a pattern of a light blocking bar formed of a gate metal under a data line in a liquid crystal display device to decrease parasitic capacitance values. The purpose is to provide.

In order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention comprises: a gate wiring formed in a first direction; A data line formed in a second direction crossing the gate line; A thin film transistor comprising a gate electrode, an active layer, a source and a drain electrode at a point where the gate line and the data line cross each other; A pixel electrode connected to the drain electrode and formed in the pixel area where the gate line and the data line cross each other; And a light shield bar formed on the same layer as the gate wiring material and formed on at least both sides of the data wiring in a second direction.

The active layer, the source electrode and the drain electrode may be etched collectively.

The light blocking bar is not overlapped with the data line and the pixel electrode.

An active layer is formed below the data line.

In addition, in order to achieve the above object, in the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, a gate line and a data line cross on an upper portion of the substrate, and a thin film transistor is formed at an intersection point of the gate line and the data line. In the array substrate for a liquid crystal display device, forming a light shield bar with an insulating film in the periphery of the data wiring when forming the gate wiring.

The thin film transistor may include a gate electrode extending from a gate wiring, an active layer, an ohmic contact layer, a source electrode and a drain electrode extending from the data wiring on the gate electrode.

The data line is sequentially stacked with the active layer and is formed by batch etching.

The light blocking bar is not overlapped with the data line and the pixel electrode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of an array substrate for a liquid crystal display according to the present invention, and FIG. 5 is a cross-sectional view taken along lines II-II 'and III-III' of FIG. 4.

4 and 5, in the array substrate for a liquid crystal display device, a gate wiring 221 having a horizontal direction and a gate electrode 222 extending from the gate wiring 221 are disposed on the transparent insulating substrate 210. Formed.

The gate insulating layer 230 is formed on the gate line 221 and the gate electrode 222, and the active layer 241 and the ohmic contact layers 251 and 252 are sequentially formed thereon.

The source electrode is disposed on the ohmic contact layers 251 and 252 with the data wire 261 orthogonal to the gate wire 221, the source electrode 262 extending from the data wire 261, and the gate electrode 222. A drain electrode 263 facing the 262 is formed.

Light blocking bars 295 and 296 are formed in a space between the data line 261 and the pixel electrode 281, and the light blocking bars 295 and 296 are formed around the data line 261. It is formed in the lower part of the ring (ring type).

In this case, as shown in FIG. 5, the light blocking bars 295 and 296 using the gate electrode 222 and the gate metal are formed on the substrate 210, and the light blocking bars 295 and 296 and the gate electrode 222 are formed. ) Is formed on the substrate 210 on which the gate insulating film 230 is formed.

The active layer 241 and the data line 261 are sequentially stacked on the gate insulating layer 230, and then patterned collectively by diffraction exposure to form the active layer 241, the source electrode and the drain electrode 262 and 263. ) Is formed, and an active layer 241 pattern is formed under the data line 261.

Here, light shield bars 295 and 296 are formed under the data line 261 with the gate insulating layer 230 interposed therebetween, and the light blocking bars 295 and 296 are ring type. The first and second light blocking bars 295 and 296 are formed so as not to overlap the data wiring 261 with the data wiring 261 interposed therebetween, and are conveniently formed in the same direction as the data wiring 261. Light blocking bars 295 and 296 will be referred to.

The data line 261 and the source and drain electrodes 262 and 263 are covered with a protective layer 270, and the protective layer 270 has a drain contact hole 271 exposing the drain electrode 263. .

The pixel electrode 281 is formed on the passivation layer 270 of the pixel region defined by the gate wiring 221 and the data wiring 261 intersecting, and the pixel electrode 281 is connected to the drain contact hole 271. It is connected to the drain electrode 262 through each.

As shown in FIG. 5, parasitic capacitances C ₁ , C ₂ , C ₃ , and C ₄ between the first and second light blocking bars 295 and 296, the pixel electrodes 281, and the data lines 261. Is formed.

The capacitance satisfies the following formula.

(C: capacitor capacity, ε: dielectric constant of insulator, A: area of electrode, d: distance between electrode bodies)

That is, the factor that can change the capacitance value in relation to the above equation may be regarded as an opposing distance between the data line 261 and the pixel electrode 281.

FIG. 6 is a cross-sectional view illustrating a pattern shift in the data wire unit illustrated in FIG. 4.

As shown in FIG. 6, when the pattern of the pixel electrode 281 shifts, capacitance difference inside the panel is generated due to the difference in the overlay between the light blocking bars 295 and 296 and the pattern of the pixel electrode 281.

In this case, since the first and second light blocking bars 295 and 296 are formed to the side of the data line 261, the light blocking bars 295 and 296 have a small area and a small value of the capacitance C ₃ .

When the pixel electrode 281 shifts, the distance between the data line 261 and the pixel electrode 281 also increases, so that the capacitance C ₁ value becomes small.

On the other hand, the capacitance (C ₄₎ between the pixel electrode 281 even when the shift active layer 241 and the light blocking bars (295, 296) distance, so much change between the active layer 241 and the light blocking bars (295, 296) is substantially There is no change, and there is almost no change in capacitance C ₂ between the active layer 241 and the pixel electrode 281.

Therefore, the capacitance value of the overall panel is lowered, thereby improving screen unevenness.

Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and the array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention are not limited thereto, and within the technical spirit of the present invention. It is apparent that modifications and improvements are possible by those skilled in the art.

The present invention has the effect of reducing the capacitance between the light blocking bar, the data wiring and the pixel electrode in the array substrate for the liquid crystal display device to block the light leakage area using the light blocking bar, as well as reducing the parasitic capacitor to improve the image quality of the liquid crystal display device. There is.

1 is a plan view of a conventional array substrate for a liquid crystal display device.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1. FIG.

FIG. 3 is a cross-sectional view illustrating a pattern shift in the data wiring portion shown in FIG. 2. FIG.

4 is a plan view of an array substrate for a liquid crystal display device according to the present invention;

FIG. 5 is a cross-sectional view taken along lines II-II 'and III-III' of FIG. 4;

FIG. 6 is a cross-sectional view illustrating a pattern shift in the data wiring portion shown in FIG. 4. FIG.

<Description of Signs of Major Parts of Drawings>

210: substrate 221: gate wiring

222: gate electrode 230: gate insulating film

241: active layer 251, 252: ohmic contact layer

261: data wiring 262: source electrode

263: drain electrode 270: protective layer

271: drain contact hole 281: pixel electrode

295, 296: shading bar

Claims (8)

A gate wiring formed in a first direction; A data line formed in a second direction crossing the gate line; A thin film transistor comprising a gate electrode, an active layer, a source and a drain electrode at a point where the gate line and the data line cross each other; A pixel electrode connected to the drain electrode and formed in the pixel area where the gate line and the data line cross each other; And a light shield bar formed on the same layer as the gate wiring material and formed on at least both sides of the data wiring in a second direction. The method of claim 1, And the active layer, the source electrode, and the drain electrode are collectively etched. The method of claim 1, The light blocking bar does not overlap the data line and the pixel electrode. The method of claim 1, An active layer is formed under the data line. In an array substrate for a liquid crystal display device in which a gate wiring and a data wiring cross over a substrate, and a thin film transistor is formed at an intersection point of the gate wiring and a data wiring, And forming a light shield bar with an insulating film interposed therebetween in the periphery of the data wiring when the gate wiring is formed. The method of claim 5, The thin film transistor includes a gate electrode extending from a gate wiring, an active layer, an ohmic contact layer, a source electrode and a drain electrode extending from the data wiring, on the gate electrode. Way. The method of claim 5 or 6, And the data lines are sequentially stacked with the active layers and are collectively etched to form the data lines. The method of claim 5, The light blocking bar does not overlap with the data line and the pixel electrode.