KR20050064600A - Flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device capable of detecting an over erased memory cell in advance and increasing a threshold voltage of such a cell to a post-program to recover a normally operated memory cell. A flash memory cell array including the memory cells, a mode setting means for setting an operation mode, a data of the flash memory cell selected by the verification enable signal output from the mode setting means, and sensing data of the selected flash memory cell And sensing amplifying means for amplifying and outputting data, and detecting the amplifying means by sensing data of the selected flash memory cell to determine whether it is over-erased, and over-detecting means for restoring when the selected flash memory cell is over-erased. It is characterized by including.

Description

Flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device, and more particularly, to detect an over erased memory cell in advance, and to increase the threshold voltage of the cell to a post-program to operate normally. A flash memory device that can recover to a memory cell.

In general, a flash memory device is a nonvolatile memory device that stores memory stably for a long time without a power supply.

Flash memory devices are also similar to electrically erased and programmable read-only memory devices (EEPROMs) in that they can be erased by electrical processing, but EEPROMs are erased one byte at a time. In contrast, since flash memory devices are erased block by block, the operation speed is high.

In addition, the flash memory device is a non-volatile memory device that is continuously powered and can erase data in block units and reprogram it.

Flash memory devices are used to store control codes, such as the BIOS of a PC. This is because, when the BIOS needs to be modified, the flash memory device is written in blocks rather than bytes, and thus easy to modify.

In the flash memory device according to the related art, the overerase phenomenon is that a specific flash memory cell having a threshold voltage of 0.5 V or less after performing an erase operation has a normal flash memory cell having a threshold voltage of 0.5 to 1.5 V. When the threshold voltage is lowered and the flash memory cells sharing the same bit line are programmed, the same phenomenon occurs as the erased by the over erased flash memory cells.

In order to prevent this over erasure, the conventional method cannot read all the currents of all flash memory cells after erasing, so that the flash memory cells of the first upper address sharing the bit line are programmed so that the data value of the flash memory cells cannot be read. It was determined whether the flash memory cell at the lower address was erased according to the reading.

However, there is a problem in that the test time is increased because the specific flash memory cells that are erased are not distributed much.

In addition, when such a problem occurs in a non-test field, there is a problem that there is no solution.

An object of the present invention for solving the above problems is to perform the post program only on the over erased flash memory cells detected using the over erase detection circuit to set the threshold voltage characteristics of the normal cells to the same.

A flash memory device of the present invention for achieving the above object is a flash memory cell array including a plurality of flash memory cells; Mode setting means for setting an operation mode; Sensing amplifying means for checking data of the flash memory cell selected by the verification activation signal output from the mode setting means, sensing and amplifying data of the selected flash memory cell, and outputting data; And sensing the data of the selected flash memory cell to determine whether it is over-erased, controlling the sense amplifying means, and restoring means for restoring when the selected flash memory cell is over-erased.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a flash memory device according to the present invention.

The flash memory device includes a flash memory cell array 2, a mode setting unit 4, a sense amplifier 6, and an over erase detector 8.

The flash memory cell array 2 includes a plurality of flash memory cells, the mode setting unit 4 sets an operation mode, and the sense amplifier 6 has a verification enable signal VES output from the mode setting unit 4. Check the data of the selected flash memory cell, detect and amplify the data CD of the selected flash memory cell, output the output data DOUT, and the over erase detection unit 8 detects and erases the data of the selected flash memory cell. Determine whether or not.

FIG. 2 is a detailed circuit diagram illustrating an example of the over erase detector 8 of FIG. 1.

The over erase detection unit 8 includes a pull-up unit 12, a detection unit 14, an activator 16, and a driver 18. The pull-up unit 12, the detector 14, and the activator 16 are connected in series between the power supply voltage and the ground, and the driver 18 inverts the potential of the common node of the pull-up unit 12 and the detector 14. Drive to output the over erase detection signal OES.

The pull-up unit 12 is constituted by a PMOS transistor PT1 having a gate connected to a ground, the detector 14 is constituted by a PMOS transistor PT2 to which a cell data CD is applied to a gate, and the activator 16 is a mode setting unit 4 at a gate. The NMOS transistor NT1 to which the verification activation signal VES outputted from < RTI ID = 0.0 >) is applied, < / RTI >

Here, the threshold voltage of the PMOS transistor PT2 of the detector 14 is designed to be able to detect the current of the over erased flash memory cell.

If a condition is formed to access the flash memory device from the outside, the mode setting unit 4 sets a mode corresponding to the input condition.

In the erase mode, the selected flash memory cell is erased by applying a gate voltage of -9V to a gate and applying a substrate voltage of + 9V to a substrate.

The mode setting unit 4 then sets a verify mode to check whether the selected flash memory cells are erased.

The over erase detection unit 8 of the present invention detects the erased amount of the flash memory cell preselected in the verify mode to determine whether the over erase is performed. 4 sets the post program mode to recover the erased flash memory cell. In addition, the sense amplifier 6 is disabled so that the output data DOUT is not output.

As described above, since the flash memory device according to the present invention detects an overerased flash memory cell in the verify mode after erasing and recovers it to a post program, the flash memory device detects an over erase even in an actual field and operates normally. It can work.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a block diagram illustrating a flash memory device according to the present invention.

FIG. 2 is a detailed circuit diagram illustrating an example of the over erase detection unit of FIG. 1. FIG.

Claims (8)

A flash memory cell array comprising a plurality of flash memory cells; Mode setting means for setting an operation mode; Sensing amplifying means for checking data of the flash memory cell selected by the verification activation signal output from the mode setting means, sensing and amplifying data of the selected flash memory cell, and outputting data; And And detecting the data of the selected flash memory cell to determine whether it is over erased, controlling the sense amplifying means and recovering when the selected flash memory cell is over erased. . The method of claim 1, wherein the over erase detection means Pull-up means for pulling up the output terminal to a high level; Detection means for varying the potential of the output terminal according to a result of detecting data of the selected flash memory cell and detecting whether or not it is over erased; And And driving means for driving a potential of the output terminal. 3. The flash memory device according to claim 2, wherein said over-erasing detecting means further comprises an activation means activated according to a verification activation signal output from said mode setting means. 4. The flash memory device of claim 3, wherein the activation means comprises an NMOS transistor connected between the detection means and ground and to which the verify activation signal is applied to a gate. 3. The flash memory device of claim 2, wherein the pull-up means comprises a PMOS transistor connected between a power supply voltage and the output terminal and whose gate is grounded. 3. The flash memory device according to claim 2, wherein said detecting means comprises a PMOS transistor to which data of said flash memory cell selected at a gate is applied. The flash memory device of claim 6, wherein the threshold voltage of the PMOS transistor is large enough to sense a current of an over erased flash memory cell. 3. The flash memory device according to claim 2, wherein said driving means comprises a plurality of inverters for driving the potential of said output terminal.