KR20050064202A - Method for forming landing plug in semiconductor device - Google Patents
Method for forming landing plug in semiconductor device Download PDFInfo
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- KR20050064202A KR20050064202A KR1020030095551A KR20030095551A KR20050064202A KR 20050064202 A KR20050064202 A KR 20050064202A KR 1020030095551 A KR1020030095551 A KR 1020030095551A KR 20030095551 A KR20030095551 A KR 20030095551A KR 20050064202 A KR20050064202 A KR 20050064202A
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- landing plug
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000001312 dry etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003472 neutralizing effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 랜딩플러그 형성방법에 관해 개시한 것으로서, 워드라인이 구비된 반도체기판을 제공하는 단계와, 기판 전면에 절연막을 형성하고 나서, 상기 절연막을 선택적으로 식각하여 상기 워드라인 사이의 공간을 노출시키는 랜딩플러그 콘택을 형성하는 단계와, 랜딩플러그 콘택을 포함한 기판 위에 다결정실리콘막을 증착하는 단계와, 소오스로서 내부에 수직 안테나를 다수개 삽입시킨 SSW-FAFAB를 이용하여 상기 다결정실리콘막을 전면식각하여 상기 랜딩플러그 콘택을 매립시키는 랜딩플러그를 형성하는 단계를 포함한다.The present invention relates to a method for forming a landing plug of a semiconductor device, the method comprising: providing a semiconductor substrate having a word line, forming an insulating film on the entire surface of the substrate, and selectively etching the insulating film to between the word lines; Forming a landing plug contact exposing the space, depositing a polysilicon film on the substrate including the landing plug contact, and using the SSW-FAFAB having a plurality of vertical antennas inserted therein as a source to front the polysilicon film. Etching to form a landing plug to bury the landing plug contact.
Description
본 발명은 반도체 소자를 제조하는 기법에 관한 것으로, 더욱 상세하게는 랜딩플러그용 다결정실리콘막의 식각균일도를 양호하게 유지하여 이 후 비트라인용 콘택 CD 및 저항 균일도를 향상으로 디바이스 특성을 향상시킬 수 있는 반도체소자의 랜딩플러그 형성방법을 제공하려는 것이다.The present invention relates to a technique for manufacturing a semiconductor device, and more particularly, to maintain a good etching uniformity of the polycrystalline silicon film for the landing plug to improve the device characteristics by improving the contact CD and resistance uniformity for the bit line afterwards It is to provide a method for forming a landing plug of a semiconductor device.
도 1a 내지 도 1b는 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 공정단면도이다. 1A to 1B are cross-sectional views illustrating a method of forming a landing plug of a semiconductor device according to the related art.
종래기술에 따른 반도체소자의 랜딩플러그 형성방법은, 도 1a에 도시된 바와 같이, 먼저 반도체기판(1) 상에 워드라인(2)을 각각 형성한다. 이때, 상기 워드라인(2)에는, 도면에 도시되지 않았지만, 상부에는 하드마스크가 형성되고, 상기 워드라인 및 하드마스크 측면에는 버퍼산화막 및 절연 스페이서가 차례로 형성된다.In the method of forming a landing plug of a semiconductor device according to the prior art, as shown in FIG. 1A, a word line 2 is first formed on a semiconductor substrate 1. In this case, although not shown in the figure, a hard mask is formed on the word line 2, and a buffer oxide film and an insulating spacer are sequentially formed on the side of the word line and the hard mask.
이어, 상기 결과의 기판 전면에 절연막(3)을 형성한 다음, 상기 절연막을 선택 식각하여 상기 워드라인(2)을 노출시키는 각각의 랜딩플러그 콘택(4)을 형성한다. Subsequently, an insulating film 3 is formed on the entire surface of the resultant substrate, and then the insulating film is selectively etched to form respective landing plug contacts 4 exposing the word line 2.
그런 다음, 상기 랜딩플러그 콘택(4)를 포함한 기판 전면에 다결정 실리콘막(5)을 증착하고 나서, 도 1b에 도시된 바와 같이, 상기 다결정 실리콘막을 에치백(etch back)하여 워드라인(2) 사이의 공간을 채우는 랜딩 플러그(5a)를 형성한다. 이때, 상기 랜딩 플러그(5a)는, 도면에 도시되지 않았지만, 비트라인용 랜딩 플러그 및 스토리지 노드용 랜딩 플러그로 구성된다. Then, a polycrystalline silicon film 5 is deposited on the entire surface of the substrate including the landing plug contact 4, and then, as shown in FIG. 1B, the polycrystalline silicon film is etched back to the word line 2. A landing plug 5a is formed to fill the space therebetween. In this case, although the landing plug 5a is not illustrated in the drawing, the landing plug 5a includes a landing plug for a bit line and a landing plug for a storage node.
그러나, 종래의 기술에서는 랜딩플러그용 다결정 실리콘막을 에치백하는 경우, 이온 또는 전자 등의 하전입자에 의해 식각되기 때문에 원형 결함 등의 변칙결함(anomaly defect)가 발생되며, 뿐만 아니라 다결정실리콘막의 식각 균일성이 양호하지 못한 문제점이 있다. 여기서, 상기 다결정실리콘막의 식각균일도는 식각균일도가 양호해야 랜딩플러그의 손실도 균일하며 이 후 비트라인용 콘택 CD(Critical Dimension) 및 저항 균일도 향상으로 디바이스 특성을 향상시킬 수 있기 때문이며, 특히, 300nm 웨이퍼의 경우 균일도의 중요성이 더욱 크다. However, in the prior art, when the polycrystalline silicon film for landing plug is etched back, since it is etched by charged particles such as ions or electrons, anomaly defects such as circular defects are generated, as well as the etching uniformity of the polycrystalline silicon film. There is a problem that the sex is not good. In this case, the etching uniformity of the polysilicon film must be uniform so that the loss of the landing plug is uniform, and the device characteristics can be improved by improving the contact CD (critical dimension) and resistance uniformity for the bit line, in particular, a 300 nm wafer. In the case of uniformity is more important.
따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 랜딩플러그용 다결정실리콘막의 식각균일도를 양호하게 유지함으로써, 이 후 비트라인용 콘택 CD 및 저항 균일도 향상으로 디바이스 특성을 향상시킬 수 있는 반도체소자의 랜딩플러그 형성방법을 제공하려는 것이다.Accordingly, in order to solve the above problems, an object of the present invention is to maintain a good etching uniformity of the polycrystalline silicon film for the landing plug, thereafter landing of the semiconductor device that can improve the device characteristics by improving the contact CD and resistance uniformity for the bit line It is to provide a plug forming method.
상기 목적을 달성하고자, 본 발명에 따른 반도체소자의 랜딩플러그 형성방법은 워드라인이 구비된 반도체기판을 제공하는 단계와, 기판 전면에 절연막을 형성하고 나서, 상기 절연막을 선택적으로 식각하여 상기 워드라인 사이의 공간을 노출시키는 랜딩플러그 콘택을 형성하는 단계와, 랜딩플러그 콘택을 포함한 기판 위에 다결정실리콘막을 증착하는 단계와, 소오스로서 내부에 수직 안테나를 다수개 삽입시킨 SSW-FAFAB를 이용하여 상기 다결정실리콘막을 전면식각하여 상기 랜딩플러그 콘택을 매립시키는 랜딩플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a landing plug of a semiconductor device according to the present invention includes providing a semiconductor substrate having a word line, forming an insulating film on the entire surface of the substrate, and selectively etching the insulating film to form the word line. Forming a landing plug contact exposing a space therebetween; depositing a polycrystalline silicon film on a substrate including the landing plug contact; and using the SSW-FAFAB having a plurality of vertical antennas inserted therein as a source. And etching the film to form a landing plug to bury the landing plug contact.
(실시예)(Example)
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기로 한다.Hereinafter, a method of forming a landing plug of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a landing plug of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 랜딩플러그 형성방법은, 도 2a에 도시된 바와 같이, 먼저 반도체기판(10) 상에 각각의 워드라인(11)을 형성한다. 이때, 상기 워드라인(11)은, 기존 구조와 동일하게, 상부에는 하드마스크가 형성되고, 상기 워드라인 및 하드마스크 측면에는 버퍼산화막 및 절연 스페이서가 차례로 형성된다.In the method for forming a landing plug of a semiconductor device according to the present invention, as shown in FIG. 2A, first, each word line 11 is formed on a semiconductor substrate 10. At this time, the word line 11, as in the conventional structure, a hard mask is formed on the top, and a buffer oxide film and an insulating spacer are formed in the word line and the hard mask side.
이어, 상기 결과의 기판 전면에 제 1절연막(12)을 형성한 다음, 상기 제 1절연막(12)을 선택식각하여 상기 워드라인(11)들을 노출시키는 각각의 랜딩플러그 콘택(13)을 형성한다. Subsequently, a first insulating layer 12 is formed on the entire surface of the resultant substrate, and then the first insulating layer 12 is selectively etched to form respective landing plug contacts 13 exposing the word lines 11. .
그런 다음, 상기 랜딩플러그 콘택(13) 구조 전면에 다결정실리콘막(14)을 증착한다. 이때, 상기 다결정실리콘막(14)은 이후의 공정에서 랜딩플러그를 형성하기 위한 것이다.Then, a polysilicon film 14 is deposited on the entire surface of the landing plug contact 13. In this case, the polysilicon film 14 is for forming a landing plug in a subsequent process.
이후, 도 2b에 도시된 바와 같이, 상기 다결정실리콘막을 에치백을 실시하여 도전플러그(14a)를 형성한다. 이때, 상기 다결정실리콘막의 에치백 공정은 소오스로서 안정한 표면 웨이퍼플라즈마에 의한 빠른 원자빔(Stable Surface Wave-Plasma Assisted Fast Atom Beam:이하, SSW-PAFAB라 칭함)을 사용하며, 이때 플라즈마 내부에 안테나를 삽입한 수개의 수직 안테나들의 시리즈를 적용한다. 여기서, 상기 안테나를 적용하는 이유는 안테나 삽입효과로 플라즈마상태에서 강한 전기장의 유도가 형성가능하기 위함이다. 즉, SSW가 커다란 영역 플라즈마(Large Area Plasma)효과도 있지만 이보다도 훨씬 강력하고 균일한 플라즈마를 형성하기 위해 수직안테나에 의해 보완하고자 하기 위함이다. 상기 수직안테나는 직선으로 형성된 안테나 상호간에 거리도 조절할 수 있어 균일도 향상을 위한 콘트롤(control)도 가능하다. 더불어 상부에 소오스파워 전극과 플라즈마 외장(sheath) 후방에 캐버티(cavaty)를 형성함으로서 식각비에 보다 피크한 부분을 줄일 수 있어 강력한 균일도 식각장치를 형성할 수 있다. 특히, 캐버티도 플라즈마 형성되는 부분의 피크 발생가능지역에 적절히 배치 및 조절할 수 있어 더욱 균일한 식각장치가 된다.Thereafter, as illustrated in FIG. 2B, the polysilicon film is etched back to form a conductive plug 14a. At this time, the etch back process of the polysilicon film uses a stable surface wave-plasma assisted fast atom beam (hereinafter referred to as SSW-PAFAB) by a stable surface wafer plasma as a source, and at this time, an antenna is Apply a series of inserted vertical antennas. Here, the reason for applying the antenna is to be able to form a strong electric field in the plasma state by the antenna insertion effect. In other words, although SSW has a large area plasma effect, it is intended to be supplemented by a vertical antenna to form a more powerful and uniform plasma. The vertical antenna can also adjust the distance between the antennas formed in a straight line, it is also possible to control (control) to improve uniformity. In addition, by forming a cavity behind the source power electrode and the plasma sheath, the peak portion of the etching ratio can be reduced, thereby forming a strong uniform etching device. In particular, the cavity can also be properly disposed and adjusted in the peak generation area of the portion where the plasma is formed, resulting in a more uniform etching device.
도 3은 본 발명에 따른 SSW-PAFAB를 적용시켜 건식식각공정을 진행시키기 위한 건식식각장비의 개략도이다.Figure 3 is a schematic diagram of a dry etching equipment for proceeding the dry etching process by applying the SSW-PAFAB according to the present invention.
상기 SSW-PAFAB의 원리에 대해 알아보면, 도 3에 도시된 바와 같이, 애노드(anode)(10)와 캐소드(cathode)(11) 사이에 전압을 걸어주고 헬리콘 소오스(helicon source)에 의해 캐소드 튜브 내의 전자가 진동(oscillation)되어 고밀도 플라즈마가 발생된다. 이때, 이온은 캐소드 끝쪽에 캐필러리 홀(capillary)(12)을 통과할때 가속화되며, 이로써 가스분자와 차지 충돌(collision)로 중화(neutralization)된다. 따라서, 이러한 원리에 의해 캐필러리 홀(12)을 통과한 중성입자들이 FAB소오스가 되어 다결정실리콘막을 식각하게 된다.Referring to the principle of the SSW-PAFAB, as shown in FIG. 3, a voltage is applied between an anode 10 and a cathode 11 and a cathode is formed by a helicon source. Electrons in the tube are oscillated to generate a high density plasma. At this time, ions are accelerated as they pass through the capillary hole 12 at the cathode end, thereby neutralizing the gas molecules with charge collision. Accordingly, by this principle, the neutral particles passing through the capillary hole 12 become FAB sources to etch the polycrystalline silicon film.
도 3에서, 미설명된 도면부호 13은 가스주입관을, 도면부호 14는 헬리컬 코일(helical coil)을, 도면부호 15는 마그네트(magnet)를, 도면부호 16은 DC 디스차지 셀(discharge cell)을, 그리고 도면부호 17은 헬리콘 셀(helicon cell)을 각각 나타낸 것이다.In FIG. 3, reference numeral 13 denotes a gas injection pipe, reference numeral 14 denotes a helical coil, reference numeral 15 denotes a magnet, reference numeral 16 denotes a DC discharge cell. And, reference numeral 17 represents a helicon cell (helicon cell), respectively.
이어, 도 2c에 도시된 바와 같이, 랜딩플러그를 포함한 기판 전면에 제 2절연막(15)을 증착하고 나서, 상기 제 2절연막(15)을 선택적으로 식각하여 랜딩플러그(14a)를 노출시키는 콘택(16)을 형성한다. Subsequently, as illustrated in FIG. 2C, after the second insulating layer 15 is deposited on the entire surface of the substrate including the landing plug, the second insulating layer 15 is selectively etched to expose the landing plug 14a. 16).
한편, 도면에 도시되지 않았지만, 이후의 공정에서 상기 콘택(16)을 통해 랜딩플러그는 비트라인 또는 캐패시터의 스토리지노드 전극와 전기적으로 연결된다.Although not shown in the drawings, the landing plug is electrically connected to the storage node of the bit line or the capacitor through the contact 16 in a subsequent process.
이상에서와 같이, 본 발명은 랜딩플러그용 다결정실리콘막을 에치백하는 경우, FAB효과에 의해 플라즈마에 의해 발생된 전하들이 랜딩플러크 콘택 통과시 원자 변화로 인해 원형결함을 방지할 수 있고, 또한 입자들의 양적인 증가와 커다란 영역의 플라즈마효과로 식각능력이 더욱 활발하며 웨이퍼 전체 균일도도 향상된다.As described above, when the polycrystalline silicon film for the landing plug is etched back, the charges generated by the plasma by the FAB effect can prevent the circular defect due to the atomic change when passing through the landing plug contact, and also the particles Due to the quantitative increase of the field and the plasma effect of the large area, the etching ability is more active and the overall uniformity of the wafer is also improved.
따라서, 이후 제 2절연막을 증착하고 랜딩플러그를 노출시키는 콘택을 형성하는 경우, 콘택의 일정한 높이(즉, 랜딩플러그에서 제 2절연막 표면까지)로 만들 수 있으므로, 웨이퍼 전체의 CD도 균일할 뿐만 아니라 식각타겟도 정확하여 콘택저항을 균일하게 만들어 디바이스 특성을 향상시킬 수 있다. Therefore, in the case of forming a contact that deposits the second insulating film and exposes the landing plug, it is possible to make the contact at a constant height (that is, from the landing plug to the surface of the second insulating film), so that the CD of the entire wafer is not only uniform. The etching target is also accurate, which makes the contact resistance uniform and improves device characteristics.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1b는 종래기술에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 공정단면도.1A to 1B are cross-sectional views illustrating a method for forming a landing plug of a semiconductor device according to the related art.
도 2a 내지 도 2c는 본 발명에 따른 반도체소자의 랜딩플러그 형성방법을 설명하기 위한 공정단면도.2A to 2C are cross-sectional views illustrating a method of forming a landing plug of a semiconductor device according to the present invention.
도 3은 본 발명에 따른 SSW-PAFAB를 적용시켜 건식식각공정을 진행시키기 위한 건식식각장비의 개략도.Figure 3 is a schematic diagram of a dry etching equipment for proceeding the dry etching process by applying the SSW-PAFAB according to the present invention.
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| US10923401B2 (en) | 2018-10-26 | 2021-02-16 | International Business Machines Corporation | Gate cut critical dimension shrink and active gate defect healing using selective deposition |
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