KR20050063653A - An transmitter/receiver for arq, and a method thereof - Google Patents

Abstract

The present invention relates to an apparatus for transmitting and receiving an automatic retransmission request (ARQ) for correcting an error in an OFDM / TDMA terminal and generating a frame at high speed.

An ARQ transmission / reception apparatus of an OFDM / TDMA terminal system according to the present invention includes a central processing unit that transmits and receives a data packet with an upper block in software; An ARQ transceiver for receiving data packets, dividing the data packets into predefined fragment sizes, storing the fragments, generating frames according to the fragment information, and transmitting and receiving ARQs in hardware while managing whether ARQs are retransmitted; An interface buffer for storing data transmitted between the CPU and the ARQ transceiver; And a fragment buffer for storing fragments generated by the ARQ transceiver.

According to the present invention, it is possible to meet the timing requirements for frame generation required by a high-speed OFDM / TDMA terminal, to generate a high-speed frame to transmit high-speed data, and to provide an error correction function. have.

Description

Automatic retransmission request transmission and reception apparatus and method thereof {An transmitter / receiver for ARQ, and a method approximately}

The present invention relates to an apparatus for transmitting and receiving an automatic retransmission request, and more particularly, to an OFDM / TDMA terminal, in which an error in a wireless data communication is corrected and an automatic retransmission request for high-speed frame generation is provided. Hereinafter, the present invention relates to an apparatus for transmitting and receiving and a method thereof.

Error control methods when frames are lost or corrupted during data transmission in a wireless environment include basic stop-and-wait ARQ, go-back-N continuous ARQ, and selective-repeat continuous ARQ) and the like, and a hybrid ARQ (hybrid ARQ) method has recently been used.

The basic ARQ method waits for an acknowledgment message (ACK) after one frame transmission, and the receiving side sends an acknowledgment message (ACK) only when it is properly received, and sends a NAK (negative-ACK) message when an error occurs in the frame. It becomes. If the frame is not received because it is destroyed, the receiver does not send any signal, and when the signal does not come after a certain time, the frame is retransmitted, which has the advantage of being simple and simple to implement, but with a long waiting time. As a result, the transmission efficiency is reduced.

In addition, the continuous ARQ method transmits a series of frames determined by the window size, and when an error is found in any one frame at the receiving end, sends a NAK message for the frame, after which the frame is not received, and the transmitting side receives the NAK. Retransmit all frames after the message.

In addition, the selective ARQ scheme is a modified scheme of the continuous ARQ scheme in which only the frame in which the NAK message is received is retransmitted. However, the selective ARQ scheme has an advantage of good transmission efficiency. Overhead due to the storage location to store may occur.

As a prior art, Korean Patent Application No. 2000-71225 (Application Date: Nov. 28, 2000) discloses an invention entitled "High speed data transmission apparatus and control method thereof in a mobile communication system". The present invention relates to a high speed data transmission apparatus and a method of controlling the same, which enable reliable high speed data transmission without deterioration of data rate by using a convolutional encoder and an ARQ scheme.

Specifically, the present invention combines a convolutional encoder and an ARQ scheme to reduce transmission rate and to provide reliable data transmission, and thus can be applied to various high-speed communication systems other than CDMA technology. The convolutional encoder of the layer and the ARQ scheme of the link layer are combined to improve the transmission rate and provide an error correction function.

On the other hand, as a prior art, International Patent Application No. PCT / IB2001 / 00618 (International Application Date: April 17, 2001) discloses the invention entitled "cooperation of ARQ protocol in the physical layer and link layer for wireless communication."

Specifically, the present invention is to increase the error correction function and reduce the overhead through the improvement of the existing protocols and algorithms, by improving the algorithm that provides both automatic error recovery operation in the physical layer and link layer structure It provides robust operation over the radio link and also provides ARQ function with low additional overhead.

Meanwhile, as a prior art, Korean Patent Application No. 2002-49754 (Application Date: Aug. 22, 2002) discloses an invention named "ARQ transmitter, ARQ receiver, and ARQ method", and this prior invention has high signaling overhead. The present invention relates to a synchronous feedback transmission method capable of adding flexibility without implying a disadvantage of an asynchronous transmission method known to have a.

Specifically, the present invention is to reduce the signaling overhead for the transmission of ACK and NAK response messages in the asynchronous transmission scheme, the tail bit used in the Forward Error Correction (FEC) block H is also used as the identification number of the frame required in the ARQ scheme to reduce the amount of additional data. That is, this prior invention provides a transmitter, a receiver, and a method that allows flexible timing of ACK / NAK without signaling overhead, thereby enabling the operation of different kinds of receivers having low processing time as well as high processing time.

Meanwhile, the above-described ARQ algorithm may be implemented in hardware or in software. For example, the selective ARQ scheme is used in a system such as WCDMA, and implemented in software in the RLC layer. In addition, in a system using a simple structure ARQ is implemented in hardware.

However, in the related art, when a mixed ARQ scheme and a continuous ARQ scheme are implemented in a high-speed OFDM / TDMA terminal, it is difficult to satisfy the timing requirements for generating the frame when implemented in software as described above. . Of course, although the receiver of a high-speed OFDM / TDMA terminal has a relatively low timing requirements, traditionally requires a lot of memory for the ARQ processing, it can be obtained by software implementation.

In addition, the requirements for a given frame generation time in a high-speed OFDM / TDMA terminal is different according to the frame period, the time becomes smaller as a high-speed OFDM / TDMA system, and the entire frame period is again a downlink frame ( It may be divided into a downlink frame time and an uplink frame time.

When data is to be received and transmitted during the downlink frame time, the data should be generated by transmitting information on the uplink frame to generate and transmit the uplink frame. At this time, the actual frame time available to the actual terminal is only about 1 to 3 ms except for the transmission and reception time in the modem, which becomes smaller as a high speed system. In this case, if the ARQ and the frame generator are implemented in software, it is difficult to meet the timing requirements.

An object of the present invention for solving the above problems is to meet the timing requirements for frame generation required by a high-speed OFDM / TDMA terminal, automatic retransmission request transmission and reception that can generate a high-speed frame to transmit high-speed data An apparatus and a method thereof are provided.

In addition, another object of the present invention is to provide an automatic retransmission request transmission and reception apparatus that can be implemented in hardware in the FPGA of the OFDM / TDMA terminal to provide an error correction function in a wireless data communication and at the same time provide a high-speed frame generation function; It is to provide a method.

In addition, another object of the present invention is to provide an error correction function in a wireless data communication, while facilitating the implementation in the receiving portion where the timing requirements are relatively easy, and at the same time reduce the memory usage in the FPGA or external hardware specifications. An automatic retransmission request transmitting and receiving device and a method thereof are provided.

In addition, another object of the present invention is to provide an automatic retransmission request transmission and reception apparatus and method capable of reducing excessive timer overhead when implementing an optional ARQ scheme in software.

As a means for achieving the above object, the automatic retransmission request transmission and reception apparatus according to the present invention,

A central processing unit that transmits and receives data packets with an upper block in software;

An ARQ that receives the data packet, divides and stores the packet in a predefined fragment size, generates a frame at the time of frame generation according to the stored fragment information, and transmits and receives the ARQ in hardware while managing whether the ARQ is retransmitted. A transceiver;

An interface buffer for storing data transmitted between the CPU and the ARQ transceiver; And

Fragment buffer for storing the fragments generated by the ARQ transceiver

There is a feature configured to include.

The data packet may be a service data unit (SDU) for receiving and storing the data from the upper block or a protocol data unit (PDU) processed with a media access control (MAC).

The apparatus may further include a frame buffer for storing uplink frame data to be transmitted from the terminal to the base station, and a downlink buffer for storing downlink data transmitted from the base station to the terminal.

Here, the CPU includes a program storage unit for implementing MAC transmitter software and MAC receiver software, wherein the MAC transmitter software receives an SDU from the upper block and stores the SDU in the interface buffer. It receives the PDU from the ARQ transceiver and performs the ARQ reception and MAC PDU processing.

Here, the ARQ transceiver,

A packet divider which receives the SDU from the central processing unit and divides the fragment into fragments having a fixed size;

Each time a new packet is stored in the fragment buffer from the packet divider, a tail pointer is updated, the state of the current fragment buffer is reported to the frame generator, and the head pointer is updated when the fragment buffer is transmitted. Incoming address manager;

A frame generator for receiving information on a current fragment from the address manager and generating a frame using the fragment information;

A retransmission manager for storing the fragment information, increasing the head pointer of the fragment buffer, moving the fragment information over a time stamp value to a retransmission buffer, and discarding fragment information over a predetermined number of retransmissions;

A receiver block for transmitting the remaining PDUs excluding the ARQ response message among the MAC PDUs received from the base station to the CPU; And

ARQ response buffer that receives and stores an ARQ response message from the receiver block and delivers it to the retransmission manager.

It is configured to include.

The management message may further include a management message processing block that receives and stores a management message from which the fragment is not allowed, from the central processing unit, and delivers the management message to the frame generator.

Here, the frame generator receives the information on the current management message from the management message processing block, generates a frame using the information, and the frame generator stores the generated frame in the frame buffer. Afterwards, the fragment information for the ARQ traffic is delivered to the retransmission manager. In addition, the frame generator is implemented in hardware in the FPGA, characterized in that to perform the frame generation in hardware using the fragment information.

Here, the retransmission manager includes an ARQ buffer for storing fragment information, and the retransmission manager uses the ARQ ACK message transmitted from the receiver block to check whether each message in the ARQ buffer is correctly transmitted. . The retransmission manager may store a transmission ARQ header having an address of a currently stored buffer and a stored time stamp value in the ARQ buffer in case of an ARQ supported traffic flow.

In this case, the retransmission manager periodically searches for the stored transmission ARQ header to update a time stamp value, and stores the transmission ARQ header having a time stamp value equal to or greater than the retransmission time in the retransmission buffer. In addition, if there is an ARQ response message in the ARQ response buffer, the retransmission manager searches for the transmission ARQ header buffer using the ARQ response buffer, checks whether the ACK response is received, and advances the transmission window value according to the ARQ scheme. It is characterized by erasing the contents.

The packet divider may cause the address manager to update the stored address value.

The address manager may include a circular queue in which a tail pointer and a head pointer are updated, and the address manager does not store a memory address value of 10 bits or more, and only the upper part of the memory address value is a head pointer. And a tail pointer.

Here, the transmitting software stores the SDU in the interface buffer between the CPU and the ARQ transceiver before the frame generation request.

On the other hand, as another means for achieving the above object, the ARQ transmission and reception method according to the present invention, in the ARQ transmission and reception method of the terminal system of the OFDM / TDMA method,

a) storing an SDU transmitted from an upper block in a corresponding buffer;

b) if the capacity of the buffer is sufficient, storing the SDU in an interface buffer;

c) if ARQ is enabled, determining whether the capacity of the fragment buffer is sufficient;

d) dividing the SDU if the capacity of the fragment buffer is sufficient;

e) storing the divided packet at a corresponding address, and updating an address manager according to an address change of the fragment;

f) generating a frame by determining whether there is a frame generation request; And

g) transmitting and receiving the ARQ according to the frame

There is a feature consisting of.

The fragment information may be a sequence number, a time stamp, a number of retransmissions, or a stored address.

Wherein step d) comprises: calculating a storage address pointer value; And dividing the SDU into a fixed size.

Here, the step d) may include inserting a value for the fragment storage address into a queue designated by a tail pointer of a circular queue after fragment fragmentation; Storing the value in an address manager; And obtaining the fragment based on the head pointer of the circular queue when the frame generation request is made.

Here, the step f) may include determining whether there is the frame generation request and receiving current fragment information from an address manager and a retransmission manager when the frame generation request is received; Determining whether there is a fragment to transmit, if there is a fragment to transmit, fetching a fragment from the fragment buffer, and generating a PDU (Protocol Data Unit) packet; Storing the fragment information in the retransmission manager; Determining whether the fragment exists in a retransmission buffer, and if there is the fragment, retrieving fragment information from the retransmission buffer; And generating a PDU packet by importing a corresponding fragment from the fragment buffer.

Here, the step f) may include: generating the frame in hardware and storing information on some bits of the head pointer for the information on the transmitted frame; Periodically updating the time stamp value; If the frame information is equal to or greater than a predetermined value, storing the information again in the retransmission buffer; And retransmitting a fragment using the frame information when generating the frame.

Accordingly, according to the present invention, a hardware frame generator, a hardware ARQ transmitter, a software ARQ receiver, and the like are configured in an OFDMA / TDMA terminal, and data transmitted from an upper block is transmitted and partitioned by hardware. In addition to performing the ARQ operation, the software receiver forwards the PDU to a higher level and processes it in a software processing block, thereby providing OFDMA / TDMA with high-speed frame generation and error correction at the terminal, while at the same time having a low timing requirement. The transceiver can be easily implemented.

Hereinafter, with reference to the accompanying drawings will be described in detail an automatic retransmission request transmission and reception apparatus and method according to an embodiment of the present invention.

Embodiments of the present invention include a hardware frame generator, a hardware ARQ transmitter, and a software ARQ receiver of an OFDM / TDMA terminal.

1 is a frame configuration diagram of a typical OFDM / TDMA system, and is divided into a MAP 110, a downlink data section 120, and an uplink data section 130.

In an example OFDM / TDMA terminal such as 802.16, each frame is divided into an uplink period 130 and a downlink period 120. The base station transmits data through the downlink period 120, and each terminal grasps data corresponding to itself through downlink map data located at the front of each period. Data can be received.

In addition, the terminal that wants to transmit data to the base station similarly checks whether there is a bandwidth allocated to itself using uplink map data, and if there is an allocated bandwidth, You can send a frame.

In this case, the entire frame period is divided into a downlink period and an uplink period. At this time, the downlink period is longer than the uplink period due to the asymmetry of the most common web data. However, the higher the speed, the shorter the frame period for the terminal to transmit to the base station.

On the other hand, unlike the base station in the OFDM / TDMA system, the terminal requires a bandwidth whenever there is data to be transmitted, and can transmit data within the range allowed by the base station.

Furthermore, the difficulty of uplink timing requirements is that the bandwidth allocation for each terminal is known after every downlink frame reception, and also receiving uplink map data containing information about the uplink frame. Because you can see.

Therefore, in a high-speed TDMA system, the frame period is in units of seconds, and the time required to grasp the structure of the frame and to generate and transmit the frame accordingly is very short.

In general, when such a system is configured in software, it is difficult to meet the timing requirements, especially with higher speed TDMA systems. This is because a large amount of time is generally required to transmit and receive data to and from external I / O devices including the central processing unit and external memory.

Therefore, if the data is downloaded to the hardware before the request for generating the frame, the data can be transmitted at higher speed.

2 is a diagram illustrating a configuration of an OFDM / TDMA terminal having a hardware ARQ transmitter, a software ARQ receiver, and a hardware frame generator according to an embodiment of the present invention.

2, the ARQ transmission and reception apparatus according to an embodiment of the present invention, the central processing unit 210 for transmitting and receiving software packets and the upper block; FPGA that receives the data packet, divides it into a predefined fragment size, stores it, generates a frame at the time of frame generation according to the stored fragment information, and transmits and receives the ARQ in hardware while managing whether to retransmit the ARQ. 230; An interface buffer 220 for storing data transmitted between the central processing unit 210 and the FPGA 230; And a fragment buffer 240 for storing fragments generated by the FPGA 230. A frame buffer 260 for storing uplink frame data to be transmitted from the terminal to the base station; And a downlink buffer 250 for storing downlink data transmitted from the base station to the terminal.

Here, the data packet may be a service data unit (SDU) for receiving and storing the data from the upper block or a protocol data unit (PDU) processed with media access control (MAC).

The CPU 210 includes a program storage unit for implementing the MAC transmitter software 211 and the MAC receiver software 212, wherein the MAC transmitter software 211 receives the SDU from the upper block to receive the interface buffer. In operation 220, the MAC receiver software 212 receives the PDU from the FPGA 230 to perform the ARQ reception and MAC PDU processing.

As shown in FIG. 2, the embodiment of the present invention can be designed in the hardware part and the software part in consideration of the timing requirements, memory requirements, and ease of implementation required for high-speed TDMA.

First, the transmitting end implements the user data transmission function in hardware, and the software simply transmits the data transferred from the upper layer to the hardware before frame generation.

On the other hand, since the receiving software has a weak timing requirement, most of the functions are handled by the software, and only a simple process is performed by the hardware.

On the other hand, for ease of data processing in hardware, all data transmitted to hardware is divided into fixed fragments of a certain size and stored in a separate fragment buffer (240). At this time, the uplink frame to be transmitted from the terminal to the base station is stored in the frame buffer 260. Typically, datagrams are encapsulated and transmitted in physical network frames. The maximum length of a frame that can actually be transmitted on a physical network is called the maximum transmission unit of that network, or MTU, and each physical network has a different MTU. Because of this, large datagrams must be sent separately for the networks with the smallest MTU. The divided datagrams are called fragments, or fragments, each of which has a fragment header.

3 is a diagram illustrating a software structure in a central processing unit having a transmitter software and a receiver software according to an embodiment of the present invention. For convenience of description, the software structure is implemented by a program including software, a buffer, and a processor. To be considered.

2 and 3, since the processing method of the ARQ receiver follows a general ARQ implementation algorithm, a detailed description thereof will be omitted.

First, the MAC transmit / receive software 320 shown in FIG. 3 is composed of the MAC transmit software 211, the MAC receive software 212, and the driver 340 shown in FIG.

The MAC transmitter software 211 may be composed of an SDU buffer 321, a management buffer 322, and a management message / SDU processing block 323, and simply transmits data transmitted from the upper block 310 to the central processing unit 210. ) And the interface buffer 220 between the FPGA 230 and inform the FPGA 230 of the interface buffer 220. That is, as described above, the transmitting end software 211 simply functions to transfer the data transmitted from the upper layer to the hardware before generating the frame. In addition, the transmitter software 211 stores the SDU in the interface buffer 220 before the frame generation request, but the fragment for the SDU is divided in hardware.

In addition, the MAC receiving software 212 is composed of a receiving buffer 331, ARQ receiver and MAC PDU processor 332 and MAC PDU buffer 333, as described above, because the receiving end is a weak timing requirements Most of the functionality is done in software, and the hardware side is just a simple process.

4 is a diagram illustrating a configuration of an FPGA having a hardware ARQ transmitter and a frame generator according to an embodiment of the present invention, and the ARQ transceiver according to the embodiment of the present invention is a field programmable gate array (FPGA). In hardware).

As shown in FIG. 4, in an FPGA 230 having a hardware ARQ transmitter and a frame generator according to an embodiment of the present invention, first, a data packet is accessed by a packet divider 411 before a current frame generation point. The data packet, which is stored in the interface 220 between the central processing unit 210 and the FPGA 230, may be divided into fragment sizes predefined by the packet divider 411 to be fragmented. It is stored in the buffer 240.

At this time, a subheader including a sequence number and a fragment length is generated and stored in the fragment buffer 240.

The frame generator 418 receives a request for frame generation, receives the currently transmittable data information to the address manager 415 and the management message processing block 413 to generate a frame.

The traffic receiver of the receiver block 414 receives the ARQ response message, stores the ARQ response message in the ARQ buffer 416-1, and notifies the retransmission manager 416. In this case, the retransmission manager 416 periodically searches for a transmission ARQ header stored in the ARQ buffer 416-1 to update the time stamp value, and if there is a transmission ARQ header having a time stamp value longer than the retransmission time, retransmits it. Move to buffer 417-1.

When there is an ARQ response message in the ARQ response buffer 417, the retransmission manager 416 searches for each header in the ARQ buffer and checks whether the ACK response is received. The fragment received the corresponding ACK is included in the ARQ buffer. Deletes the header of the fragment and passes the result to the address manager 415 to update the address management pointer, that is, the head pointer, to the fragment buffer 240.

Specifically, referring back to FIG. 4, the FPGA 230 according to an embodiment of the present invention may include a packet divider 411, a fragment block 412, a management message processing block 413, a receiver block 414, and an address. Manager 415, retransmission manager 416, ARQ response buffer 417, and frame generator 418.

The packet divider 411 receives the SDU from the central processing unit 210 and divides the fragment into fragments having a fixed size. At this time, the packet divider 411 causes the address manager 415 to update the stored address value.

The address manager 415 receives a tail pointer every time a new packet is stored in the fragment buffer 240 from the packet divider 411, and updates the state of the current fragment buffer to the frame generator 418. The head pointer is updated when the fragment buffer 240 is transmitted.

In addition, the address manager 415 includes a circular queue in which a tail pointer and a head pointer are updated. Also, the address manager 415 does not store a memory address value of 10 bits or more and only the upper part bits of the memory address value are used as the head pointer and the tail pointer. Will be used.

The frame generator 418 receives the information on the current fragment from the address manager 415 and generates a frame using the fragment information. The frame generator 418 stores the generated frame in the frame buffer, and then transfers fragment information on ARQ traffic to the retransmission manager 416, wherein the frame generator 418 is configured to execute the FPGA 230. In hardware), frame generation is performed in hardware using the fragment information. Herein, the fragment information may be a sequence number, a time stamp, a retransmission number, or a stored address.

The retransmission manager 416 stores the fragment information, increases the head pointer of the fragment buffer 240, moves the fragment information exceeding the time stamp value to the retransmission buffer 417-1, and a predetermined number of retransmissions. Fragment information passed to is discarded. In addition, the retransmission manager 416 includes an ARQ buffer 416-1 storing fragment information, and the retransmission manager 416 uses the ARQ ACK message transmitted from the receiver block 414 to perform the ARQ. Each message in the buffer 416-1 is checked for correct transmission.

In addition, the retransmission manager 416 stores a transmission ARQ header having an address of a currently stored buffer and a stored time stamp value in the ARQ buffer 416-1 in the case of an ARQ supported traffic flow.

In addition, the retransmission manager 416-1 periodically searches for the stored transmission ARQ header to update a time stamp value, and stores the transmission ARQ header having a time stamp value longer than the retransmission time in the retransmission buffer 417-1. come.

In addition, if there is an ARQ response message in the ARQ response buffer 417, the retransmission manager 416 searches for the transmission ARQ header buffer using the ARQ response message and checks whether the ACK response is received. This will advance the value and clear the contents of that buffer.

The receiver block 414 transfers the remaining PDUs except the ARQ response message among the MAC PDUs received from the base station to the CPU 210. That is, the traffic receiver of the receiver block 414 forwards the remaining data packets except for the ARQ response message to the CPU 210, and also performs the MAC reception and the MAC PDU processing with the software fragment recombination function. The receiving end software 212 recombines the fragments according to the ARQ scheme and delivers the fragments to the higher block 310.

The ARQ response buffer 417 receives and stores an ARQ response message from the receiver block 414 and delivers the ARQ response message to the retransmission manager 416.

The management message processing block 413 receives and stores a management message for which the fragment is not allowed from the CPU 210, and transmits the management message to the frame generator 418. In this case, the frame generator 418 receives the information on the current management message from the management message processing block 413 and generates a frame using this information.

5 is a fragment buffer management diagram using a circular queue according to an embodiment of the present invention, in which a packet divider 411, an address manager 415, and a frame generator 418 are involved in managing the fragment buffer 240. At this time, the buffer management indicates that the circular queue method is used.

Referring to FIG. 5, the fragment buffer 240 must be stably accessed by the packet divider 411 and the frame generator 418 at the same time, and must have integrity in memory management. That is, the fragment generator 418 and the fragment consumer should be regarded as having the same memory management address, and for this purpose, a circular queue type memory management is required.

As shown in FIG. 5, the packet divider 411 receives data from the central processing unit 210, divides and stores the data into a predetermined size, and updates only a tail pointer in the address manager 415. Done.

The frame generator 418 consumes fragments starting from a head pointer to generate a frame, and transmits a result value to the address manager 415 to update the fragment.

Therefore, the head pointer is updated only by the frame generator 418, and the tail pointer is updated by the packet divider 411, thereby maintaining memory consistency in the fragment buffer 240.

6 is a diagram illustrating an internal process of a hardware ARQ transmitter and a frame generator according to an embodiment of the present invention.

In order to reduce the memory consumption for the ARQ process, it indicates that the retransmission manager 416 stores and manages a header having only minimum information about the fragment, not the entire fragment currently transmitted.

First, the frame generator 418 transmits a fragment of the fragment buffer 240, and then transfers the information about the fragment generator 240 to the retransmission manager 416.

The retransmission manager 416 receives a current time-stamp value, a sequence number, and a storage address value of the fragment buffer 240 from the frame generator 418. Manage storage.

Next, after storing the storage address value, the retransmission manager 416 periodically increases the time stamp value, and the fragment information having a predetermined value or more from the ARQ buffer 416-1 to the retransmission buffer 417. -1).

In addition, the frame generator 418 generates a frame by referring to the contents of the retransmission buffer 417-1 in the retransmission manager 416 as well as the information from the address manager when the next frame is generated.

In addition, the information on the transmitted retransmission buffer 417-1 is stored in the ARQ buffer 416-1 of the retransmission manager 416 again, and at this time, the value of the retransmission counter is increased and is equal to or greater than a predetermined value. If it is thrown away.

In addition, the receiver block 414 transmits ARQ feedback information to the ARQ response buffer 417, and also transmits MAC PDU information excluding the ARQ feedback information to the uplink buffer 250.

7A and 7B illustrate an example of a frame generation process according to an exemplary embodiment of the present invention, which is an example of a frame generation process having the above-described structure.

Referring to FIGS. 7A and 7B, a frame generation process according to an exemplary embodiment of the present invention, which is divided into processes in the transmitter software 211, the packet divider 411, and the frame generator 418, will be described.

First, referring to FIG. 7A, when the SDU (Service Data Unit) is transmitted from an upper block (S701), the transmitting end software 211 stores the SDU in the corresponding SDU buffer 321 (S702). It is determined whether or not the capacity of the buffers in the CPU 210 and the FPGA 230 is sufficient (S703).

Next, if the capacity of the buffers is sufficient, the SDU is stored in the interface buffer 220 (S704).

Next, the packet splitter 411 determines whether the ARQ is enabled (S705), and if the ARQ is not enabled, access the non-ARQ enable (S706), but the ARQ is enabled. In this case, it is determined whether the capacity of the fragment buffer 240 is sufficient (S707). If the capacity of the fragment buffer 240 is not sufficient, the packet divider 411 is suspended (S708).

Next, when the capacity of the fragment buffer 240 is sufficient, the storage address pointer value is calculated (S709), and the SDU is divided into fixed sizes (S710).

Next, the divided packet is stored at the corresponding address (S711), and the address manager 415 is updated according to the fragment address change (S712).

Next, referring to FIG. 7B, the frame generator 418 determines whether there is a frame generation request (S713), and if there is the frame generation request, the current fragment from the address manager 415 and the retransmission manager 416. Information is received (S714).

Next, it is determined whether there is a fragment to be transmitted (S715). If there is the fragment to be transmitted, the fragment is taken from the fragment buffer 240, and a PDU (Protocol Data Unit) packet is generated (S716).

Next, a current sequence number, a fragment storage address, and the like are stored in the retransmission manager 416 (S717), and thereafter, it is determined whether the fragment exists in the retransmission buffer 417-1 (S718), and the fragment is present. In this case, the frame generator 418 obtains fragment information from the retransmission buffer 417-1, obtains the fragment from the fragment buffer 240, and generates a PDU packet (S719).

As a result, according to the embodiment of the present invention, the hardware of the frame generator 418 and the ARQ transmitter 231 for high-speed frame generation, and the software of the PDU processor and the ARQ receiver 332 ease of implementation and ease of software implementation. It is to provide an apparatus and method that can increase the.

While the invention has been shown and described in connection with specific embodiments thereof, it will be appreciated that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.

According to the present invention, an uplink frame can be generated at high speed in a high-speed OFDM / TDMA terminal of several microseconds or less.

In addition, according to the present invention, an ARQ transmitter for error correction may be implemented in hardware, and a high speed frame may be generated by processing not only a frame of initial transmission but also a frame to be retransmitted by hardware.

In addition, according to the present invention, it is possible to maintain the ARQ transmitter with a small memory requirement, and by implementing the ARQ receiver in software, it is possible to reduce the memory usage of the receiving end in the FPGA and increase the ease of implementation.

1 is a frame configuration diagram of a typical OFDM / TDMA system.

2 is a diagram illustrating a configuration of an OFDM / TDMA terminal having a hardware ARQ transmitter, a software ARQ receiver, and a hardware frame generator according to an embodiment of the present invention.

3 is a diagram illustrating a software structure in a central processing unit having a transmitter software and a receiver software according to an embodiment of the present invention.

4 is a diagram illustrating a configuration of an FPGA having a hardware ARQ transmitter and a frame generator according to an embodiment of the present invention.

5 is a fragment buffer management diagram by a circular queue according to an embodiment of the present invention.

6 is a diagram illustrating an internal process of a hardware ARQ transmitter and a frame generator according to an embodiment of the present invention.

7A and 7B illustrate an example of a frame generation process according to an embodiment of the present invention.

Claims (25)

In an automatic repeat request (ARQ) transmission / reception apparatus of an orthogonal frequency division multiplexing (OFDM) / time division multiplexing (TDMA) terminal system, A central processing unit that transmits and receives data packets with an upper block in software; An ARQ that receives the data packet, divides and stores the packet in a predefined fragment size, generates a frame at the time of frame generation according to the stored fragment information, and transmits and receives the ARQ in hardware while managing whether the ARQ is retransmitted. A transceiver; An interface buffer for storing data transmitted between the CPU and the ARQ transceiver; And Fragment buffer for storing the fragments generated by the ARQ transceiver ARQ transceiver comprising a. The method of claim 1, And the data packet is a service data unit (SDU) for receiving and storing the data from the upper block or a protocol data unit (PDU) processed with a media access control (MAC). The method of claim 1, And a frame buffer for storing uplink frame data to be transmitted from the terminal to the base station. The method of claim 1, And a downlink buffer for storing downlink data transmitted from a base station to the terminal. The method of claim 1, The CPU includes a program storage unit that implements MAC transmitter software and MAC receiver software, The MAC transmitter software receives the SDU from the upper block and stores the SDU in the interface buffer, and the MAC receiver software receives the PDU from the ARQ transceiver and performs the ARQ reception and MAC PDU processing. Device. The method of claim 1, wherein the ARQ transceiver, A packet divider which receives the SDU from the central processing unit and divides the fragment into fragments having a fixed size; Each time a new packet is stored in the fragment buffer from the packet divider, a tail pointer is updated, the state of the current fragment buffer is reported to the frame generator, and the head pointer is updated when the fragment buffer is transmitted. Incoming address manager; A frame generator for receiving information on a current fragment from the address manager and generating a frame using the fragment information; A retransmission manager for storing the fragment information, increasing the head pointer of the fragment buffer, moving the fragment information over a time stamp value to a retransmission buffer, and discarding fragment information over a predetermined number of retransmissions; A receiver block for transmitting the remaining PDUs excluding the ARQ response message among the MAC PDUs received from the base station to the CPU; And ARQ response buffer that receives and stores an ARQ response message from the receiver block and delivers it to the retransmission manager. ARQ transceiver comprising a. The method of claim 6, And a management message processing block receiving and storing a management message from which the fragment is not allowed, from the central processing unit, and delivering the management message to the frame generator. The method of claim 7, wherein And the frame generator reports information on a current management message from the management message processing block and generates a frame using the information. The method of claim 6, And the frame generator stores the generated frame in the frame buffer and then transmits fragment information on ARQ traffic to the retransmission manager. The method of claim 6, And the retransmission manager comprises an ARQ buffer for storing fragment information. The method of claim 10, And the retransmission manager checks whether each message in the ARQ buffer is correctly transmitted using the ARQ ACK message transmitted from the receiver block. The method of claim 6, And the retransmission manager stores, in the ARQ buffer, a transmission ARQ header having an address of a currently stored buffer and a stored time stamp value in the ARQ buffer, in case of an ARQ supported traffic flow. The method of claim 12, And the retransmission manager periodically retrieves the transmitted ARQ header to update a time stamp value, and stores a transmission ARQ header having a time stamp value equal to or greater than the retransmission time in the retransmission buffer. The method of claim 12, If there is an ARQ response message in the ARQ response buffer, the retransmission manager searches for the transmission ARQ header buffer using the ARQ response buffer, checks whether an ACK response is received, and then advances a transmission window value according to an ARQ scheme and contents of the buffer. ARQ transceiver, characterized in that for clearing. The method of claim 6, And the packet divider causes the address manager to update a stored address value. The method of claim 6, And the address manager comprises a circular queue in which a tail pointer and a head pointer are updated. The method of claim 16, And the address manager does not store a memory address value of 10 bits or more, and uses only the upper part bits of the memory address value as a head pointer and a tail pointer. The method of claim 5, And the transmitting end software stores the SDU in the interface buffer between the central processing unit and the ARQ transceiver before the frame generation request. An ARQ transmission / reception method of an OFDM / TDMA terminal system, a) storing an SDU transmitted from an upper block in a corresponding buffer; b) if the capacity of the buffer is sufficient, storing the SDU in an interface buffer; c) if ARQ is enabled, determining whether the capacity of the fragment buffer is sufficient; d) dividing the SDU if the capacity of the fragment buffer is sufficient; e) storing the divided packet at a corresponding address, and updating an address manager according to an address change of the fragment; f) generating a frame by determining whether there is a frame generation request; And g) transmitting and receiving the ARQ according to the frame ARQ transmission and reception method comprising a. The method of claim 19, The fragment information is a sequence number, time stamp, ARQ transmission and reception method, characterized in that the number of retransmission or stored address. The method of claim 19, wherein step d), Calculating a storage address pointer value; And Dividing the SDU into a fixed size ARQ transmission and reception method comprising a. The method of claim 21, wherein step d) Inserting a value for the fragment storage address into a queue designated by a tail pointer of a circular queue after fragment fragmentation; Storing the value in an address manager; And Fetching the fragment using the head pointer of the circular queue as a starting point when the frame generation request is made; ARQ transmission and reception method further comprising. The method of claim 19, wherein f) is, Determining whether there is the frame generation request and receiving current fragment information from an address manager and a retransmission manager when the frame generation request is received; Determining whether there is a fragment to transmit, if there is a fragment to transmit, fetching a fragment from the fragment buffer, and generating a PDU (Protocol Data Unit) packet; Storing the fragment information in the retransmission manager; Determining whether the fragment exists in a retransmission buffer, and if there is the fragment, retrieving fragment information from the retransmission buffer; And Generating a PDU packet by importing the fragment from the fragment buffer; ARQ transmission and reception method comprising a. The method of claim 19, wherein f) is, Generating the frame in hardware, and storing information about some bits of the head pointer for the information about the transmitted frame; Periodically updating the time stamp value; If the frame information is equal to or greater than a predetermined value, storing the information again in the retransmission buffer; And Retransmitting a fragment using the frame information when generating the frame ARQ transmission and reception method further comprising. The method of claim 19, Receiving an ARQ response message from a base station; Sending the ARQ response message to the retransmission manager without sending it to software; Deleting the fragment information receiving the ACK; And Updating a fragment address in the address manager ARQ transmission and reception method further comprising.