KR20050061892A - Active phase alignment apparatus with compensation for the parallel data skew - Google Patents

Abstract

The present invention relates to an active phase alignment device for adjusting skew between input parallel data using M phase adjusted clocks.

The present invention includes a delay locked loop for adjusting the phase of the input clock to M and outputting the M phase adjusted clocks; A reception retiming and phase selection unit for retiming the received N bits of parallel data using the phase adjusted clock, selecting a clock having an optimal phase for restoring the data, and outputting the clocked data to the selected clock; And a data path selector for selecting a desired path among the output data paths and restoring the data by correcting +/− 1 skew generated between the data paths.

According to the present invention, it is possible to reduce the system design cost and time by designing a data bus irrespective of parallel data skew.

Description

Active Phase Alignment Apparatus with Compensation for the Parallel Data Skew}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active phase alignment device for parallel data skew correction, and more particularly, to generate clocks of different phases using delay locked loops and to adjust skew between parallel data inputs using clocks of different phases. The present invention relates to an active phase alignment device for parallel data skew correction for adjusting data skew during parallel data transmission.

In devices requiring high speed and high performance, the processing data rate is faster and the parallel data bits are increasing, which makes hardware design difficult. In particular, the skew problem between data buses is increased when the signal is high speed. This skew problem can generally be solved by matching parallel data paths with the same length, but there may be cases where the path lengths cannot be identical. There is a lot of difficulty in hardware design to match the length. In addition, parallel data skew can be fit using a variable delay buffer, but when the number of bits of the parallel data increases, there are many difficulties in implementation. In particular, a skew occurring within 1 bit can restore data by modulating a delay buffer or clock phase.

FIG. 1 is a block diagram of a conventional data recovery apparatus, and illustrates a process of extracting data by modulating a clock phase with respect to a skew in which parallel data occurs within 1 bit in a conventional data restoration method. Referring to FIG. 1, a conventional data recovery apparatus includes a phase modulator 11, an input data latch unit 12, and a selector 13 that modulates a phase of an input clock, and includes a clock CLK_IN (1-10-). 1) and 4-bit parallel data DATA_IN [3: 0] (1-10-2) are used to solve the skew problem by using clock phase modulation or delay buffer. Here, the phase modulator 11 may use a clock 1/8 period delay buffer composed of multiple stages, and the delay buffer and 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees. The phase modulation clocks CLK0 (1-1-1), CLK45 (1-1-2), CLK90 (1-1-3), CLK135 (1-1-4), and CLK180 ( 1-1-5), CLK225 (1-1-6), CLK270 (1-1-7), and CLK315 (1-1-8) to generate a phase modulated clock that can clock all parallel data Find and clock to recover the data DATA_OUT [3: 0] (1-10-3). When the phase adjustment function is applied at the correct clock frequency, a phase locked clock using a delay locked loop method can be used.

The input data latch section 12 is a D flip-flop (F / F) (1-2-1) that clocks data using a zero degree delay clock CLK0 using a clock coming from each phase delay tap, a 45 degree delay clock. Equipped with eight D flip flops (1-2-1 to 1-2-8) per data bus, such as a D flip flop (1-2-2) that clocks data using As shown in the timing diagram, the selector 13 selects the most appropriate phase clock Sel_CLK (1-10-4) and clocks the selected clock.

2 is an embodiment of a data timing diagram restored by a conventional data restoration apparatus. FIG. 2 (a) is a skew timing diagram of data arriving at a receiver, and is an example of restoring data to a clock Sel_CLK (1-10-4) delayed by 180 degrees. If skew occurs within one clock cycle of DATA_IN [3: 0], and there is a phase-modulated clock that can clock each data, DATA_OUT [3: 0] can be restored normally.

However, the data skew timing diagram of FIG. 2 (b) shows an example in which data skew occurs within one clock period but recovery is not possible using any phase modulated clock. DATA_OUT [1] and DATA_OUT [2] are shifted by one bit, but normal data restoration is impossible.

In addition, the data skew timing diagram of FIG. 2 (c) shows an example in which restoration cannot be performed when DATA_IN [1] has +1 bit skew among the received parallel data. If the skew is different within 1 bit or if +/- 1 bit data skew occurs, normal data recovery is impossible using any delay tap.

2 (b) and 2 (c), in the conventional data recovery apparatus, when skew occurs within one clock period, there is a problem in that normal data recovery is impossible even if any delay buffer or any clock phase modulated clock is used. .

Accordingly, the present invention has been proposed to solve the above problems, and the most suitable phase clock among them when clocking data using different phase clocks for each data in parallel data with skew of +/- 1 bits. The purpose of the present invention is to provide an active phase alignment device for parallel data skew correction, which solves the skew problem caused by different data path length in hardware design by selecting clocked data.

According to an aspect of the present invention, there is provided a delay locked loop unit for adjusting a phase of an input clock to M and outputting the M phase adjusted clocks; A reception retiming and phase selection unit for retiming the received N bits of parallel data using the phase adjusted clock, selecting a clock having an optimal phase for restoring the data, and outputting the clocked data to the selected clock; And a data path selector for selecting a desired path among the output data paths and restoring the data by correcting +/− 1 skew generated between the data paths.

The above objects, features and advantages will become more apparent from the following description taken in conjunction with the accompanying drawings. Hereinafter, an active phase alignment device for parallel data skew correction according to the present invention will be described in detail with reference to the drawings in which preferred embodiments of the present invention are shown. In the following description, for convenience of description of the present invention, it is assumed that parallel data is 4 bits, and 8 phase adjusting clocks are generated in a delay locked loop. However, the present invention is not limited thereto, and the actual implementation may be extended to N bits. In addition, the delay locked loop for generating the phase-controlled clock is merely for explaining the present invention and it is revealed that a phase locked loop (PLL) element or a delay buffer can be used.

3 is a block diagram of an active phase alignment device for parallel data skew correction according to an embodiment of the present invention. As shown in FIG. 3, the active phase aligner 300 for parallel data skew correction according to an embodiment of the present invention adjusts the received clock CLK_IN 31-1 to eight phases using a delay locked loop. Delay-locked loop section 31 for generating clocks 31-2 to 31-9, and the received 4-bit parallel data DATA_IN [3: 0] (31-10) to phase-locked clocks 31-2 to 31. -9) a reception retiming and phase selector 32 for retiming and selecting a phase, and a data path selector 33 for selecting a desired data path from the retimed data DATA_OUT [3: 0] 32-1. It is composed of

3, the operation of the active phase alignment device 300 according to the present invention will be described in detail. The delay locked loop 31 is a clock CLK_0 (31-2) that is 0 degree phase modulated using the received clock CLK_IN (31-1), clocks CLK_45 (31-3) that are 45 degree phase modulated, and CLK_90 (31-). 4) 8 phase modulated clocks including CLK_135 (31-5), CLK_180 (31-6), CLK_225 (31-7), CLK_270 (31-8), and 315 degree phase modulated clock CLK_315 (31-9) Create Here, since the operation principle of the delay lock loop unit 31 applied to the present invention is a known technique, a detailed description thereof will be omitted.

The reception retiming and phase selector 32 uses the phase modulated clock to retime the reception parallel data DATA_IN [3: 0] 31-10 to clock the data DATA_OUT [to the phase modulated clock located at the center of the data. 3: 0] (32-1) is output. The reception retiming and phase selector 32 will be described in more detail later with reference to FIGS. 4 and 5.

The data path selector 33 restores data without error through skew correction in the clocking data DATA_OUT [3: 0] 32-1. Even when +/- 1 skew occurs between data paths, normal data is restored through the data delay method and data DATA 33-1 is output. The data path selector 33 will be described in detail later with reference to FIG. 7.

4 is a configuration diagram of the reception retiming and phase selection unit according to an embodiment of the present invention, and is a configuration diagram of the reception retiming and phase selection unit 32 shown in FIG. As shown in FIG. 4, the first stage retiming unit 41 retiming with eight phase-modulated clocks performs eight phase modulation on a 4-bit D flip-flop (F / F) that processes 4-bit parallel data. It consists of eight 4-bit D flip-flops 41-1 to 41-8 for clocking into the clock. The first stage retiming unit 41 clocks the input data DATA_IN [3: 0] to the CLK_0 (31-2) clock, and the I_DATA_0 [3: 0] data 41-1-1 and CLK_45 (31-3). 8-bit D flip-flops (41-1 to 41-8), such as I_DATA_45 [3: 0] data (41-2-1) clocked with a clock, are clocked with eight phase-modulated clocks Outputs 4-bit D flip-flop data (41-1-1 to 41-8-1). However, since the received data may exist in the same phase as the clocked clock, in some cases, unstable data may be output by the setup hold time vibration.

The second stage retiming section 42 is a latch for eliminating unstable data due to setup hold time vibration that may occur in the first stage retiming section 41 and retiming to the internal clock of the device. It consists of dogs 42-1 to 42-8. Here, the device internal clock is a clock which is synchronized with the reception clock and used as the main clock in the device. In the present invention, CLK_0 is used.

The phase selector 43 selects stable data for each of the eight 4-bit parallel data output from the second stage retiming unit 42. To this end, the phase selector 43 may select the DATA0 group (Q_DATA_0 [0], Q_DATA_45 [0], Q_DATA_315 [0]), phase selector 43-1, and DATA1 group Q_DATA_0 [1 for each data group. ], Q_DATA_45 [1], ..., Q_DATA_315 [1]) phase selector 43-2, DATA2 group (Q_DATA_0 [2], Q_DATA_45 [2], ..., Q_DATA_315 [2]) phase selector (43-3) and the DATA3 group (Q_DATA_0 [3], Q_DATA_45 [3], ..., Q_DATA_315 [3]) phase selector 43-4. The phase selectors 43-1 to 43-4 for each group include a phase detector 51 and a data selector 52, as shown in FIG. 5, which will be described below with reference to FIG. 5. It demonstrates in more detail.

5 is a configuration diagram of the phase detector 51 and the data selector 52 of each group phase selector according to the present invention. As shown in FIG. 5, the phase detector 51 detects a point in time when the phase changes by using an exclusive OR logic as follows.

Exclusive logical OR logic 51-1 of Q_DATA_0 [x] and Q_DATA_45 [x] and logical OR XOR_x [0], exclusive logical OR logic 51-2 of Q_DATA_45 [x] and Q_DATA_90 [x] and logical OR XOR_x [1], Exclusive OR logic 51-3 of Q_DATA_90 [x] and Q_DATA_135 [x] and OR XOR_x [2], exclusive OR logic 51-4 of Q_DATA_135 [x] and Q_DATA_180 [x] and OR XOR_x [3], Exclusive OR logic (5-1-5) of Q_DATA_180 [x] and Q_DATA_225 [x] and OR XOR_x [4], exclusive OR logic (5-1-6) of Q_DATA_225 [x] and Q_DATA_270 [x] and OR XOR_x [5], and the exclusive OR logic 51-7 and the OR XOR_x [6] of Q_DATA_270 [x] and Q_DATA_315 [x], and XOR_x [6] according to each output value XOR_x [0: 6] as shown in Table 1 below. The select signal Q_SELx [2: 0] signal can be implemented in logic logic to select the appropriate data path. Here, x means a data stream corresponding to 1 bit of 4-bit parallel data.

TABLE 1

XOR_x [0] XOR_x [1] XOR_x [2] XOR_x [3] XOR_x [4] XOR_x [5] XOR_x [6] Q_SELx_ [2: 0] 0 0 0 0 0 0 0 010 One 0 0 0 0 0 0 011 0 One 0 0 0 0 0 100 0 0 One 0 0 0 0 101 0 0 0 One 0 0 0 110 0 0 0 0 One 0 0 111 0 0 0 0 0 One 0 000 0 0 0 0 0 0 One 001

For example, the part indicated by 1 in the timing XOR_x [3] means that the phase is changed at Q_DATA_135 [x] and Q_DATA_180 [x], and thus the data can be most stably restored when clocked at the data center. Means that the Q_DATA_270 [x] data clocked with the third phase modulation clock CLK_270 is selected at the data phase change time.

The operation of the retiming and phase selector 32 will be described in detail with reference to the timing diagram shown in FIG. 6 is a timing diagram of a retiming and phase selection unit according to the present invention. In FIG. 6, the data DATA_IN [x] 61 is received with the skew delayed by 45 degrees compared to the input clock by the data path length. For example, the first stage retiming unit 41 and the first stage are described. The correlation between the output data of the two stage retiming part 42 is shown. The horizontal axis represents clocked phase adjusted clock phases (0, 45, 90, ..., 315), and the vertical axis represents input / output data.

The output data of the first stage retiming unit 41 is I_DATA_0 [x] 62-1 output using the CLK_0 phase modulation clock and I_DATA_45 [x] 6262 output using the CLK_45 phase modulation clock. ), I_DATA_90 [x] 62-3 output using the CLK_90 phase modulation clock, ..., and I_DATA_315 [x] 62-8 output using the CLK_315 phase modulation clock.

The output data of the second stage retiming unit 42 is QKDATA_0 [x] 63-1, Q_DATA_45 [x] 63-2, Q_DATA_90 [x] (63-3) as clocking data with CLK_0 clock. ), ..., Q_DATA_315 [x] (63-8).

In FIG. 6, when the clock clocking the input data is selected as CLK_180, CLK_225, or CLK_270, it is assumed that the clock is selected assuming that data restoration is optimal.

When the received data DATA_IN [x] 61 is clocked CLK_0, a 1-bit delay is generated and I_DATA_0 [x] 62-1 is output. When clocking with CLK_45, the unstable data I_DATA_45 [is caused by the setup hold time vibration. x] 62-2 is shown. Other phase clocks can confirm that data is clocked normally.

Q_DATA_0 [x] 63-1 and Q_DATA_45 [x] 63-2 of the waveforms output by clocking the data to the clock CLK_0 by the second stage retiming unit 42 are output after being delayed by one bit. The other data is normally clocked and output. Here, Q_DATA_45 [x] 63-2 shows that the unstable data I_DATA_45 [x] 62-2 due to the setup hold time vibration is output after 1 bit, but may be output without delay in some cases. .

It can be seen that the phase is changed between Q_DATA_45 [x] 63-2 and Q_DATA_90 [x] 63-3 among the output data of the second stage retiming unit 42. The result is the phase detector 51. In XOR_x [1], the exclusive OR result is 1, and by using this result, Q_SELx [2: 0] signal '100' is generated as shown in Table 1, and the Q_DATA_180 [x] data clocked to CLK_180 is DATA_OUT [x] (32 -1). It can be seen that CLK_180 is selected from the above-described optimal clocks CLK_180, CLK_225, or CLK_270.

The selected parallel data output DATA_OUT [3: 0] 32-1 is restored by the data path selector 33 through +/- 1 bit skew compensation. The operation of the data path selector 33 will be described in more detail with reference to FIG. 7.

7 is a block diagram illustrating a data path selection unit in accordance with an embodiment of the present invention. Referring to FIG. 7, the data path selector according to the present invention includes three one-bit delay units composed of four 1-bit D flip flops including three 71, 72, and 73 and a path selector 74. In the case of 7, an example of compensating +/- 1 bit skew can be provided. If compensation is required for more skew, the delay unit can be further extended.

The first stage delay unit 71 clocks the data DATA_OUT [3: 0] 32-1 signal output from the phase selector 43 to the CLK_0 clock, and outputs DA [3: 0] data. The delay unit 72 clocks DA [3: 0] data to the CLK_0 clock to output DB [3: 0] data, and the third delay unit 73 clocks the DB [3: 0] data to CLK_0 clock. Clock it and output DC [3: 0] data. Using the data bits DA [x], DB [x], and DC [x], D_SELx_ [1: 0] is selected by using the path selector 74 to select skew-compensated data as shown in Table 2 below. To select the data path.

TABLE 2

Skew DA [x] DB [x] DC [x] D_SELx_ [1: 0] -One One One One 10 +1 0 0 One 00 0 One 0 0 01

For example, in the case of +1 skew data, the D_SELx_ [1: 0] signal selects the DA [x] signal as '00' as shown in Table 2, which is described in FIG. 8. It demonstrates with reference to a timing chart.

On the other hand, the present invention assumes that the phase alignment signal is 0001000 'and uses the signal bits to assume that the parallel data is aligned in phase with' 1 '. Since the phase alignment signal bits may vary depending on the application, the phase alignment signal bits may be implemented using the phase alignment bits as appropriate when designing using the present invention.

FIG. 8 is a timing diagram of a data path selection unit according to +/- 1 skew of the present invention, for a predetermined time T in the DA [x], DB [x], and DC [x] data paths (the device according to the present invention). It is assumed that three cycles of the internal clock CLK_0 are used. FIG. 8 (a) shows that the input data DATA_IN (31-10) appears in the DA [x], DB [x], and DC [x] data as '1' signals at time T when -1 skew occurs. In this case, DC FIG. 8B shows an example of selecting [x], and FIG. 8 (b) shows a signal '1' is present in DC [x] data at time T when the input data DATA_IN 31-10 is +1 skew. 8 shows an example of selecting DA [x] when only 0 is displayed. FIG. 8 (c) shows a signal of '1' at time T when skew occurs within 0 bits of the input data DATA_IN 31-10. Shows an example of selecting DB [x] when is present in DB [x], DC [x] data and only DA is displayed as '0' in DA [x].

In this manner, a timing diagram for confirming whether DATA_IN [3: 0] restores data normally even when +/- 1 bit skew occurs bit by bit is shown in FIG. 9 is a reconstruction data timing diagram according to an embodiment of the present invention. Referring to FIG. 9, a timing diagram of FIG. 9A is a timing diagram of selecting DC [0] as D_SEL0_ [1: 0] is '10' when DATA_IN [0] is -1 bit skew. The timing diagram of 9 (b) is a timing diagram of selecting DA [1] with D_SEL1_ [1: 0] set to '00' when DATA_IN [1] has +1 bit skew, and the timing diagram of FIG. 9 (c). Is a timing diagram where D_SEL2_ [1: 0] selects DB [2] with '01' when DATA_IN [2] has 0 bit skew, and the timing diagram of FIG. 9 (d) shows +1. When bit skew occurs, D_SEL3_ [1: 0] selects DC [3] as '10'. Referring to FIG. 9, it can be seen that DATA_IN [3: 0] normally restores data even when +/- 1 bit skew occurs per bit.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the design of the data bus is independent of skew using programmable logic gates to reduce system design cost and time, even when the path lengths cannot be matched structurally or many constraints may occur in the hardware PCB design. There is an advantage to reduce.

1 is a block diagram of a conventional data recovery apparatus.

2 is an embodiment of a data timing diagram restored by a conventional data restoration apparatus.

3 is a block diagram of an active phase alignment device for parallel data skew correction according to an embodiment of the present invention.

4 is a block diagram of a reception retiming and phase selector according to an embodiment of the present invention.

5 is a configuration diagram illustrating a phase detector and a data selector of each phase selector according to the present invention.

6 is a timing diagram of a retiming and phase selection unit according to the present invention.

7 is a block diagram illustrating a data path selection unit in accordance with an embodiment of the present invention.

8 is a timing diagram of a data path selection unit for +/- 1 skew according to the present invention.

9 is a timing diagram of reconstruction data according to an embodiment of the present invention.

 Explanation of symbols on the main parts of the drawings

31: delay locked loop portion 32: reception retiming and phase selector

33: data path selection section 41: first stage retiming section

42: two-stage retiming section 43: phase selector

51: phase detector 52: data selector

71: first stage delay unit 72: second stage delay unit

73: third stage delay unit 74: path selector

Claims (7)

A delay locked loop unit for adjusting the phase of the input clock to M and outputting the M phase adjusted clocks; A reception retiming and phase selection unit for retiming the received N bits of parallel data using the phase adjusted clock, selecting a clock having an optimal phase for restoring the data, and outputting the clocked data to the selected clock; And A data path selector which selects a desired path from among the output data paths and restores data by correcting +/− 1 skew between the data paths; Active phase alignment device for parallel data skew recovery, characterized in that it comprises a. The method of claim 1, wherein the delay lock loop portion, An active phase alignment device for parallel data skew recovery comprising one of a phase locked loop, a phase locked loop (PLL) or a delay buffer. The method of claim 1, wherein the reception retiming and phase selector, A first stage retiming unit configured to clock the received N bits of parallel data with the phase-adjusted clocks to output M N bits of parallel data; And A phase selector for selecting data clocked by an optimum clock for each of the M N-bit parallel data output from the first stage retiming unit; Active phase alignment device for parallel data skew correction, characterized in that it comprises a. The method of claim 3, wherein And a second stage retiming unit configured to clock data obtained by the setup hold time vibration among the M N-bit data output from the first stage retiming unit, and to retime to a specific clock set among the phase adjusted clocks. Active phase alignment device for parallel data skew correction, characterized in that. The method of claim 3 or 4, wherein the phase selector, A phase detector for detecting a time point at which each phase of the M N-bit data is changed; And A data selector which selects data clocked by a corresponding phase-controlled clock of the data at the data phase change time point; Active phase alignment device for parallel data skew correction, characterized in that it comprises a. The data path selector of claim 1, Active phase alignment device for parallel data skew correction, characterized in that for restoring the selected data of the re-timed data through + /-1 bit skew correction. The data path selector of claim 1, A first stage delay unit configured to output data clocked from the retiming and phase selector to a specific clock set as an internal clock; A second stage delay unit configured to output data clocked from the first stage delay unit to the internal clock; A third stage delay unit configured to output data clocked from the second stage delay unit to the internal clock; And A path selector which selects data compensated for +/- 1 skew using each data output from the first, second and third delay units, and selects a desired data path using the selected data; Active phase alignment device for parallel data skew correction, characterized in that it comprises a.