KR20050059266A - Method for fabricating semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device in which yield and productivity can be enhanced. The method for fabricating a semiconductor device comprises a step for providing a plasma etching system comprising a vacuum container (1), a susceptor (7) for placing a wafer (8) in the vacuum container (1), means (2) for introducing material gas to the vacuum container, and means (6) for introducing high-frequency power, and a step for generating, by using the high-frequency power, plasma of the gas introduced into the vacuum container (1) by the gas introducing means (2) and making a plurality of holes selectively in an oxide film (23) on the major surface of the wafer in the plasma atmosphere, characterized in that the flat part and the hole part on the major surface of the semiconductor wafer is irradiated with light (15) having a continuous spectrum in the process for making the holes and variation of reflectivity is measured at the flat part and the hole part.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor technology, and in particular to a method of manufacturing a semiconductor device comprising a step of forming a contact hole in an interlayer insulating film.

In the process of manufacturing a semiconductor device, a step of forming a contact hole in an interlayer insulating film (mainly an insulating film mainly composed of silicon oxide) formed on a wafer main surface by a dry etching method using plasma, and filling a semiconductor or metal in the contact hole. There is this. In this contact hole formation, it is indispensable for the improvement of the yield of a semiconductor device to open completely without etch stop until the surface of a base semiconductor area | region or lower wiring is exposed. Therefore, in the situation where the difficulty of etching increases with the miniaturization of the contact hole, in order to perform a desired etching process, it is extremely important to accurately grasp the progress of the etching, particularly the etching depth, and to reflect it in the process conditions. .

The situation where the contact hole formation is etched off halfway and the semiconductor region or wiring of the base is not exposed is referred to as non-opening. Conventionally, in order to suppress the fall of the yield by this non-opening, the cross-sectional observation by scanning electron microscope (Scanning Electron Microscopy) etc., or the non-opening test by the potential contrast system were performed, and the cause of the defect was identified.

In the conventional method, however, it is necessary to actually extract the wafer from the lot and prepare a sample (sample) for an inspection apparatus such as an SEM. For this reason, productivity was reduced because of the need for a non-product wafer and the time required for feedback to the manufacturing process. In addition, a non-product wafer means the wafer which does not directly contribute to manufacture of a semiconductor device.

In addition, under the situation that the hole diameter is becoming finer and the diameter becomes 100 nm or less, light of the visible wavelength from the ultraviolet light is hardly incident to the bottom of the pattern without the influence of the pattern boundary, and the optical path length difference between the top of the pattern and the bottom is small. With the interference waveform measuring method used, a practical S / N ratio cannot be sufficiently obtained.

In addition, as disclosed in Japanese Patent Application Laid-Open No. 2000-131028 or Japanese Patent Application Laid-Open No. 2001-284323, as a means for monitoring the etching depth of a contact hole in real time, an interference waveform caused by the optical path length difference between the upper and lower portions of the pattern is measured. There is a method for obtaining the etching depth from the.

1 is a schematic view of a dry etching apparatus having an etching depth inspection function used in a first embodiment of the present invention.

2 is a partial sectional view of a wafer according to a first embodiment of the present invention.

3 is a plan view of a wafer according to a first embodiment of the present invention.

4 is an explanatory diagram showing a scanning process of a detection light irradiation position according to the first embodiment of the present invention.

Fig. 5 is a characteristic diagram showing the wavelength dependence of the reflectance of the flat portion and the hole portion and the wavelength shift amount of the interference peak according to the first embodiment of the present invention.

Fig. 6 is a characteristic diagram showing the relationship between the wavelength shift amount of the interference peak and the etching time according to the first embodiment of the present invention.

Fig. 7 is a characteristic diagram showing the relationship between the wavelength shift amount and the number of wafer processing sheets at the time of etching completion according to the first embodiment of the present invention.

8 is a schematic diagram of a multi-chamber plasma etching apparatus used in the first embodiment of the present invention.

Fig. 9 is a schematic diagram of the unload lock chamber with etching depth inspection function used in the second embodiment of the present invention.

Fig. 10 is a characteristic diagram showing a relationship between measurement accuracy and measurement frequency of impedance measurement according to the second embodiment of the present invention.

Fig. 11 is an equivalent circuit diagram showing a capacitance between an upper electrode and a lower electrode in the flat part of the wafer main surface according to the second embodiment of the present invention.

Fig. 12 is an equivalent circuit diagram showing the capacitance between the upper electrode and the lower electrode in the hole portion of the main surface of the wafer according to the second embodiment of the present invention.

Fig. 13 is a characteristic diagram showing the relationship between the etching depth and ΔC according to the second embodiment of the present invention.

14 is a schematic diagram of a dry etching apparatus having an etching depth inspection function used in a third embodiment of the present invention.

Fig. 15 is a characteristic diagram showing a relationship between an added O ₂ flow rate and a maximum aspect ratio at which an etch stop is generated according to the third embodiment of the present invention.

Fig. 16 is a sequence diagram showing a control step of O ₂ flow rate according to the third embodiment of the present invention.

Fig. 17 is a partial sectional view of a semiconductor device in a HARC forming step according to a third embodiment of the present invention.

Fig. 18 is a partial sectional view of a semiconductor device in a SAC forming process according to a third embodiment of the present invention.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can improve yield and productivity.

Among the inventions disclosed in the present application, an outline of typical ones will be briefly described as follows.

The present invention provides a plasma etching apparatus including a vacuum container, a susceptor for installing a semiconductor wafer provided in the vacuum container, a gas introduction means for introducing a source gas into the vacuum container, and a high frequency power introduction means. A method of manufacturing a semiconductor device, comprising the step of converting a gas introduced into the vacuum container by the gas introduction means into the high frequency power to selectively form a plurality of holes in a main surface of a semiconductor wafer in the plasma atmosphere. During or after the step of forming the hole, a step of irradiating light having a continuous spectrum to the flat part and the hole part of the main surface of the semiconductor wafer, and measuring the reflectance change of the flat part and the hole part. .

According to the present invention, in the etching process, by simply measuring the optical characteristics, the etching state, in particular the etching depth of the contact hole, is monitored non-destructively, and the early lot stoppage and the feedback to the process conditions are performed. As a result, it is possible to contribute to the improvement of productivity not only in the production of a large amount of small articles represented by DRAM (Dynamic Randam Access Memory), but also in a logic product that requires the production of a small quantity of small articles.

BRIEF DESCRIPTION OF DRAWINGS To describe the present invention in more detail, this is described in accordance with the accompanying drawings.

(First embodiment)

The structural diagram of the dry etching apparatus with an etching depth test function used for the Example of this invention is shown in FIG. According to this etching apparatus, source gas is introduce | transduced into the vacuum container 1 through the gas introduction pipe 2 and the shower plate 3, and a plasma is formed by the high frequency electric field which the high frequency power supply 6 generate | occur | produced. Like the turbomolecular pump in the vacuum chamber 1 (etching chamber), the high exhaust gas is decompressed by a possible vacuum exhaust means (not shown), and the pressure adjustment therein is performed by the conductance valve 21. The lower electrode 7 is provided in the vacuum container 1, and the semiconductor wafer 8 is provided on this lower electrode 7. As shown in FIG. The semiconductor wafer 8 is made of, for example, single crystal silicon (Si), and has a celestial separation region and a semiconductor region (active region) partitioned by the celestial separation region. The main surface of the semiconductor wafer 8 has an insulating film (interlayer insulating film) made of silicon dioxide (specifically, a TEOS film). The high frequency bias power supply 9 is connected to this lower electrode 7. The frequency of the high frequency Fire power supply 9 is 400 kHz to 1.56 MHz, preferably 800 kHz. The inside of the vacuum vessel 1 is maintained in a reduced pressure atmosphere, and the high frequency bias power supply 9 draws ions in the plasma by a peak to peak (Vpp) voltage of about 0.5 kV to 2 kV generated at the lower electrode 7. The insulating film is etched.

Next, the etching depth inspection function (etching depth measuring device) built in the etching apparatus will be described in detail.

The etching depth measuring apparatus of this embodiment is provided on the upper portion of the vacuum container 1. That is, the quartz window 14 for introducing the detection light 15 is provided in the ceiling part of the vacuum container 1. White light (continuous spectrum of 350 nm or more) from the Xe lamp 11 which is detection light enters through this quartz window. Some components of the detection light irradiate onto the wafer 8, and the reflected light passes through the same optical path and is reflected by the beam splitter and enters the detection system. In addition, other components of the detection light are guided directly to the detection system via the beam splitter 12 as reference light. The detection system is constituted by the spectrometer 16 and the diode array 17, and can measure the wavelength distribution of incident incident light intensity and reflected light intensity instantaneously. The lens 13 is provided in a vertical movement stage (not shown) for focusing on the wafer 8. And these etching depth measuring apparatuses are provided in the XY movement table 18 which can move to a horizontal direction. The XY shift table 18 is electrically connected to the calculator 20 via the D / A converter 38. In addition, the calculator 20 is electrically connected to the diode array 17 via the A / D converter 19.

In the present embodiment, one set of the light source, the optical system, and the detection system is provided, and the flat part measurement and the hole part measurement are performed in real time. However, in order to improve inspection throughput, two sets of light sources, an optical system, and a detection system may be provided, one for hole measurement and the other for flat part measurement.

The measuring method using the etching depth measuring apparatus comprised as mentioned above is demonstrated below with reference to FIGS. 2 shows that an oxide film 23 is deposited on a wafer (Si substrate 40), and a hole pattern is transferred to the oxide film 23 by a resist mask 22 having holes for forming a plurality of contact holes. It is a partial sectional view of the wafer which shows a state. As shown in FIG. 2, the resist mask 22 formed on the oxide film 23 (insulating film) has a plurality of hole pattern portions and a flat portion where no hole pattern is formed. 3 is a plan view of a wafer on which a hole pattern is formed. On the main surface of the wafer 8, patterns 24 constituting the IC chip are arranged in a lattice shape. A hole pattern (plural holes) is formed in each chip pattern 24. 4 is a plan view showing a part of the chip pattern in which the hole patterns are dense.

First, in FIG. 1, the position of the flat part in which the hole pattern is not formed is calculated from the calculator 20 into which data of the wafer pattern 24 shown in FIG. The detection light position for flat part measurement is determined. The detection light 15 is irradiated from the Xe lamp 11 to the measurement position on the wafer 8 via the lens 13. That is, as shown in FIG. 2, the detection light 15A is incident on the flat portion 22A where the hole pattern is not formed, or is inclined at an angle while maintaining a predetermined angle. At that time, the vertical movement stage is moved up and down so as to focus at the measurement position on the wafer. Here, using the spectroscope 16 and the diode array 17, the wavelength dependence of the reflectance which is the intensity ratio of incident light and reflected light is measured, and stored in the calculator 20 as reference data. In the flat part measurement, interference occurs due to a phase deviation between the reflected light on the surface of the resist mask 22 and the reflected light at the interface between the resist 22 and the oxide film 23.

Next, the measurement position actually measured is outputted from the calculator 20, the XY shift table 18 is driven, and the position of the detection light is determined once. Similar to the flat portion, the detection light 15 is irradiated from the Xe lamp to the measurement position on the wafer through the lens. In addition, the vertical movement stage is moved up and down so as to focus at the measurement position on the wafer. That is, as shown in FIG. 2, the detection light 15B enters into the hole part 22B in which the hole pattern is formed. Incident at this time is performed on the same conditions as the incidence to the flat part 22A. That is, if the incidence into the flat portion 22A is vertical incidence, the incidence into the hole 22B is also vertical incidence.

4, the XY shift table is scanned, and the wavelength dependence of the reflectance of a detection light is measured at each point. First, the wavelength shift amount with respect to the interference peak position of the acquired reference data is calculated, and the XY shift table is fixed where the value becomes maximum. By this process, even in a pattern with a large pitch of the hole part like a logic product, the number of holes that enter the detection light irradiation area 25 can be kept constant and maximum for each wafer at all times, thereby making it possible to improve the measurement accuracy.

In this embodiment, since the wavelength of the detection light is set to two or more times the diameter of the hole to be measured, it can be understood that the hole portion is subjected to macroporous formation as the etching progresses, and as shown in FIG. Wavelength shift occurs. The wavelength shift amount [Delta] [lambda] of the interference peak with this reference data gives a volume change of the measurement area.

Therefore, assuming that the oxide film thickness of the hole portion and the resist film thickness are the same as those of the flat portion, and the hole diameter is calculated from the pattern data, the volume change amount is converted into the etching depth. During the above steps, the etching depth can be measured in real time by repeatedly performing steps other than the measurement positioning steps of the flat part and the hole part during the etching process.

Next, the calculation method of a resist selectivity ratio is demonstrated. From the comparison of the reference data of the wavelength dependence of the reflectance at the flat portion obtained first with the theoretical curve data calculated based on the multiple reflection interference model using the oxide film thickness of the film thickness structure of the wafer stored beforehand, The resist film thickness of can be calculated. Therefore, the difference with the initial film thickness becomes the resist reduction amount at that time. On the other hand, since already described, since the etching depth of a hole part is calculated | required from the wavelength shift amount of the interference peak position with respect to reference data, the resist selectivity can be calculated | required by dividing the value by the resist reduction amount.

6 shows the relationship between the etching time and the wavelength shift amount. When etching progresses, as shown by the curve a, the wavelength shift amount increases with respect to the etching time, but when an etch stop occurs in the middle, the wavelength shift amount shows a constant value from that point as shown by the curve b. In the present embodiment, for example, when the curve b is obtained during the etching process, it is determined that it is an etch stop, and as shown in Fig. 7, the recipe is changed to a high porosity condition to continue the process. As a result, it is possible to prevent the metal filling of the non-opening, that is, the contact failure, and to build a system that can improve the yield and productivity while maintaining the throughput.

In this embodiment, the case where one set of the light source, the optical system, and the detection system is provided, but the same effect can be obtained by dividing the detection light from the light source into an optical element such as a beam splitter and providing two sets of the optical system and the detection system. have. In addition, by measuring only the reflectance of the detection light at the hole for each wafer, it can also be used for monitoring the change over time.

In addition, although the structure which performs etching depth measurement in real time was demonstrated in this Example, this etching depth measuring apparatus can be installed regardless of a gas atmosphere. That is, the etching depth measuring apparatus can be installed in a place where the wafer is conveyed after etching and stagnant for a certain time, such as the unload lock chamber 29 illustrated in FIG. 8, in addition to the vacuum container for etching. As a result, the etching depth can be monitored without lowering the throughput. By monitoring the etching depth of the contact hole, processing stop for the semiconductor wafer to be etched subsequently or feedback to the etching process conditions is performed.

Subsequently, a metal such as tungsten (W) or copper (Cu) is embedded in the through hole formed in this way.

(2nd Example)

With reference to FIGS. 9-13, the Example which observes an etching depth by capacitance measurement is demonstrated.

According to this embodiment, the measuring means is provided in the unload lock chamber, for example, the unload lock chamber 29 shown in FIG. The unload lock chamber is an intermediate vacuum chamber for discharging the processed wafer into the wafer cassette in the etching processing chamber.

In FIG. 9, the upper part of the unloading lock chamber 29 is provided with a measuring upper electrode (second electrode) 30 so as to face the surface of the wafer. The measuring upper electrode 30 is electrically isolated from the vacuum container and the insulator 31. The end surface of the upper electrode 30 facing the wafer forms a circular plane having a diameter of 0.1 mm to 3 mm. The upper electrode 30 is provided on the vertical movement stage 32 so as to set a distance from the wafer surface to 0.1 µm to 50 µm. In order to monitor the gap, a laser displacement meter 33 is provided at the tip of the electrode. It is installed. On the other hand, the measurement lower electrode (first electrode) 35 on which the wafer is mounted is provided on the XY movement table 36 which can move in the XY directions, and can measure any position. This XY movement table 36 is electrically connected to the calculator 20 via the A / D converter 38A. The vertical movement stage 32 is electrically connected to the calculator 20 via the A / D converter 38B. The laser displacement meter 33 is electrically connected to the calculator 20 via the A / D converter 19. The lower electrode 35 is provided with a plurality of protruding electrodes 34 having sharp edges that penetrate the oxide film on the back surface of the wafer so that contacts are always stably obtained. And the impedance meter 37 is electrically connected between the upper electrode 30 and the lower electrode 35, and the capacitance between electrodes can be measured. The impedance meter 37 is electrically connected to the calculator 20 via the A / D converter 38C.

Next, the measuring method of an etching depth is demonstrated.

First, as shown in FIG. 9, the wafer 8 after etching is conveyed and installed on the lower electrode 35. As shown in FIG. Since an oxide film is formed on the back surface of some wafers, the projection electrodes are reliably contacted. In this case, when the resistance of any two projection periods is measured for each wafer installation, the reproducibility of the back contact is assured. However, of course, if it is a means which a contact is taken reliably even if it is not a minute protrusion electrode, it goes without saying that it falls in the scope of a present Example.

Next, the XY movement table 36 is driven based on the pattern data of the wafer previously stored in the calculator 20 to move the electrode 30 to the measurement position of the flat portion without the pattern. Then, the vertical movement stage 32 is driven while feeding back the output value of the laser displacement meter 33, and the space | interval of the surface of the wafer 8 and the surface of the upper electrode 30 is fixed to a set value. 10 shows the relationship between the measurement accuracy of the impedance meter and the measurement frequency. In this embodiment, the measurement frequency is set to 100 kHz so that the measurement accuracy is minimized.

Impedance measurement is performed at the measurement position of this flat part. As shown in FIG. 11, the measurement result is equivalent to the synthesized capacitance in which the electrode-wafer gap capacitance Cg, the resist capacitance Cm, and the oxide film capacitance Cf are connected in series.

Next, the position of the upper electrode 30 is taken to the hole part which is a measurement position in the XY moving table 36. Next, as shown in FIG. Here, as in the measurement of the flat part, the combined capacitance is measured from the impedance measurement. Here, similarly to the first embodiment, assuming that the group of holes formed by etching is macroscopicized, as shown in Fig. 12, the capacitance (Ch) of the hole portion and the portion (hole peripheral portion) filled with the oxide film are shown in FIG. This can be understood as the parallel capacity of the capacity Cf '. Therefore, since the combined capacitance decreases due to etching, the relationship between ΔC and the etching depth, which is a difference from the value of the flat portion, is as shown in FIG. 13. Here, an oxide film thickness of 2 µm, a pore area of 20%, and an electrode-wafer spacing of 1 µm were assumed. In this case, ΔC increases with the etching depth and becomes ΔC = 0.47 (pF) at an etching depth of 2 μm. This is a value that can be fully measured as a value of about 5% relative to the synthetic dose.

Next, the reproducibility improvement of a measurement position is demonstrated. As in the case described in the first embodiment, the XY moving table on which the wafer is provided is scanned near the measurement position of the hole portion. The synthesized capacity is measured at each position, and the difference between the minimum value of the value and the synthesized capacity of the flat portion obtained above is taken as true ΔC. By this process, even in a pattern with a large pitch of the hole part like a logic product, the number of holes that always enter the measurement range of the upper electrode can be kept constant and maximum for each wafer, so that the measurement accuracy can be improved.

If through-hole formation by etching is performed reliably by the above inspection, a metal such as tungsten (W) or copper (Cu) is embedded in the formed through-hole. That is, the process of embedding a metal in a through hole is performed. If the through hole is non-opening, for the next semiconductor wafer to be etched, the etching condition is changed to a recipe that is surely opened.

Also in this embodiment, the resist selection ratio can be calculated similarly to the first embodiment. The resist film thickness at this point can be calculated from the comparison between the synthesized capacity in the flat portion obtained first and the theoretical synthesized capacity calculated from the film thickness structure of the wafer stored in advance. Therefore, the difference with the initial film thickness becomes the resist reduction amount after the completion of etching. On the other hand, as described above, since the etching depth is obtained from the difference in the compound capacitance at the hole portion with respect to the compound capacitance in the flat portion, and the film structure of the oxide film thickness, the opening area, and the electrode-wafer spacing, the value of resist reduction By dividing by, the resist selection ratio can be obtained.

(Third Embodiment)

With reference to FIGS. 14-18, the Example of the manufacturing method of a more specific semiconductor device is described below. 17 and 18 show contact hole forming processes in which high precision etching is required as the semiconductor device LSI is miniaturized.

First, FIG. 17 shows a cross-sectional view of a contact hole forming process called high aspect ratio contact hole (HARC) for an interlayer insulating film (specifically, a TEOS film). HARC formation requires the formation of a very deep hole in the interlayer insulating film 23B from a hole diameter of 0.13 mu m to a depth of 2 mu m at 0.1 mu m or less in the future. In the dry etching process at this time, a contact failure occurs due to a defective shape at the bottom of the hole, a tapered shape, or the like, and is likely to cause a decrease in yield.

18 illustrates a cross-sectional view of a contact hole forming process called Self-Align Contact (SAC). SAC formation dry-etches the silicon oxide film 23A without etching the silicon nitride film 42 protecting the gate electrode 41, so that the main surface of the silicon substrate (more specifically, a semiconductor region such as a source or a drain) 40 To expose the process. In order to obtain the selectivity of the silicon nitride film 42 and the silicon oxide film 23, high deposition control is required, and a slight change in etching conditions causes shape defects such as opening defects or tapered shapes of the contact portion.

The etching method evaluation method described in the first or second embodiment is applied to such a contact hole forming step shown in FIG. 17 or FIG. 18.

In addition, the etching apparatus shown in FIG. 14 is applied in such a contact hole formation process. The embodiment will be described below.

Using a Ar / C ₅ F ₈ / O ₂ mixed gas system as the source gas, the gas pressure is set to 2 Pa. In this gas condition, for example, even nano-scale holes of the diameter showing the 17 0.1㎛ case of etching the (contact holes (CH)), O ₂ was added up to the aspect ratio of the flow rate and the etch stop occurs is that the O ₂ flow rate The relationship of FIG. 15 is established. Accordingly, the etch stop may be seen that this region is drastically improved, inhibiting etching in the vicinity of the aspect ratio of 4 for the flow rate of O ₂ present. In other words, in order to suppress the O ₂ flow rate to be added to the minimum necessary and improve the mask selection ratio, it has been found that a step etching for increasing the O ₂ flow rate up to the aspect ratio 4 and reducing the O ₂ flow rate thereafter is effective. .

In the present embodiment, as shown in FIG. 14, the basic configuration is as described in the first embodiment with reference to FIG. 1. In particular, the gas flow meter 10 is electrically connected to the recipe control calculator 39 via the A / D converter 38 for O ₂ flow rate control. In this embodiment, etching is performed by the step of controlling the O ₂ flow rate shown in FIG. 16. By inputting the relationship between the aspect ratio and the added O ₂ flow rate in the recipe control calculator 39 in advance, the above problems can be solved without being influenced by the variation of the etching rate due to the change over time. Although only the control system of gas flow rate is shown here, it can apply also to control of other external parameters, such as gas pressure, high frequency electric power, and high frequency bias electric power.

After the contact hole forming step, a so-called plug forming step of embedding a metal in the contact hole CH is performed. And after this plug formation process, a wiring formation process is performed using a well-known sputtering method and photolithography technique.

Moreover, in the manufacturing process of a semiconductor device, the SAC formation process shown in FIG. 18 is performed before the HARC formation process shown in FIG. The HARC formation process shown in FIG. 18 is performed with respect to the insulation film 23B formed on the interlayer insulation film 23A shown in FIG.

As described above, according to the present invention described based on the specific examples, in the etching method of forming contact holes by etching, the process of etching the mask selectivity such as the etching depth and the resist, or the wafer from the etching processing chamber after the etching is finished In the process of conveying, non-destructive and simple monitoring is possible to enable early lot stoppage and feedback to process conditions. As a result, productivity can be improved not only in the production of a large amount of small articles represented by DRAM, but also in a logic product requiring a small amount of large products.

According to the present invention, in the manufacturing process of a semiconductor device, in particular, the contact hole forming step, the mask selection ratio such as the etching depth and the resist can be easily and non-destructively in the process of conveying the wafer from the etching process chamber after the etching process or the end of the etching. Monitoring enables early lot shutdown or feedback to process conditions. Thereby, the yield and productivity of a semiconductor device can be improved.

Claims (20)

A plasma etching apparatus having a vacuum container, a susceptor for installing a semiconductor wafer provided in the vacuum container, gas introduction means for introducing a source gas into the vacuum container, and high frequency power introduction means are prepared, and the gas introduction means Plasma forming the gas introduced into the vacuum chamber by the high frequency power, and selectively forming a plurality of holes in the semiconductor wafer main surface in the plasma atmosphere, wherein the holes are formed. And a step of irradiating light having a continuous spectrum to the flat portion and the hole portion of the main surface of the semiconductor wafer during or after the step of measuring the change in reflectance of the flat portion and the hole portion. Manufacturing method. The method of claim 1, The light is perpendicularly incident or obliquely incident to the main surface of the semiconductor wafer, and the reflectance is measured from the intensity ratio of the incident light and the reflected light. The method of claim 1, The light is white light, and is incident perpendicularly or obliquely to the main surface of the semiconductor wafer, and the wavelength dependence of reflectance is measured from an intensity ratio of incident light and reflected light of the white light. The method of claim 1, The semiconductor wafer main surface has an interlayer insulating film, and the plurality of holes are formed in the interlayer insulating film. (1) forming an insulating film on the semiconductor substrate and a mask having a plurality of hole pattern portions and flat portions on which the hole patterns are not formed; (2) forming a plurality of holes in the insulating film based on the mask by dry etching; (3) During the step (2), the flat portion and the hole portion are irradiated with light having a continuous spectrum to measure the change in reflectance of the flat portion and the hole portion, and based on the measurement result, Penetrating a plurality of holes, (4) embedding metal in a plurality of holes in the hole portion The semiconductor device manufacturing method characterized by the above-mentioned. The method of claim 5, In the step (2), the light is incident perpendicularly or obliquely to the main surface of the semiconductor wafer, and the reflectance is measured from the intensity ratio of the incident light and the reflected light. The method of claim 5, In the step (2), the light is white light, is perpendicularly incident or obliquely incident to the main surface of the semiconductor wafer, and the wavelength dependence of the reflectance is measured from the ratio of the intensity of the incident light and the reflected light of the white light. Manufacturing method. (1) forming an insulating film on the semiconductor substrate and a mask having a plurality of hole pattern portions and flat portions on which the hole patterns are not formed; (2) forming a plurality of holes in the insulating film based on the mask by dry etching; (3) During the step (2), the step of measuring the wavelength dependency of the reflectance at the flat part, the step of measuring the wavelength dependency of the reflectance at the hole part, and the specification of the wavelength dependency obtained at the hole part and the flat part. Comparing the column with each other to obtain a wavelength shift amount of the interference peak position of the hole portion with respect to the interference peak position of the flat portion; and then passing through the plurality of holes in the hole portion based on the measurement result; , (4) embedding metal in a plurality of holes in the hole portion The semiconductor device manufacturing method characterized by the above-mentioned. The method of claim 8, In the step (2), the light is incident perpendicularly or obliquely to the main surface of the semiconductor wafer, and the reflectance is measured from the intensity ratio of the incident light and the reflected light. The method of claim 9, And the light is white light. A plasma etching apparatus having a vacuum container, a susceptor for installing a semiconductor wafer installed in the vacuum container, gas introduction means for introducing a source gas into the vacuum container, and high frequency power introduction means are prepared, and the gas introduction means A method of manufacturing a semiconductor device, comprising the step of converting a gas introduced into the vacuum vessel into the high frequency power by plasma, and selectively forming a plurality of holes in the semiconductor wafer main surface in the plasma atmosphere. The plasma etching apparatus includes a light source for emitting detection light, a detection system comprising a beam splitter, a lens, a spectrometer, and a diode array arranged in an optical path, an XY shift table capable of moving the detection system in a horizontal direction, and the detection system And a calculator for storing data of the light source, wherein the detection light from the light source is irradiated to the main surface of the semiconductor wafer through a quartz window provided on the ceiling of the vacuum vessel. During or after the step of forming the hole, a step of irradiating detection light from the light source to the flat part and the hole part of the main surface of the semiconductor wafer, and measuring the reflectance change of the flat part and the hole part. The manufacturing method of the semiconductor device characterized by the above-mentioned. The method of claim 11, The light source is a method of manufacturing a semiconductor device, characterized in that the Xe lamp. The method of claim 11, And the detection light is perpendicularly incident or obliquely incident to the main surface of the semiconductor wafer, and the reflectance is measured from the intensity ratio of the incident light and the reflected light. The method of claim 11, The detection light is white light, and is incident perpendicularly or obliquely to the main surface of the semiconductor wafer, and the wavelength dependence of reflectance is measured from an intensity ratio of incident light and reflected light of the white light. A plasma etching apparatus having a vacuum vessel, gas introduction means for introducing source gas into the vacuum vessel, and high frequency power introduction means is prepared, and the gas introduced into the vacuum container by the gas introduction means is plasma at the high frequency power. And forming a plurality of holes selectively on a main surface of the semiconductor wafer in the plasma atmosphere. The plasma etching apparatus includes a first electrode movable in a horizontal direction in which a semiconductor wafer is provided in contact, a second electrode disposed to face the first electrode, and movable in an up and down direction; An etching depth inspection device having an impedance meter electrically connected to the two electrodes, and a calculator electrically connected to the impedance meter through an A / D converter; After the hole is formed, a step of measuring the capacitance of the flat portion and the hole portion of the main surface of the semiconductor wafer by an etching depth inspection device is compared with the capacitance acquired from the flat portion and the hole portion, and the electrostatic capacitance of the flat portion is reduced. And obtaining a difference between the measured value of the capacitance and the measured value of the capacitance of the hole portion. The method of claim 15, The second electrode measuring the hole portion includes a step of scanning a semiconductor wafer, and the second electrode position is determined such that the capacitance is minimized by this scanning step. . The method of claim 15, The plasma etching apparatus includes a load lock chamber and an unload lock chamber, and the first and second electrodes are provided in the unload lock chamber. The method of claim 15, And a plurality of protruding electrodes in contact with the back surface of the semiconductor wafer are arranged on the first electrode. The method of claim 15, A tip portion of the second electrode is a semiconductor device manufacturing apparatus, characterized in that the circular surface having a diameter of 0.1mm to 3mm. The method of claim 15, A method of manufacturing a semiconductor device, wherein the distance between the second electrode and the surface of the semiconductor wafer is between 0.1 µm and 50 µm.