KR20050055466A - Method for reducing test time of semiconductor device - Google Patents

Abstract

A high voltage is applied to force a die to be caused by a pre-test to force a specific pad to open / short (O / S). A method for reducing test time during post-test is disclosed. Such a method includes pre-testing a fab-out wafer, performing laser repair, and performing post-test using the results of the pre-test in the DRAM production process. Therefore, the die which the non-repairable dies of the pre-tested dies using the empty count information obtained in the pre-test have occurred can be marked by the test equipment so that these dies can be used during post-testing. There is an effect that can reduce the test time by not proceeding the flow on the test plan unnecessarily.

Description

Method for reducing test time of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to force open / short (O / S; opern) on a specific pad with respect to a die in which a defect occurs due to pre-test. The present invention relates to a method for reducing test time during post-test by forcibly applying a high voltage to cause a failure.

In general, a test of dynamic random access memory (DRAM) consists of a pre-test and a post-test, which are divided before and after a laser repair operation. Each of the pre-test and the post-test consists of a plurality of test items, and the test progress is flowed by the test plan.

When the test is performed and a defect occurs in a specific test item, a bin count corresponding to the defective item is output and the test time is skipped by skipping the test of the remaining items.

However, the result of the pre-test according to the above-described method is not effectively used for the post-test performed after the laser repair, and the same test time as the pre-test is used, which is the result of the probe test. This problem occurs because the test equipment cannot be used to recognize the die on the wafer die.

As a result, the above-mentioned problem increases unnecessary test time, leading to an increase in test cost, which leads to a decrease in productivity.

The present invention was created in order to improve the above problems, and the technical problem to be achieved by the present invention is to use the information obtained in the pre-test more effectively, so that unnecessary test work in the post-test does not proceed with the test time. To provide a way to reduce the

According to one type of the present invention for achieving the above object, in the process of producing DRAM, pre-testing the fab-out wafer, performing laser repair and post-test using the results of the pre-test A method is provided for reducing test time comprising performing a test.

In addition, the pre-test result is preferably empty count data.

In addition, for dies for which good dying or repair is not possible as a result of the pre-test, the test equipment is characterized in that it is a bad die in the preceding test on the test item.

In addition, it is desirable to apply a high voltage to a die that can not be repaired using a pre-test result so that O / S defects may occur on a specific pad.

In addition, the value of the high voltage is characterized in that it is a value sufficient to cause breakage of the gate oxide film of the die, which is not repairable, and to cause a short between the gate of the transistor and the substrate.

In addition, the die forcibly O / S failure is characterized in that no separate test is performed in the post-test.

Hereinafter, with reference to the accompanying drawings will be described in detail a method for reducing the test time in the manufacturing process of the semiconductor device according to an embodiment of the present invention. Like reference numerals in the following drawings denote like elements.

1 is a schematic flowchart illustrating a test of a DRAM production wafer according to a preferred embodiment of the present invention.

As shown in FIG. 1, when the DRAM production wafer is fab-outed, a pre-test is executed. Subsequently, the laser repair operation is performed according to the result of the pre-test, and then the post-test is performed. In the next step, packaging is performed only for dies with good post-test results.

2 is a detailed flow chart for explaining the test of the DRAM production wafer in accordance with a preferred embodiment of the present invention.

FIG. 2 is a test flow for executing in a pre-test. When a defect occurs in a corresponding item, an empty count (O, L, V, H, W, X ... I) corresponding to the defective item is generated. Print and test the rest of the items. For example, if a failure occurs in an open / short test item, a corresponding bin count is outputted as O.

3 is a plan view illustrating a bin count map on a wafer on which a pre-test has been performed according to a preferred embodiment of the present invention.

After the pre-test according to the flow chart of FIG. 2 is executed, bin count map information as shown in FIG. 3 is obtained for each wafer 10. Here, the good die 120 is a die that has passed all test items, and the die 130 is a repairable die. The remaining dies 110 corresponding to the empty counts are dies in which defects are impossible and cannot be repaired by a repair.

After such classification, the repairable dies 110 are repaired in the laser repair equipment and then test in the test equipment again.

At this time, since the information performed in the pre-test is not properly used, wafer bin count information is obtained as shown in FIG. 5A. In other words, the dies 210 that are found to be dies having failed in the pre-test are also subjected to unnecessary tests to test the items up to the item where the failure occurs. If the empty count is at the beginning of the test flow, such as W, then the loss of test time is small, but if it exists at the end of the test flow, such as D or I, the loss of test time is significant. This is because the items that exist behind the test flow are often significantly larger than other items.

In particular, a test item such as a disturbance test (D) takes more than a few times as long as the other item, so if a large number of dies re-checks the D defect as shown in the map of FIG. There is a problem that the test cost (cost) is significantly increased.

On the other hand, Fig. 5B shows a plan view for explaining the empty count map on the wafer in the case of applying the preferred embodiment of the present invention.

According to a preferred embodiment of the present invention, as shown in FIG. 4, for a die in which a defect occurs in the pre-test, a high voltage is forcibly applied to a specific bonding pad 112 and the gate and the transistor are destroyed by Gox destruction. Causes short to the substrate.

This provides a map of the wafer 300 as shown in FIG. 5B in post-test without any additional work on the test rig. That is, since all of the dies 310 that are defective are defective in the open / short (O / S) test, which is the first step in the test flow, a blank count corresponding to O is obtained and thus unnecessary tests are not performed. The time is greatly reduced.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is in spite of an example, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined not by the scope of the detailed description but by the appended claims.

According to the preferred embodiment of the present invention configured as described above, the test equipment can recognize the dies that cannot be repaired among the dies in which the pre-test is performed by using the blank count information obtained in the pre-test. In this case, the test time can be reduced by unnecessarily allowing the flows on these dies to be unnecessarily carried out during the post-test.

In addition, the test equipment recognizes the presence or absence of defects by applying a high voltage to a specific pad of the die that caused the defect to be recognized by the first test item O / S test in the test flow to cause the short issued By adopting a method that does not execute unnecessary tests after the O / S item, there is an effect that it can be simply implemented without requiring additional equipment.

1 is a schematic flowchart illustrating a test of a DRAM production wafer according to a preferred embodiment of the present invention.

2 is a detailed flow chart for explaining the test of the DRAM production wafer in accordance with a preferred embodiment of the present invention.

3 is a plan view illustrating a bin count map on a wafer on which a pre-test has been performed according to a preferred embodiment of the present invention.

FIG. 4 is a plan view showing a bonding pad for one of the dies of the wafer shown in FIG.

5A and 5B respectively show plan views for explaining the empty count map on the wafer when and without the preferred embodiment of the present invention.

* Description of Signs of Major Parts of Drawings *

100, 200, 300: Wafer

110, 210, 310: bad die

120, 220, 320: good die

112: bonding pad

114: circuit area

130, 230: Repairable die

Claims (6)

In the process of producing DRAM, Pre-testing the fab-out wafer; Performing laser repair; And Performing a post-test using the results of the pre-test Test time reduction method of a semiconductor device comprising a. The method of claim 1, And the pre-test result is empty count data. The method of claim 2, And a die for which good dying or repair is not possible as a result of the pre-test, so that the test equipment knows that the die is a bad die in the preceding test on the test item. The method of claim 1, The method of reducing a test time of a semiconductor device, wherein a high voltage is forcibly applied to a die that cannot be repaired using the pre-test result so that an O / S defect may occur on a specific pad. The method of claim 4, wherein And wherein said high voltage value is sufficient to cause breakage of a gate oxide film of said non-repairable die, resulting in a short between a gate of said transistor and a substrate. The method of claim 5, The method for reducing the test time of a semiconductor device according to claim 1, wherein a separate test is not performed in a force-test for the die forcibly O / S failure occurs.