KR20030063683A - burn-in test equipment of semiconductor device - Google Patents

Abstract

PURPOSE: A burn-in test apparatus of a semiconductor device is provided to improve the reliability of the device by preventing a specific memory cell or a gate oxide from a heavy stress by giving a dat line stress to the dummy word line using as a memory mat dummy. CONSTITUTION: A burn-in test apparatus of a semiconductor device includes a plurality of main word lines(21), a plurality of main bit lines(22), a sense amplifier(23), a sub word line driver(24), a plurality of memory cells(25), a dummy word line(26), a dummy bit line(27) and a dummy cell(28). In the burn-in test apparatus, the plurality of main word lines(21) are formed by a predetermined distance in a specific direction, and the plurality of the main bit lines(22) are formed by a predetermined distance in a vertical direction with respect to the main word lines(21). The sense amplifier(23) amplifies the voltage to store and to read the data on/from the memory cell by connecting to each of the main bit lines(22). The sub word line driver(24) drives the word line and the plurality of the memory cells(25) are connected between each of the main word lines(21) and the main bit lines(22). The dummy word line(26) is formed on the most outer peripheral surface of the main word lines(21) in the same direction of the main word lines(21) and the dummy bit line(27) is formed on the most outer peripheral surface of the main bit lines(22) in the same direction of the main bit lines(22). And, the dummy cell(28) is connected between the dummy word line(26) and the dummy bit line(27).

Description

Burn-in test equipment of semiconductor device

TECHNICAL FIELD The present invention relates to semiconductor devices, and more particularly, to a burn-in test apparatus for semiconductor devices suitable for improving the overall yield of the devices.

In general, in manufacturing a device and supplying it to a user, a process defect is delivered from a supplier's point of view through a burn-in test to guarantee long-term reliability of the chip.

Currently, burn-in tests are usually carried out in a packaged state after the manufacturing process, so that the test method has an inefficient production cost that has to be discarded even though the fail portion of the burn-in has gone from the wafer fabrication stage to the assembly stage. to be.

Therefore, many studies on know good die have been conducted, and a method of realizing the burn-in test at the wafer manufacturing stage has been published.

Among the memory devices, especially for Dynamic Random Access Memory (DRAM), most burn-in failures are single bit failures, which require a lot of time.

Single bit failure is directly related to the leakage of incomplete memory cells, and leakage current is caused by poor transfer gate oxide, capacitor dielectric, or storage node capacities.

Until now, the wafer burn-in (hereinafter referred to as WBI) structure is not only different depending on the word line structure of the memory device but also the stress of each node is different according to the implementation of the WBI operation. Still remains.

On the other hand, when a semiconductor product is shipped and used in a system, it exhibits a high failure rate in the first one to two months due to the inherent life characteristics of the semiconductor product. This is because there is a failure factor that can cause a failure when the product is stressed.

Therefore, it is necessary to test the product to eliminate such defects. Since the general use condition takes a lot of time, the product is tested in a much worse environment.

In other words, by raising the temperature and increasing the stress voltage, products that may be defective may be identified within a predetermined time (within 72 hours). This process is called burn-in. The burn-in test is intended to stress the product and to screen the initial failure before shipping.

However, most of the devices that are determined to be bad after the burn-in test at the package level are bad bits, and therefore, all the devices that are determined to be bad after the burn-in test at the package level must be scrapped. There is a wasteful issue.

Accordingly, in order to repair a device having a bit defect, a burn-in test must be performed before packaging the device, that is, at the wafer level.

However, the wafer-level burn-in test cannot test a large number of devices at the same time, so it is possible to perform the same effect as the package-level burn-in test in the shortest time (for example, within a few seconds). The burn-in test requires a long time (for example, a few tens of hours) because it is accessed one word at a time. Therefore, the burn-in time required when performing the burn-in test at the wafer level is very high. It becomes big.

In addition, when using an existing tester such as a memory tester for testing, there is a problem that the system is complicated and the efficiency is lowered.

Hereinafter, a burn-in test apparatus of a conventional semiconductor device will be described with reference to the accompanying drawings.

1 is a block diagram showing a burn-in test apparatus of a conventional semiconductor device.

As shown in FIG. 1, a plurality of main word lines 11 are formed at regular intervals in one direction, and are formed at regular intervals in a direction perpendicular to the main word lines 11. A plurality of main bit lines 12 and a sense amp 13 connected to the main bit lines 12 to amplify a voltage for storing or reading data in a memory cell; A plurality of sub word line drivers (SWDs) 14 connected to the main word lines 11 to drive word lines, and a plurality of main word lines 11 and main bit lines 12 connected between the main word lines 11 and the main bit lines 12. The memory cell 15, the dummy word line 16 formed at the outermost side of the main word line 11 in the same direction as the main word line 11, and the main in the same direction as the main bit line 12. A dummy bit formed at the outermost part of the bit line 12 It is composed of 17 and the dummy cell 18 connected between the dummy word line 16 and dummy bit line (17).

19, which is not described herein, is a bit line contact.

The burn-in test of the conventional semiconductor device configured as described above has a word line stress for stressing a memory cell and a gate oxide and a data line stress for stressing between bit lines.

In this case, since the data line stress is given on a memory mat that is actually used, a specific cell or gate oxide is heavily stressed against another, and thus becomes a vulnerable cell in terms of throat reliability.

In other words, the word line stress drives the entire word line at the same time to stress all memory cells and gate oxides for a certain period of time, thereby screening for weak wafers such as gate oxide pin holes and cell degradation. do.

The data line stress inputs a specific pattern of data into a memory mat and drives a specific word line, thereby giving a potential difference between the bit line and the bit line as a cell data and a sense amplifier, thereby screening a weak wick between bit lines.

However, the above burn-in test apparatus of the conventional semiconductor device has the following problems.

In other words, during the wafer burn-in test, only the memory cell or gate oxide corresponding to the word line driven during the data line stress is subjected to heavy stress, which is a weak cell in terms of reliability, resulting in a failure, resulting in lower overall yield of the device. .

The present invention has been made to solve the conventional problems as described above to prevent excessive stress applied to a specific cell or gate oxide during wafer burn-in test to improve the reliability of the device to improve the overall device yield It is an object of the present invention to provide a burn-in test apparatus for a semiconductor device.

1 is a block diagram showing a burn-in test apparatus of a conventional semiconductor device

2 is a block diagram showing a burn-in test device for a semiconductor device according to the present invention

Explanation of symbols for the main parts of the drawings

21: main word line 22: main bit line

23: sense amplifier 24: sub word line driver

25: memory cell 26: dummy word line

27: dummy bit line 28: dummy cell

29: bit line contact

Burn-in test apparatus for a semiconductor device according to the present invention for achieving the above object has a plurality of main word lines formed with a predetermined interval in one direction, and a constant interval in a direction perpendicular to the main word line A plurality of main bit lines formed, a sense amplifier connected to each main bit line to amplify a voltage for storing or reading data in a memory cell, and a sub word connected to each main word line to drive a word line A line driver, a plurality of memory cells connected between each main word line and a main bit line, a dummy word line formed at an outermost side of the main word line in the same direction as the main word line, and the main bit line; A dummy bit line formed at an outermost side of the main bit line in the same direction, and the dummy word A burn-in test apparatus for a semiconductor device including a dummy cell connected between a line and a dummy bit line, the test is performed by applying a data line stress to the dummy word line.

Hereinafter, a burn-in test apparatus for a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram showing a burn-in test apparatus for a semiconductor device according to the present invention.

As shown in FIG. 2, a plurality of main word lines 21 are formed at regular intervals in one direction, and are formed at regular intervals in a direction perpendicular to the main word lines 21. A plurality of main bit lines 22 and a sense amp 23 connected to each of the main bit lines 22 to amplify a voltage for storing or reading data in a memory cell; And a plurality of sub word line drivers (SWDs) 24 connected to the main word lines 21 to drive word lines, and a plurality of main word lines 21 and main bit lines 22 connected between the main word lines 21 and the main bit lines 22. The memory cell 25, the dummy word line 26 formed at the outermost side of the main word line 21 in the same direction as the main word line 21, and the main in the same direction as the main bit line 22. A dummy bit formed at the outermost part of the bit line 22 It is composed of 27 and the dummy cell 28 connected between the dummy word line 26 and the dummy bit line 27.

29, which is not described herein, is a bit line contact.

The burn-in test of the semiconductor device according to the present invention configured as described above gives a data line stress to the dummy word line 26.

That is, in the related art, since data line stress is given on a memory mat that is actually used, stress is applied to a specific memory cell or gate oxide, but in the present invention, a dummy word line used as a memory mat dummy By giving the data line stress to (26), it is possible to minimize the defective cells by preventing the excessive stress applied to the memory cells and the gate oxide as in the prior art.

As described above, the burn-in test apparatus of the semiconductor device according to the present invention has the following effects.

In other words, by applying a data line stress to a dummy word line used as a memory mat dummy, an excessive stress to a specific memory cell or gate oxide can be prevented, thereby improving device reliability and improving overall device yield.

Claims (1)

A plurality of main word lines formed at regular intervals in one direction, a plurality of main bit lines formed at regular intervals in a direction perpendicular to the main word line, and connected to each of the main bit lines to data in a memory cell A sense amplifier for amplifying a voltage for storing or reading a signal, a sub word line driver connected to each main word line to drive a word line, and a plurality of memory cells connected between each main word line and a main bit line And a dummy word line formed at the outermost part of the main word line in the same direction as the main word line, a dummy bit line formed at the outermost part of the main bit line in the same direction as the main bit line, and the dummy word line. -In test of a semiconductor device consisting of dummy cells connected between a chip and a dummy bit line In the apparatus, And testing the dummy word line by applying a data line stress to the dummy word line.