KR20050052787A - Apparatus of viterbi decoding in dmb receiver and method of the same - Google Patents

Abstract

The present invention relates to a Viterbi decoder of a digital multimedia broadcasting (DMB) receiver. According to the present invention, a branch input of convolutional coded data for correcting a transmission error of a DMB receiver and entering each state on a trellis is most suitable. A Viterbi decoder that traces and decodes a small pass metric as a survivor path includes a single port memory having a single port for reading and writing data, and the convolutional coded data transmitted to the single port memory through the single port. And a plurality of additional buffers for temporarily storing the data in order to lower the data rate output from the memory, and a controller for writing and writing back traces of the written data through the port. In the implementation of the clock, the efficient use of memory and clock By giving the lower frequency has the effect that the entire system is in operation at low power.

Description

Apparatus of viterbi decoding in DMB receiver and method of the same}

The present invention relates to a digital multimedia broadcasting (DMB) receiver, and more particularly, to a Viterbi decoding apparatus and method in a DMB receiver for transmission error correction.

Digitization of broadcasts has also affected conventional analog radio broadcasts, speeding up the advent of digital radio broadcasts. In addition to the conventional voice radio service, digital multimedia broadcasting (DMB), which includes data transmission and multimedia services, has become possible. Digital multimedia broadcasting is resistant to noise and distortion on a transmission channel, has a high transmission efficiency, and has various advantages of enabling various multimedia services.

This digital multimedia broadcasting (DMB), adopted in Korea, is based on the Eureka-147 digital radio broadcasting (DAB), which has been adopted as the European terrestrial radio standard.

Added to the DAB to improve multimedia broadcasting performance, RS codes and convolutional interleavers that are robust to burst errors that may occur on a transmission channel are included.

The two additional blocks are applied to the DAB Ensemble input signal at the transmitter and provide an error rate low enough for video service even in a mobile receiving environment.

The transmission channel of the DMB broadcast is a wireless mobile reception channel, and the amplitude of the received signal is not only time-varying but also the Doppler Spreading of the received signal spectrum due to the influence of the mobile receiver. Occurs.

In addition, the DMB transmission signal is transmitted with a very small signal strength compared to the conventional analog radio broadcast signal, and the signal strength of the actual received signal is very small considering the mobile reception such as in a car in a severe fading channel environment such as downtown. .

Therefore, the DMB receiver should be able to correct the transmission error by receiving the received signal as much as possible in such a poor reception environment.

In addition, considering the fact that it is a mobile receiving terminal, it is necessary to exhibit maximum reception performance at a limited cost, and to operate at low power in consideration of battery capacity, etc., becomes a key requirement of the DMB receiver configuration.

Accordingly, an object of the present invention is to solve the problems of the prior art, to propose an efficient decoding apparatus and method for implementing a Viterbi decoder in a DMB receiver for transmission error correction.

Another object of the present invention is to propose a Viterbi decoder which can reduce power consumption.

Viterbi decoding apparatus of the DMB receiver according to the present invention for achieving the above object, the traceback decoding of the smallest path metric among the branches coming into each state on the trellis receiving convolutional coded data as a survivor path decoding In order to read and write data, the single port memory includes a single port, and the convolutional coded data transmitted to the single port memory is written through the one port, and the written data is read back through the port. And a plurality of additional buffers for temporarily storing the data in order to reduce the data rate output from the memory.

The data is recorded once through the one port, and the cycle of reading three times is repeated.

The data written to the additional buffer is characterized in that it is read in the opposite direction to the written direction.

In the Viterbi decoding method according to the present invention, the transmitted convolutional coded data is decoded in order to trace back and decode the smallest path metric among the branches which enter convolutional coded data and enter each state on the trellis as a survivor path. Writing to a memory having a single port, backtracking and reading the written data through the port, temporarily storing the read data in a plurality of buffers, and backing up the temporarily stored data back in the reverse direction Characterized in that it comprises a step of reading.

The speed of reading data written to the memory having the one port is four times the writing speed.

The speed of reading the temporarily stored data in the reverse direction is the same as the system clock of the entire DMB receiver.

Hereinafter, a configuration and an operation according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing the overall configuration of a DMB receiving system including a Viterbi decoder according to the present invention.

As shown in FIG. 1, the DMB receiver receives a transmitted broadcast signal through an antenna 1, and the received broadcast signal is a pass-band signal of a desired intermediate frequency through a tuner 2. Is converted to.

 In order to keep the signal tuned through the tuner 2, the gain value calculated according to the reference signal size is multiplied by the AGC (Automatic Gain Control) unit 3, and then A / D (Analog). In the digital converter block 4, sampling is performed on the signal having a predetermined size and converted into a digital signal. The converted digital signal recovers the real part of the complex signal into a complex signal through the I / Q divider 5.

At this time, the transmission mode detection unit 6 detects the transmission mode of the received signal in order to obtain an accurate frame synchronization and OFDM symbol synchronization signal, and then the OFDM demodulator 8 removes unnecessary guard intervals and then removes the FFT ( Fast Fourier Transform) transforms the time domain signal into the frequency domain. The input and output signals of the OFDM demodulator 8 become input signals of the signal synchronizer 7, and the signal synchronizer 7 extracts information necessary for synchronization in the time / frequency domain.

The signal transformed into the frequency domain restores the positions of the sub-carrier signals interleaved by the transmitter through a frequency de-interleaver (9). Through 1 (10), the control channel is divided into a fast information channel (FIC) channel and a data channel (MSC) main service channel and outputted.

The FIC channel is input to the FIC decoder 11 so that information necessary to decode the MSC channel is decoded. Separate data (ex. Traffic information, etc.) transmitted through the FIC channel is used for the FIC data decoder 12. Decoded via

The MSC channel restores the 16 logical frames interleaved at the transmitter through the time deinterleaver 13 in the original frame order, and the interleaved MSC channel is a random error that may occur during transmission. Error correction is performed through a convolutional decoder 14 that corrects an error.

The error corrected data is inputted to the channel divider 2 (16) after the data that was scrambled for encryption by the energy descrambler 15 is restored to the original data.

The channel divider 2 (16) distinguishes and outputs whether the transmitted MSC data channel is an audio / data signal for a DAB service or a video signal for a DMB service. The audio / data for the DAB service is decoded through the audio / data decoder 17 and output as an audio / data signal.

The signal for the DMB service is again arranged in the original order of the data additionally interleaved by the transmitter through the convolutional deinterleaver 18, and the RS-encoded data is restored by the transmitter through the RS decoder 19. Serve

The reconstructed data is reconstructed and output as a video signal through the video decoder 20.

In the configuration of the DMB receiver operating as described above, the convolutional decoder 14 for correcting the random error performs convolutional decoding between the current input data and the past stored input data at the transmitting end and proceeds sequentially. By increasing the correlation between them, the receiver uses this feature to eliminate the error.

The most representative implementation of the convolutional decoder 14 is the Viterbi decoding algorithm.

The Viterbi algorithm uses a branch metric and a path metric as a measure of the difference between the trellis of the transmitting end and the received signal.

The branch metric is obtained as a Hamming distance or Euclidian distance according to the channel model, and the pass metric is obtained as the sum of the branch metrics.

This Viterbi algorithm selects the smallest path metric among the branches coming into each state on the trellis and adds the branch metric of that state to generate a new pass metric and store the information at this time. The path having the smallest path metric is defined as a survivor path, and a decoding output is determined by tracing back the survivor path on the current time axis after a truncation depth (T).

Methods for implementing such a Viterbi algorithm include a register exchange method and a trace back method.

Among these, the register implementation method is characterized in that additional memory and hardware are required in order to have fast operation characteristics, and accordingly, the required power consumption is large, and the backtracking method requires less power but has an initial value. It is characterized by a constant delay time until decoding.

Accordingly, the present invention implements a Viterbi decoder using the above traceback method to focus on low power and to construct the whole system.

FIG. 2 is a diagram schematically illustrating a backtracking algorithm using a single pointer. In the one-pointer method, a write and read time point is represented by each pointer. An algorithm for efficiently performing report traceback.

As shown in FIG. 2, the Viterbi decoding implementation method of searching for a survivor path by using a backtracking method uses a memory, and requires a part to write and a part to read.

That is, Bank0, Bank1, Bank2, and Bank3 of FIG. 2 represent memory blocks and all have the same size, and T represents the truncation depth. 'tb' represents a trace back section, 'dc' represents a decision section, and 'wr' represents a block to write.

In order to obtain the correct decoding value, the length of the Truncaton depth must be traced back, and the 'tb' and 'dc' block parts are all read operations.

In the one-point traceback algorithm, the write pointer and the read pointer start to operate at the same time, but the read pointer must operate at exactly three times the speed at which the write pointer moves.

This is to decode the correct value without conflicting the write pointer and the read pointer in the memory.

According to the present invention, the single pointer algorithm is implemented in real hardware by using one port rather than two ports, a write port and a read port.

That is, by efficiently configuring a memory addressing method for low power consumption, a single port memory is used instead of dual port memory.

In order to use the single port memory, only one clock may be used to access the memory, and a clock corresponding to four times the data clock is used to reflect the speed difference between writing and reading.

To describe in more detail such a relationship through the accompanying drawings as follows.

3 is a diagram illustrating a relationship between a memory addressing method and a clock when using a single port memory according to the present invention.

As shown in Fig. 3, the write address is increased (0, 1, 2, 3, ...) with the data clock, and the read address is decreased with the memory access clock (2T-1, 2T). -2,2T-3, ...).

In addition, the write enable (write_enb) signal and the read enable (read_enable) signal are adjusted as shown in FIG. 3 so that they can be read three times after writing once. This operation relationship is achieved through the control of a controller (not shown) in the Viterbi decoder.

In the case of performing the back trace using one pointer algorithm, the back trace is decoded by performing the back trace in the reverse direction. Therefore, the output result value is also output in the reverse order in units of the memory bank.

Therefore, to obtain the output values in the correct order, an additional buffer corresponding to the memory bank of T / 2 is required. At this time, the value input to the additional buffer is input at the same value as the reading speed (4 times the clock), and the output value of the buffer is also at the same speed as the reading speed in order to prevent overwriting the value input to the buffer. Should be printed as

However, in the case of the DMB receiver, data is transmitted at twice the clock of the original receiver clock in order to divide the I and Q values in the demodulation block after the channel divider 1 (10), and at this double clock speed. It is input to the Viterbi decoder.

Therefore, in order to perform back-tracking of one pointer method in the Viterbi decoder, the clock speed corresponding to 8 times speed multiplied by the 4 times speed and 2 times speed is obtained.

In order to prevent the data input into the buffer at the speed of the 8 times speed, the output of the buffer should be output at the same speed as the buffer input speed.

However, the use of high frequency clock increases power consumption, and since the Viterbi decoder can operate only with the original system clock, 8x clock is used for buffer input and 1x clock is used for output. It is efficient.

To do this, an additional buffer size of 8 times the memory bank is required. This is shown in Figure 4 attached.

FIG. 4 is a diagram illustrating the size of a memory and a buffer added to implement a Viterbi traceback algorithm using a single pointer method according to the present invention.

As shown in FIG. 4, the single port memory requires a memory corresponding to (2T * state number) according to one-pointer algorithm, and the size of the additionally required buffer is (T / 2 * 1 * 8). ) Is the size.

That is, the additionally required buffer requires eight buffers from 0 to 7, and performs an operation of first input least output (FILO), in which the first data entered last.

Looking at the operation of the added buffer, the first, 8 times the clock is written back to the first buffer from the address 0, the result value is written, and when the first buffer is full, it continues to fill from the address 0 of the second buffer.

If the last address T / 2 of the first buffer is filled up and the value is written to address 0 of the second buffer, the value is read backwards from T / 2, the last address of the first buffer, and then decoded correctly. You get a non-resulting value.

As described above, in the Viterbi decoding apparatus and method of the DMB receiver according to the present invention, the entire system is operated at low power by reducing the clock frequency and using the memory efficiently in implementing the Viterbi decoder.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.

1 is a block diagram showing the overall configuration of a DMB receiving system including a Viterbi decoder according to the present invention

2 is a simplified diagram of a backtracking algorithm using a pointer according to the present invention.

3 is a diagram illustrating a relationship between a memory addressing method and a clock when using a single port memory according to the present invention.

4 is a diagram illustrating the size of a memory and an additional buffer required to implement a Viterbi traceback algorithm in a single pointer method according to the present invention.

-Explanation of symbols for the main parts of the drawing-

1: antenna 2: tuner

3: AGC part 4: A / D converter

5: I / Q distributor 6: transmission mode discriminator

7: signal synchronizer 8: OFDM demodulator

9: frequency reverse interleaver 10: channel divider 1

11: FIC decoder 12: FIC data decoder

13: time deinterleaver 14: convolutional decoder

15: energy descrambler 16: channel divider 2

17 audio / data decoder 18 convolutional deinterleaver

19: RS decoder 20: video decoder

Claims (6)

A Viterbi decoder that receives convolutional coded data to correct a transmission error of a DMB receiver and traces and decodes the smallest path metric among branches entering each state on a trellis as a survivor path. Single port memory with one port for reading and writing data, A control unit which writes the convolutional coded data transmitted to the single port memory through the one port, and controls to read back the read data through the port; Viterbi decoding apparatus of the DMB receiver comprising a plurality of additional buffers for temporarily storing the data to lower the data rate output from the memory. The method of claim 1, Viterbi decoding apparatus of the DMB receiver, characterized in that the data is written once through the one port, and the cycle of reading three times is repeated. The method of claim 1, Viterbi decoding apparatus of the DMB receiver, characterized in that the data written to the additional buffer is read in the opposite direction to the written direction. A Viterbi decoding method that receives convolutional coded data to correct a transmission error of a DMB receiver and traces and decodes the smallest path metric among branches entering each state on a trellis as a survivor path. Writing the transmitted convolutional coded data to a memory having one port; Reading back and reading the written data through the port; Temporarily storing the read data in a plurality of buffers; Viterbi decoding method comprising the step of reading the temporarily stored data back in the reverse direction. The method of claim 4, wherein And a read speed of data written to the memory having one port is four times the write speed. The method of claim 4, wherein The rate of reading the temporarily stored data in the reverse direction is the system clock and the silver speed of the entire DMB receiver Viterbi decoding method of the DMB receiver.