KR20050052855A - Method for reducing time de-interleaving memory in dmb receiver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital multimedia broadcasting (DMB) receivers, and more particularly, to a method for reducing time inverse interleaver memory in a digital multimedia broadcasting receiver. Such a method for reducing time-interleaver memory in a digital multimedia broadcasting receiver according to the present invention uses a memory required for deinterleaving data interleaved for a predetermined time in a digital multimedia broadcasting receiver. (segment) to use.

Description

Method for reducing time de-interleaving memory in DMB receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital multimedia broadcasting, and more particularly to a technique for reducing the size of memory required in a time deinterleaver of a digital multimedia broadcasting receiver.

In general, the digitization of broadcasts has also affected existing analog radio broadcasts, which has accelerated the advent of digital radio broadcasts. In addition, digital multimedia broadcasting (DMB), which includes data transmission and multimedia services, as well as existing voice radio services, has become possible. Digital multimedia broadcasting is robust against noise and distortion on a transmission channel, has a high transmission efficiency, and has various advantages of enabling various multimedia services.

The Digital Multimedia Broadcasting (DMB) currently adopted in Korea is based on Eureka-147 Digital Audio Broadcasting (DAB), which has been adopted as the European terrestrial radio standard. It is a Reed-Solomon Code and Convolutional Interleaver that are robust against burst errors.

The two additional blocks are applied to the DAB Ensemble input signal at the transmitter and provide an error rate low enough to enable video service even in a mobile reception environment.

The transmission channel of the DMB broadcast is a wireless mobile reception channel, and the amplitude of the received signal is not only time-varying, but also the Doppler Spreading of the received signal spectrum due to the influence of the mobile receiver. Occurs.

In addition, the DMB transmission signal is transmitted with a very small signal strength compared to the conventional analog radio broadcast signal, and considering the mobile reception, such as in a car in a severe fading channel environment, such as downtown, the signal strength of the actual received signal is very small.

In consideration of the transmission and reception in such a channel environment, the DMB transmission method is based on Orthogonal Frequency Division Multiplexing, and interleaving the signal in the time domain and the frequency domain to generate an error in the transmission channel. To correct it.

Therefore, the DMB receiver should be able to correct the transmission error by receiving the received signal as much as possible in such a poor reception environment. In addition, considering the fact that it is a mobile receiving terminal, it is a key requirement of the DMB receiver configuration that the maximum reception performance is achieved at a limited cost.

In addition, time interleaving is necessary to randomize the aggregation error of the received signal.

Here, the time interleaving means storing data for a predetermined time, and then transmitting the data in a random order differently from the order in which the data came in.

1 is a table illustrating time interleaving according to a general DMB standard.

First, the time interleaving scheme defined in the DMB standard stores data for 16 frames in a memory and randomizes them according to the bit reverse rule as shown in FIG.

Similarly, time deinterleaving is required to recover this at the receiving side, and memory is also needed to store data for 16 frames.

Referring to FIG. 1, time interleaving used in the DMB standard illustrates a form in which data is transmitted for a time corresponding to 16 frames from time r to r + 15.

Here, a _{r and i} refer to the i-th data (sample) of time r.

Data transmitted in the previous time, r is the interleaving is an original data by the bit reverse of the rule 2 as the i (modulo) value changes from 0 to a 15 _{r, i} are interleaved in a _{r ', i.}

Therefore, in time deinterleaving _, a _{r, i} can be obtained from a _{r ', i} by the reverse order of this process.

Thus, according to the DMB specification, since there are 55296 samples in one frame, the memory size of a general time deinterleaver requires 16 × 55296 × 4 bits of memory when a soft decision is made of 4 bits. Since the memory of 16 uses only the darkened portion of FIG. 1 during 16 frames, the remaining portion is an idle portion, which causes a waste of memory.

Accordingly, an object of the present invention has been made in view of the above-mentioned problems of the prior art, and reduces the size of the gate required for ASIC of the DMB receiving chip by reducing the size of the memory required for the time deinterleaver in the DMB receiver. It is to provide a time deinterleaver memory reduction method in a DMB receiver.

       According to a feature of the present invention for achieving the above object, in the memory use required for deinterleaving the interleaved data for a certain time in the DMB receiver, the memory is segmented only for the portion actually used use.

Preferably, the memory has a structure modified to store a total of 120 samples from segment 0 of size 15 to segment 14 of size 8.

In addition, the segment is modulo as much as its size to perform time deinterleaving for each segment. The multi-segment reads the value stored in the time deinterleaver memory first in the reading process and outputs it to the output of the deinterleaver, and writes the input of the deinterleaver in the deinterleaver memory at the same address as the reading process.

Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a DMB receiver according to the present invention.

Referring to FIG. 1, a DMB receiver includes an antenna 11 for receiving a transmitted broadcast signal and a received signal input to the antenna 11 as a pass-band signal of a desired intermediate frequency. AGC multiplying the tuner 12 to be converted and the gain value calculated according to the reference signal size in order to keep the size of the signal input to the A / D converter 14 to be subsequently input to the tuned signal ( An automatic gain control unit 13, an A / D converter 14 for converting a predetermined size signal into a digital signal, and a mode for detecting a transmission mode of the converted digital signal After removing the detector 15, the I / Q divider 16 which restores the real part of the complex signal of the converted digital signal to a complex signal, and unnecessary guard intervals, Fast Fourier Transform (FFT) An OFDM demodulator 8 for converting a signal into a frequency domain, a signal synchronizer 17 for extracting information necessary for synchronization in a time / frequency domain of the signal using the input and output signals of the OFDM demodulator 18; The channel divider 1 (20) for distributing the frequency interleaver 19 for restoring the positions of the sub-carrier signals interleaved at the transmitter and the FIC channel as the control channel and the MSC channel as the data channel. The FIC decoder 21 receives the separated FIC channel and separates information necessary to decode the MSC channel, and the 16 logical frames received from the MSC channel and interleaved by the transmitter are reconstructed. Convolutional decoding for correcting a random error occurring in a transmission channel among the time deinterleaved MSC channels A convolution decoder 23, an energy descrambler 24 that restores the original data through the corrected data, and whether the transmitted data channel is an audio / data signal for a DAB service or a video for a DMB service. A channel divider 2 (25) for discriminating whether the signal is separated and an audio / data decoder (29) for decoding the audio / data signal for the separated DAB service, and a signal for the DMB service is additionally received at the transmitting end. Convolutional de-interleaver 26 for arranging interleaved data in the original order, RS decoder 27 for restoring RS-encoded data at the transmitting end, and video for DMB service. The video decoder 30 recovers the signal and the FIC data decoder 28 decodes the separate data transmitted through the FIC channel.

As the DMB receiver is expected to be miniaturized and developed in the future in combination with a mobile phone, the DMB receiver chip is also ASIC, and a form of a one chip solution is required.

Therefore, reducing the size required for the time inverse interleaver has a very important meaning in reducing the size of the gate to enable one chip in an ASIC implementation.

Therefore, in the present invention, in the time deinterleaving, a new method called by the multi-segment method reduces the size of the memory required for the time deinterleaver.

Hereinafter, with reference to the accompanying drawings as follows.

4 is a view for explaining a time deinterleaver memory reduction method in a DMB receiver according to the present invention.

First, in the present invention, as shown in the standard of FIG. 1, a unit of a memory whose size changes in accordance with an i value is called a segment.

Storing 16 samples in 16 frames typically requires as much as 16x16 = 256.

However, in the memory of the present invention, only 120 samples are required, which are the sum total of 15 segments, from segment 0 of size 15, to segment 14 of size 8.

In general memory usage, all the samples take the same modulo, whereas in the multi-segment method, each segment takes a modulo by that size, thereby removing the idle part of the memory.

The first step is to read the value stored in the time deinterleaver memory and export it to the output of the time deinterleaver.

The second step is a write process, in which the input of the time reverse interleaver is written to the time reverse interleaver memory at the same address as the read process.

In this way, since the process of first reading and then writing to the memory having the same address is repeated, one memory required for each segment may be further reduced.

Segment 0, for example, should initially store 16 samples, but if you read first, then write, you only need to store 15 samples.

Therefore, as shown in FIG. 4, the size of segment 0 is 15, and segment 15 does not allocate memory separately because the reverse interleaving is possible when the input to the time deinterleaver is bypassed.

As described above, the present invention has an advantage of reducing the size of the memory, which is one of the most important resources of the chip implementation, by more than half, and accordingly, the gate size is greatly reduced, thereby making the IC of the DMB receiver ASIC It is possible to make one chip).

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

1 is a table showing time interleaving according to the standard of the general digital multimedia broadcasting standard

FIG. 2 is a table illustrating a bit reverse rule of the time interleaving table according to FIG. 1.

3 is a block diagram showing a digital multimedia broadcasting receiver according to the present invention.

4 is a diagram illustrating a structure of a time deinterleaver memory in a digital multimedia broadcasting receiver according to the present invention.

Explanation of symbols on the main parts of the drawings

11: antenna 12: tuner

13: Automatic Gain Controller (AGC) 14: A / D Converter

15: mode detector 16: I / Q distributor

17 signal synchronization unit 18 OFDM demodulator

19: frequency reverse interleaver 20: channel divider 1

21: FIC decoder 22: FIC data decoder

23: time deinterleaver 24: convolutional decoder

25: energy reverse scrambler 26: channel divider 2

27 audio / data decoder 28 convolutional deinterleaver

29: RS decoder 30: video decoder

Claims (4)

        In using the memory required to deinterleave the interleaved data for a certain time in the DMB receiver,        The method of claim 1, wherein the memory is segmented only for a portion actually used. The method of claim 1, And the memory requires only a total of 120 sample memories, ranging from segment 0 of size 15 to segment 14 of size 8.        The method of claim 1,        And said segment is time deinterleaved by taking a modulo by that size. The method of claim 3, wherein The multi-segment reads the value stored in the memory in the time reverse interleaver first and outputs it to the output of the time reverse interleaver, and writes the input of the time reverse interleaver in the time reverse interleaver memory at the same address as the read process. How to reduce time deinterleaver memory in receiver.