KR20050052109A - Method which the flip-chip bump forms - Google Patents

Abstract

The present invention relates to a method for forming flip chip bumps. In particular, the method of forming a flip chip bump enables fine bump pitch and solder resist opening by using a film type solder resist instead of a conventional ink type solder resist and using a laser drill. It is about.

In addition, according to the present invention, the first step of laminating a film-type solder resist on the insulating material, the first laser processing to open the solder resist; A second step of forming an electroless copper plating layer after the first step, laminating a dry film, and opening the dry film by second laser processing; A third step of filling a copper pad in the open portion of the solder resist in the first step, and a solder in the open portion of the dry film in the second step; And a fourth step of etching the dry film and the electroless copper plating layer and performing a surface treatment.

Description

Method of forming flip chip bumps {Method which the flip-chip bump forms}

The present invention relates to a method for forming flip chip bumps. In particular, the method of forming a flip chip bump enables fine bump pitch and solder resist opening by using a film type solder resist instead of a conventional ink type solder resist and using a laser drill. It is about.

The semiconductor manufacturing process consists of three steps: fabrication, packaging and inspection of silicon chips. Dual packaging and inspection processes are known to account for 70% of the total cost, and packaging has a significant impact on chip size and performance.

Electronic packaging is a technology that constructs a semiconductor chip into a system. The function of packaging is as follows. (1) signal redistribution, (2) power distribution, (3) mechanical support and protection, and (4) thermal management.

(1) interconnection of chips in electronic packaging, (2) packaging semiconductor chips into a single chip module (SCM), and (3) SCM to PCB Bonding to a card, (4) joining several cards to a board using a connector or the like, and (5) configuring a system.

Technologies such as COB (Chip on Board) and MCM (Multi-Chip Module) are a combination of two and three levels, sometimes called 2.5 steps.

In the electronic packaging step, step 0 is a metallization process inside the chip, and microjunction is mainly used in steps 1 and 2.

Processes used in step 1 include wire bonding, tape automated bonding (TAB), flip chip, diffusion bonding, and the like. PTH and SMT are used in step 2. Can be mentioned.

Such bonding process should be performed at low temperature so as not to damage the semiconductor circuit.

Here, the first step is chip bonding, wire bonding, TAB, flip chip (or C4: Controlled Collapse Chip Connection), flip chip (or C4) during the process. Controlled Collapse Chip Connection

The term flip chip is derived from a shape in which a bare chip is inverted and bonded to a substrate.

Flip chips were developed by IBM in the early sixties to replace manual wire bonding with low reliability. At the time of development, IBM was known under the name Controlled Collapse Chip Connection (C4).

In this method, solder bumps are deposited on metallization sites formed on Al pads of bare chips, and the solder is spherically shaped by a reflow soldering process.

Bare chips with solder are bonded to the substrate by a reflow soldering process. In order to deposit solder bumps, metallization such as Cr, Au, Ti, Cu, or the like is deposited on an aluminum pad on a bare chip surface by metallization or etching. The surface must be treated to allow the wetting of the solder, which is also called UBM (Under Bump Metallurgy).

During melting of the solder, a solder flows out of place by wetting, forming an active layer around the solder to prevent short-circuit from occurring in the circuit. The active layer serves to protect not only insulation but also circuits or silicon surfaces from impurities and moisture.

Solder is composed of 95% Pb-5% Sn (T _m = 315 ^o C) for ceramic substrates and 37% Pb-63% Sn (T _m = 183 ^o C for PCBs and other substrates) Eutectic composition).

Flip chip joins solder bumps using a reflow soldering process to obtain a self-aligning effect, and the pad (chip) in the internal circuit of the chip (chip) The location of the pad can be determined as needed, which simplifies the circuit design and reduces the length of the circuit to improve electrical performance. In addition, the resistance by the circuit line is reduced to reduce the power consumption and the heat of resistance, and the highest integration density among the packaging methods.

Flip chip method is widely used in communication equipment because it can increase the integration density and reduce the power consumption, and is the basic element of COB and MCM. As the integration density increases, the amount of heat generated per unit area also increases, so cooling is very important. In order to connect a flip chip and a circuit line of a substrate, a multi-layer substrate is often used, and the connection between the substrates is made through a via. Underfill that fills between the chip and the substrate with epoxy resin to prevent fracture of the joint due to thermal stress caused by CTE mismatch of the substrate, chip and solder joints. Work to reduce thermal stress and increase fatigue life.

Chip scale packaging (CSP) is a method for improving the stability of bare chips. The CSP is a package of bare chips. Due to the packaging, the area of the CSP increases within 20%, but the stability is increased and handling is easy.

1A to 1F are flow charts of a flip chip bump forming method according to the prior art.

Referring to FIG. 1A, after forming a copper pad 102 on an insulating material 101, a solder resist 103 is coated.

Referring to FIG. 1B, the solder resist 103 is exposed / developed to remove the solder resist 103 on the copper pad 102.

Referring to FIG. 1C, Ni / Au plating 104 and 105 may be performed on an upper portion of the copper pad 102 from which the solder resist 103 is removed.

Subsequently, referring to FIG. 1D, a metal mask 106 is coated, a solder 107 is deposited on the Ni / Au plating layer, and a metal mask 106 is coated as shown in FIG. Planarize.

Figure 1f shows the final product of the bump flattened by the bump planarization process of Figure 1e.

On the other hand, in order to cope with the trend of light and short reduction of the set products, the circuit density of the substrate for the BGA / CSP package is increasing. Efforts have been made to fine-tune patterns (fine), finer via holes, and finer solder resist opening size (Fine) to improve circuit density.

Among many packaged products, the trend of fineness of flip chip package, which is particularly difficult, is as follows.

Bump Pitch refinement: 250㎛ → 150㎛ → 120㎛

Solder resist open size refinement: 150㎛ → 80㎛ → 40㎛

In particular, there is a tendency to manufacture solder bumps, especially when manufacturing flip chip substrates, and there is a limit to bump printing using a general metal mask.

In addition, solder resist opening is also limited to around 80 μm using a glass mask.

Accordingly, the present invention has been made in order to meet the above needs, by using a film-type solder resist and using a laser drill to simultaneously solve the miniaturization of the solder resist open size and the bump refinement of the flip chip substrate. It is an object of the present invention to provide a flip chip bump forming method.

The present invention for achieving the above object, the first step of laminating a film-type solder resist on the insulating material, the first laser processing to open the solder resist; A second step of forming an electroless copper plating layer after the first step, laminating a dry film, and opening the dry film by second laser processing; A third step of filling a copper pad in the open portion of the solder resist in the first step, and a solder in the open portion of the dry film in the second step; And a fourth step of etching the dry film and the electroless copper plating layer and performing a surface treatment.

Now, with reference to the drawings of Figure 2a will be described in detail a preferred embodiment of the present invention.

2A to 2H are flowcharts of a flip chip bump forming process according to an embodiment of the present invention.

Referring to FIG. 2A, a solder resist 202 is laminated on the insulating material 201 using a film type, which is used to replace the ink type of the solder resist 202.

The solder resist 202 refers to a film that covers the wiring pattern so that unwanted connection is not caused by soldering that is made during component mounting.

The solder resist 202 also serves as a protective material for protecting circuits on the surface of the BGA / CSP substrate and is generally in the form of paint.

In general, the wiring pattern is made by corrosion of the copper foil coated on the substrate, so in principle, it can be said to be a spiral without an insulation coating. As the density of BGA / CSP substrates increases, the spacing between wirings becomes narrower, which causes a problem of short-circuit and misconnection between wirings, similarly to the use of uncovered electric wires.

In particular, when soldering electronic components onto BGA / CSP substrates, the BGA / CSP substrates are exposed to melting solder, which may result in undesired connections. This leads to serious defects that prevent the electronics from operating normally.

In order to prevent such defects, a film for shielding other portions except for the land periphery necessary for soldering the component for the purpose of covering the spiral wiring is called a solder resist 202. The solder resist 202 is also called a solder mask by applying the meaning of shielding.

The plating resist or the corrosion resist is temporarily used during the manufacturing process and is later removed all while the solder resist 202 is different from other resists in that the parts remain in the product even after mounting and perform insulation and protection. The resist ink for solder resist is called PSR (Photo imageable Solder Resist ink).

However, the solder resist ink is not easy to adjust the thickness, there was a problem that is severely affected by the desmear.

Thus, instead of using solder resist ink, a film type solder resist 202 is used.

As such, when the solder resists 202 are laminated using the film type, the thickness is easily controlled and is not severely affected by the desmear.

Referring to FIG. 2B, the solder resist 202 is etched using a laser drill. The use of a laser drill allows for fine opening. In this case, preferably, solder resist opening of 50 μm or less is performed on the flip chip BGA / CSP substrate. And bump pitch of 1200 micrometers or less is formed with respect to a flip chip BGA / CSP board | substrate.

Here, the laser drill is highly flexible, and laser processing, which can process complex shapes or small quantities of products without expensive mold costs, is suitable for the recent market situation of small quantity batch production, and also applies to prototype processing.

The optical energy is concentrated on the surface to melt and evaporate a part of the material, taking a desired shape. A computer program can easily process complex shapes, and even composite materials that are difficult to cut by other methods can be processed. . Cut diameters as small as 0.005mm are possible, and the thickness range is wide.

It is preferable to use a YAG (Yttrium Aluminum Garnet) laser or a CO ₂ laser as a laser drill. The YAG laser is a laser capable of processing both a copper foil layer and an insulating layer, and the CO ₂ laser is a laser capable of processing only an insulating layer.

Referring to Figure 2c, after changing the desmear chemicals to form a desmear and surface roughness, the electroless plating layer 203 is formed, wherein the thickness is about 0.5 ~ 1.5㎛.

Desmear removes smear by chemical method and at the same time, fine corrosion occurs in epoxy of inner wall of hole, which enhances adhesion of copper particles during electroless copper plating. Chemicals used in desmear include sulfuric acid, chromic acid, permanganic acid, and plasma.

Electroless plating is the only plating method for imparting conductivity to the surface of non-conductors such as resins, ceramics, glass, and the like.

Electroless copper plating is plating on insulators, so reactions with electrically charged ions cannot be expected. Electroless copper plating is carried out by precipitation reactions, which are promoted by catalysts.

To deposit copper from the plating solution, a catalyst must be attached to the surface of the material to be plated. This indicates that electroless copper plating requires a lot of pretreatment. Electroless copper plating is generally difficult to thicken the plating film, and even the physical properties are inferior to the electrolytic copper plating, but in recent years, its properties have been greatly improved and its use has been expanded.

Electroless copper plating is performed by immersing the substrate in a plating solution so that not only the inner wall of the hole but also all parts of the substrate are plated.

Electroless copper plating is a degreasing process that removes oxides and foreign substances, especially oils and fats, present on the surface of copper foil with chemicals containing acid or alkali surfactants. Soft corrosion process, pre-catalytic process to immerse the substrate in a low concentration of catalyst chemical prior to catalysis, to prevent contamination or change of concentration of the chemical used in the catalytic treatment step, catalyst particles on the copper foil and epoxy surface of the substrate Activation process of forcibly ionizing Sn and Pb to increase the conductivity and affinity of copper plating while Pd-Sn is applied to the surface of the substrate and the inner wall of the hole through the catalyst treatment. It consists of a thawing plating process.

Meanwhile, copper plating is classified into heavy copper plating (heavy copper, 2㎛ or more), medium copper plating (medium copper, 1 ~ 2㎛), and light copper plating (light copper, 1㎛ or less) according to the thickness. The electroless copper plating layer 203 is formed by light copper plating at 0.5 to 1.5 µm.

Referring to FIG. 2D, after laminating the dry film 204 that withstands pattern plating, and referring to FIG. 2E, the hole diameter is processed to be smaller than that of the primary laser drill in the hole machining using the secondary laser drill.

The dry film 204 is commonly referred to as D / F, and the D / F is made of a photosensitive material in the form of a film and a Mylar film and a cover film for imparting elasticity. The cover film is peeled off in the lamination process where D / F is coated on the copper clad laminate. Mylar film remains after lamination to protect the photoresist film and is stripped off prior to the development process.

D / F is applied to the substrate that has improved the adhesion of D / F by the front face treatment, and during lamination, D / F is thermo-compressed with a heated roller to secure additional adhesion with the substrate. Peel off the cover film and leave the Mylar film to protect the photoresist film, a photoresist.

When performing lamination of the D / F 204, in particular, it is necessary to thoroughly prevent contamination of foreign substances such as dust.

Factors affecting the quality of the lining process include the temperature of the pressing roller, the pressing speed, and the temperature of the substrate.

Referring to FIG. 2F, copper is laminated in holes processed using a primary laser drill, and solder is deposited in holes processed using a secondary drill. In the case of PBGA, the ratio of Sn and Pb is 63% vs. 37%, and in the case of PBGA, 62%, 36%, and 2% are made of Sn, PbGA, and CSP. It is. In the case of CBGA, the solder has a ratio of Sn to Pb of 10% to 90%.

Referring to FIG. 2G, the dry film 204 is removed using pattern plating, and referring to FIG. 2H, the electroless copper plating layer 203 is removed using flash etching.

Then, surface treatment is performed to prevent oxidation of copper and final finishing treatment is performed on the substrate. This is to prevent oxidation of the exposed copper foil portion without being covered with the solder resist 202, to improve solderability of the component to be mounted, and to impart good conductivity. HASL (Hot Air Solder Leveling) has been widely used as a representative method for surface treatment. Recently, a new method has been adopted due to various requirements for surface treatment, and here, OSP (Organic Solderability Preservation) treatment is performed.

OSP is called pre-flux and is divided into organic solvent type and water soluble. The organic solvent type uses a method of applying a resin film to the entire substrate by using a roll coating or spray. The organic solvent type preplex is gradually decreasing its use ratio.

In the case of water-soluble preplexes, there is a difficulty in use because there is no heat resistance against high heat, but recently, heat resistance is improved and low-cost products have been developed and used. In general, the preflex coating method has a problem inferior in heat resistance and solderability compared to other surface treatment methods.

According to the present invention as described above, there is an effect to enable the solder resist opening of 50㎛ or less with respect to the flip chip BGA / CSP substrate.

In addition, according to the present invention, the flip chip bump pitch of 120 μm or less can be realized with respect to the flip chip BGA / CSP substrate.

In addition, according to the present invention, the bump printing process and the flattening process are eliminated with respect to the flip chip BGA / CSP substrate, thereby reducing the cost of the metal mask, planarizing jig, and the like used in the process.

In addition, according to the present invention, the surface treatment of flip chip BGA / CSP substrate using the Cu / Sn plating rather than Ni / Ai plating has the effect of reducing the cost.

What has been described above is just one embodiment for carrying out the method of forming a flip chip bump according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims Without departing from the gist of the present invention, those skilled in the art to which the present invention pertains to the technical spirit of the present invention to the extent that various modifications can be made.

1A to 1F are flow charts of a flip chip bump forming method according to the prior art.

2A to 2H are flowcharts of a flip chip bump forming process according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

201: insulating material 202: solder resist

203: electroless plating layer 204: dry film

205: copper pad layer 206: solder

Claims (4)

A first step of laminating a film type solder resist on an insulating material and opening the solder resist by first laser processing; A second step of forming an electroless copper plating layer after the first step, laminating a dry film, and opening the dry film by second laser processing; A third step of filling a copper pad in the open portion of the solder resist in the first step, and a solder in the open portion of the dry film in the second step; And And etching the dry film and the electroless copper plating layer and performing a surface treatment. The method of claim 1, The laser processing is a flip chip bump forming method characterized in that the processing using a YAG (Yttrium Aluminum Garnet) laser or CO ₂ laser. The method of claim 1, And a solder resist open size of the first step is 50 μm or less. The method of claim 1, The bump pitch of the first step is 120㎛ or less characterized in that the bump formation method.