KR20050048900A - Memory module having the mirror type package of semiconductor memory chips - Google Patents

Abstract

A memory module having semiconductor memory chips in a mirrored package is disclosed. The memory module includes a first semiconductor memory chip and a second semiconductor memory chip. The first semiconductor memory chip includes a normal metal redistribution layer and the second semiconductor memory chip includes a bonding pad of a mirrored metal redistribution layer symmetrically arranged with respect to the bonding pad of the normal metal redistribution layer. . The bonding pads of the normal metal redistribution layer and the bonding pads of the mirrored metal redistribution layer are connected to a stub connected to the channel of the memory module. Since the memory module has a mirrored package using a metal redistribution layer, the reflected wave on the channel can be reduced by reducing the burden of chip design and minimizing the length of the stub.

Description

Memory module having the mirror type package of semiconductor memory chips

The present invention relates to a memory module, and more particularly, to a memory module having semiconductor memory chips in a mirror type package using a metal rerouting layer.

Generally, to increase the capacity of a memory, a plurality of memories are modularized and connected to one channel (or transmission line). The memory module is a set of semiconductor devices having a single function, and may be generated by mounting a plurality of semiconductor memory chips interconnected on a printed circuit board (PCB).

1 is a cross-sectional view of a memory module including semiconductor memory chips that do not have a mirrored package. Referring to FIG. 1, the memory module 100 includes a printed circuit board 110, a first semiconductor memory chip 120, and a second semiconductor memory chip 130. The first and second semiconductor memory chips 120 and 130 are package level chips and are mounted on both sides of the printed circuit board 110.

Pins 121 of the first semiconductor memory chip 120 are connected to the pins 131 of the corresponding second semiconductor memory chip 130 through stubs. The pins 121 and 131 may also be referred to as solder balls in a ball grid array type package. Meanwhile, in FIG. 1, only some of the stubs are shown by reference numerals 111, 113, and 115. Although not shown in FIG. 1, the stubs are connected to a channel to which another memory module is connected.

On the other hand, as the operation speed of the semiconductor memory chip becomes faster, the length of the stubs should be minimized to minimize the reflected wave on the channel to which the stubs are connected. In order to minimize the length of the stubs, the corresponding pins of semiconductor memory chips must be connected at the shortest distance through the stubs. Description of this is described with reference to FIG. 2.

2 is a cross-sectional view of a memory module including semiconductor memory chips of a mirrored package. Referring to FIG. 2, the memory module 200 includes a printed circuit board 210, a first semiconductor memory chip 220, and a second semiconductor memory chip 230. The first and second semiconductor memory chips 220 and 230 are package level chips and are mounted on both sides of the printed circuit board 210.

The pins 221 of the first semiconductor memory chip 220 are connected to the pins 231 of the corresponding second semiconductor memory chip 230 at the shortest distance through the stubs 211 to 218. The stubs 211-218 are connected to a channel (not shown) to which another memory module is connected. As shown in FIG. 2, the fins 221 and 231 of the first and second semiconductor memory chips 220 and 230 are symmetrically arranged (or arranged) with each other to reduce the reflected wave on the channel of the memory module. This is called a mirror type package.

3 is a cross-sectional view of a semiconductor memory chip of a mirror type package according to the prior art. Referring to FIG. 3, the semiconductor memory chip 300 may be a wafer level semiconductor memory chip 305, an electrode pad 310, a dielectric layer 315, a metal redistribution layer 320, and a bonding wire ( bonding wires 325, 330, bonding pads 335, 340, printed circuit board 345 for packaging, and a plurality of pins 351-358.

The semiconductor memory chip 300 corresponds to the first semiconductor memory chip 220 or the second semiconductor memory chip 230, which is a package level of FIG. 2. In addition, the semiconductor memory chip 305 at the wafer level includes a logic circuit for implementing a mirrored package function, and the bonding pads 335 and 340 are connected to each other by a metal line. 358).

4 is a plan view illustrating a bottom surface of the semiconductor memory chip of FIG. 3. Referring to FIG. 4, a plurality of pins are disposed on lower surfaces of the first or second semiconductor memory chips. In order to implement the semiconductor memory chips of the mirror package, a mirror function enable pin (MF, 400) is disposed at a position corresponding to A row 9 column of a pin configuration or ball configuration.

Referring to FIGS. 3 and 4, a method of implementing semiconductor memory chips of a mirror type package is as follows. That is, the logic circuit inside the semiconductor memory chip 305 at the wafer level performs a switching operation in response to a signal input to the mirror function enable pin MF 400 from the outside, and performs the switching operation. As a result, the bonding pads of the second semiconductor memory chip 230 of FIG. 2 are symmetrically arranged with respect to the bonding pads of the first semiconductor memory chip 220 of FIG. 2.

However, since the semiconductor memory chips of the mirror-type package according to the related art have separate pins and logic circuits, it is a burden when designing a semiconductor chip and the signal quality due to the transistors in the logic circuits is reduced. Can be degraded.

Accordingly, an aspect of the present invention is to provide a memory module including semiconductor memory chips of a mirror package using a metal redistribution layer without using a separate pin and logic circuit to implement a mirror package. have.

According to an aspect of the present invention, a memory module includes a first semiconductor memory chip including a normal metal redistribution layer and symmetrically arranged with respect to a bonding pad of the normal metal redistribution layer. And a second semiconductor memory chip comprising bonding pads of the mirrored metal redistribution layer, wherein the bonding pads of the normal metal redistribution layer and the bonding pads of the mirrored metal redistribution layer are stubs connected to the channels of the memory module. It is characterized in that connected to.

In example embodiments, the memory module may further include a printed circuit board on which the first and second semiconductor memory chips are mounted and including the stub.

According to another aspect of the present invention, a memory module includes a package level first semiconductor memory chip including a normal metal redistribution layer formed on a wafer level semiconductor memory chip, and the normal metal. A second semiconductor memory chip comprising first bonding pads of a mirrored metal redistribution layer produced on a wafer-level semiconductor memory chip symmetrically arranged with respect to the first bonding pads of the redistribution layer; Second semiconductor memory chips are mounted, and pins connected to the first bonding pads of the normal metal redistribution layer and pins connected to the first bonding pads of the mirrored metal redistribution layer corresponding to the pins are disposed at the shortest distance. And a printed circuit board comprising interconnecting stubs.

According to a preferred embodiment, the first semiconductor memory chip is mounted on the wafer level semiconductor memory chip, the second bonding pads and the second bonding are connected to the first bonding pads of the normal metal redistribution layer. And a printed circuit board for a package including pins connected to first bonding pads of the normal metal redistribution layer connected to the pads.

According to a preferred embodiment, the second semiconductor memory chip is mounted on the wafer level semiconductor memory chip, the second bonding pads and the second bonding are connected to the first bonding pads of the mirrored metal redistribution layer. And a printed circuit board for a package including pins connected to first bonding pads of the mirrored metal redistribution layer connected to the pads.

The memory module according to the present invention can implement a mirror-type package using a metal redistribution layer without including a separate pin and logic circuit, thereby reducing the burden of chip design and minimizing the length of the stub, thereby reducing the reflected wave on the channel. Can be reduced.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

5 is a cross-sectional view of a semiconductor memory chip of a mirror type package according to an embodiment of the present invention. Referring to FIG. 5, the semiconductor memory chip 500 of the mirrored package includes a semiconductor memory chip 505, an electrode pad 510, a dielectric layer 515, and a metal redistribution layer 520 at a wafer level. , Bonding wires 525, 530, bonding pads 535, 540, printed circuit board 545 for the package, and a plurality of pins 551-558. The bonding pads of the metal redistribution layer 520 are connected to the bonding pads 535, 540 through the bonding wires 525, 530. The bonding pads 535 and 540 are connected to the corresponding plurality of pins 551 to 558 through metal wires.

The semiconductor memory chip 500 corresponds to the first semiconductor memory chip 220 or the second semiconductor memory chip 230, which is a package level of FIG. 2. Accordingly, the metal redistribution layer 520 may be a normal type metal redistribution layer or a mirrored metal redistribution layer, which will be described later.

FIG. 6A is a plan view of the normal metal redistribution layer shown in FIG. 5. 5 and 6A, the normal metal redistribution layer (corresponding to 520 of FIG. 5) includes electrode pads 611-620, metal redistributions 641-650, and bonding pads 621. 630) is generated. The metal redistributions 641-650 change the position of the bonding pads so that the bonding pads 621-630 are disposed at the edge of the mirrored metal redistribution layer.

The electrode pads 611-620 correspond to the electrode pad 510 of FIG. 5. The electrode pads 611-620 are connected to the bonding pads 621-630 through metal redistributions 641-650. The bonding pads 621-630 are connected to the bonding pads 535, 540 of FIG. 5 through the bonding wires 525, 530 of FIG. 5.

FIG. 6B is a top view of the mirrored metal redistribution layer shown in FIG. 5. 5 and 6B, the normal metal redistribution layer (corresponding to 520 of FIG. 5) includes electrode pads 711-720, metal redistributions 741-750, and bonding pads 721. 730) is generated. The metal redistributions 741-750 change the position of the bonding pads such that the bonding pads 721-730 are disposed at the edge of the mirrored metal redistribution layer.

The electrode pads 711-720 correspond to the electrode pad 510 of FIG. 5. The electrode pads 711-720 are connected to the bonding pads 721-730 through the metal redistributions 741-750. The bonding pads 721-730 are connected to the bonding pads 535, 540 of FIG. 5 through the bonding wires 525, 530 of FIG. 5.

6A and 6B, a method of implementing semiconductor memory chips of a mirror type package will be described below. Turning over the mirrored metal redistribution layer of FIG. 6B and facing the normal metal redistribution layer of FIG. 6A, the electrode pads [611-620], [711-720], the metal redistributions [641-650]. , [741-750]), and bonding pads [621-630], [721-720] each symmetrically overlap each other like a mirror. Accordingly, since the bonding pads [621-630] and [721-720] connected to the electrode pads through metal redistributions have a symmetrical arrangement with each other, a memory module including semiconductor memory chips in a mirrored package is provided. Can be implemented.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The memory module according to the present invention can implement a mirrored package using a metal redistribution layer without including a separate pin and logic circuit, thereby reducing the burden of chip design and minimizing the length of the stub, thereby reducing the reflected wave on the channel. Can be reduced.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a cross-sectional view of a memory module including semiconductor memory chips that do not have a mirrored package.

2 is a cross-sectional view of a memory module including semiconductor memory chips of a mirrored package.

3 is a cross-sectional view of a semiconductor memory chip of a mirror type package according to the prior art.

4 is a plan view illustrating a bottom surface of the semiconductor memory chip of FIG. 3.

5 is a cross-sectional view of a semiconductor memory chip of a mirror type package according to an embodiment of the present invention.

FIG. 6A is a plan view of the normal metal redistribution layer shown in FIG. 5.

FIG. 6B is a plan view of a mirror metal redistribution layer corresponding to FIG. 6A.

Claims (5)

A first semiconductor memory chip comprising a normal metal redistribution layer; And A second semiconductor memory chip comprising bonding pads of the mirror metal redistribution layer symmetrically arranged with respect to the bonding pads of the normal metal redistribution layer, And bonding pads of the normal metal redistribution layer and bonding pads of the mirrored metal redistribution layer are connected to a stub connected to a channel of the memory module. The method of claim 1, wherein the memory module And a printed circuit board on which the first and second semiconductor memory chips are mounted and including the stub. A package level first semiconductor memory chip comprising a normal metal redistribution layer formed on a wafer level semiconductor memory chip; A second semiconductor memory chip comprising a mirrored metal redistribution layer formed on a wafer level semiconductor memory chip symmetrically arranged with respect to the normal metal redistribution layer; And Fins connected to the first and second semiconductor memory chips and mounted to the first bonding pads of the normal metal redistribution layer and the first bonding pads of the mirrored metal redistribution layer corresponding to the fins. And a printed circuit board comprising stubs for interconnecting the shortest distances. The semiconductor memory chip of claim 3, wherein the first semiconductor memory chip is A second bonding pad connected to the first bonding pads of the normal metal redistribution layer and the normal metal redistribution layer connected to the second bonding pads, mounted on the wafer level semiconductor memory chip. 1. The memory module of claim 1, further comprising a printed circuit board for packaging including pins connected to the bonding pads. The method of claim 4, wherein the second semiconductor memory chip is A second bonding pad connected to the first bonding pads of the mirrored metal redistribution layer and the mirrored metal redistribution layer connected to the second bonding pads, mounted on the wafer level semiconductor memory chip. 1. The memory module of claim 1, further comprising a printed circuit board for packaging including pins connected to the bonding pads.