KR20050045096A - Liquid crystal display - Google Patents

Abstract

The present invention improves image quality by regularly changing screen brightness when adjusting the brightness of a screen in a liquid crystal display. According to an embodiment of the present invention, a first control signal blinking from the signal control unit or the outside is applied to the first inverter control unit. The signal delay unit receives the first blinking control signal and generates a second blinking control signal delayed by a predetermined time from the phase of the first blinking control signal and applies it to the second inverter controller. Accordingly, the first and second inverter controllers operate on the basis of the first and second blinking control signals respectively applied to apply the control signals for controlling the blinking operation of the connected lamps, respectively. Therefore, the flickering timings of the lamp controlled by the first inverter control unit and the lamp controlled by the second inverter control unit are shifted from each other. Therefore, when the lamps are all turned on, when the lamps are turned off, and when only some lamps are turned on, the brightness of the screen changes sequentially so that finer brightness of the screen can be adjusted.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

Display devices used in monitors and TVs of computers include light emitting diodes (LEDs), electroluminescence (EL), vacuum fluorescent displays (VFDs), and electroluminescent devices (fields). emission display (FED), plasma display panel (PDP), and the like, a liquid crystal display (LCD) that does not emit light by itself and requires a light source.

A general liquid crystal display device includes two display panels provided with a field generating electrode and a liquid crystal layer having dielectric anisotropy interposed therebetween. A voltage is applied to the field generating electrode to generate an electric field in the liquid crystal layer, and the voltage is changed to adjust the intensity of the electric field, thereby adjusting the transmittance of light passing through the liquid crystal layer to obtain a desired image.

In this case, the light may be a separate artificial light source or natural light. In the case of using a separately provided light source, the brightness of the entire screen is controlled by adjusting the ratio of the lighting time and the lighting time of the light source or the current flowing through the light source.

The latter method has a problem that when the lamp is kept at a low luminance, the magnitude of the current flowing through the lamp becomes small and the lighting of the lamp is very unstable and the lamp is easily turned off while the former method does not have such a problem. That is, the former method is preferred because the luminance can be easily controlled.

In general, in a liquid crystal display, the light source is disposed under the display panel assembly or at an edge thereof. All of them mostly include a plurality of light sources, and these light sources are turned on and off at the same time. Therefore, the change in brightness of the light source is large, which adversely affects natural screen brightness. In particular, when the ratio of the lighting time and the unlighting time of the light source is changed, the brightness of the screen may be greatly changed, and the screen brightness does not sequentially change and suddenly darkens or becomes bright.

Therefore, the technical problem to be achieved by the present invention is to improve the image quality of the liquid crystal display by changing the brightness of the light source regularly.

The liquid crystal display device for achieving the technical problem

A plurality of pixels arranged in a matrix form,

A plurality of light sources for supplying light to the pixels based on a plurality of flashing control signals

Each of the flashing control signals includes a lighting section for turning on the light source and an off section for turning off the light source, and the phases of the flashing control signals for flashing the light sources are different from each other.

The brightness of the liquid crystal display may be determined by the ratio of the lighting time and the lighting time of the light source.

Preferably, the liquid crystal display further includes an inverter for blinking at least two of the light sources, wherein the plurality of blink control signals include first and second blink control signals for blinking the at least two light sources, respectively. The first and second blink control signals may be applied to the inverter.

The inverter may further include a signal delay unit configured to delay the first flashing control signal to generate the second flashing control signal.

The inverter may further include: a first lamp driver for applying an AC voltage to at least one of the light sources and blinking; a second lamp driver for applying an AC voltage to the other one of the light sources and blinking; based on the first flashing control signal; The display device may further include a first inverter controller controlling a first lamp driver, and a second inverter controller controlling the second lamp driver based on the second flashing control signal.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an exploded perspective view of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is a liquid crystal according to an embodiment of the present invention. It is an equivalent circuit diagram of one pixel of a display device.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the 500, the lamp unit 940 for irradiating light to the liquid crystal panel assembly 300, the inverter unit 920 connected thereto, and a signal controller 600 for controlling them. It includes.

Meanwhile, as shown in FIG. 2, when the LCD according to the exemplary embodiment of the present invention is structurally shown, the liquid crystal module 350 and the liquid crystal module 350 including the display unit 330 and the backlight unit 340 are shown. Front and rear cases 361 and 362, a chassis 363, and a mold frame 364 to receive and fix the same.

The display unit 330 includes a liquid crystal panel assembly 300, a gate flexible printed circuit (FPC) substrate 410 and a data FPC substrate 510 attached thereto, and a gate PCB attached to the corresponding FPC substrates 410 and 510. printed circuit board 450 and data PCB 550.

The liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 and a liquid crystal layer 3 interposed therebetween, as shown in FIGS. 2 and 3. And a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , as shown in FIG. 3, arranged in a substantially matrix form. do.

The display signal lines G ₁ -G _n and D ₁ -D _m are provided on the lower panel 100 and transmit a plurality of gate lines G ₁ -G _n to transfer a gate signal (also called a “scan signal”). And a data signal line or data line D ₁ -D _m for transmitting a data signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 3, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage V _com is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, to implement color display, each pixel uniquely displays one of the three primary colors (spatial division) or each pixel alternately displays the three primary colors over time (time division) so that the desired color can be selected by the spatial and temporal sum of these three primary colors. To be recognized. 3 illustrates that each pixel includes a red, green, or blue color filter 230 in an area of the upper panel 200 corresponding to the pixel electrode 190. Unlike FIG. 3, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

In FIG. 2, the backlight unit 340 is positioned between the plurality of lamps 341 and the assembly 300 and the lamp 341 which are mounted under the liquid crystal panel assembly 300, and assembles light from the lamps 341. A light guide plate 342 and a plurality of optical sheets 343, which guide and diffuse to 300, and a reflector plate 344 positioned below the lamp 341 and reflecting light from the lamp 341 toward the assembly 300. It includes.

In this embodiment, a fluorescent lamp such as a cold cathode fluorescent lamp (CCFL) and an external electrode fluorescent lamp (EEFL) is used as the lamp 341. However, light emitting diodes (LEDs) and the like can also be used as lamps.

1, the lamp unit 940 includes a plurality of lamps 941-944 corresponding to the lamp 341 in FIG. 2. Although only four lamps are shown in the embodiment of the present invention, the number of lamps is not limited to this number, and the number of lamps may be added or subtracted as necessary.

The inverter unit 920 of FIG. 1 includes a first inverter control unit 921, a second inverter control unit 922, and first and second inverters to which a first flashing control signal V _dim1 , which is a pulse width modulation signal, is applied from the _outside . First to fourth lamp drivers 923-926 connected in pairs to the controllers 921 and 922, and a signal delay unit 927 connected between the first flashing control signal V _dim1 and the second inverter controller 922. ). The first inverter controller 921 is connected to the first and second lamp drivers 923 924, and the second inverter controller 922 is connected to the third and fourth lamp drivers 925 and 926. The first to fourth lamp drivers 923-926 are connected to the first to fourth lamps 941-944, respectively. The inverter unit 920 may be provided in a separately mounted inverter PCB (not shown) or may be provided in the gate PCB 450 or the data PCB 550. In addition, in the embodiment of the present invention, the signal delay unit 927 is included in the inverter unit 920, but may be included in a device other than the inverter unit 920, or may be separately mounted to the inverter PCB.

Polarizers (not shown) for polarizing light emitted from the lamp 341 are attached to outer surfaces of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

1 and 2, the gray voltage generator 800 is provided in the data PCB 550 and generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is mounted on each gate FPC substrate 410 in the form of an integrated circuit (IC) chip, and is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to externally. The gate signal consisting of a combination of the gate on voltage V _on and the gate off voltage V _off from the gate line G ₁ -G _n is applied.

The data driver 500 is mounted on each data FPC board 510 in the form of an IC chip, and is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 from the gray voltage generator 800. The data voltage selected from among the gray scale voltages is applied to the data lines D ₁ -D _m .

According to another exemplary embodiment of the present invention, the gate driver 400 and / or the data driver 500 are mounted on the lower panel 100 in the form of an IC chip, and according to another exemplary embodiment, other elements on the lower panel 100 are provided. Are integrated with them. In both cases, the gate PCB 450 and / or the gate FPC substrate 410 may be omitted.

The signal controller 600 for controlling operations of the gate driver 400 and the data driver 500 is provided in the data PCB 550 or the gate PCB 450.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2 and the like, the gate control signal CONT1 is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed. ) Is sent to the data driver 500.

The gate control signal (CONT1) includes a gate-on voltage vertical synchronization start signal (STV) for instructing the start of output of the (V _on), the gate-on voltage gated clock signal that controls the output timing of the (V _on) (CPV) and the gate-on An output enable signal OE or the like that defines the duration of the voltage V _on .

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of a horizontal period, a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage V _com . And the inversion signal RVS and the data clock signal HCLK for inverting the polarity of the data voltage with respect to (hereinafter, referred to as "polarity of the data voltage" by reducing "polarity of the data voltage with respect to the common voltage").

The data driver 500 sequentially receives and shifts image data R ', G', and B 'corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage. The image data R ', G', and B 'are converted into the corresponding data voltages by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the unit 800. This is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. When the switching element Q connected to the () is turned on, the data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage.

Inverter 920 comprises a first flash control signal DC lamp driving voltage according to (V _dim1) and a signal delay unit (927) a second flash control signal (V _dim2) output from the from the external or the signal controller 600, Is converted into AC voltage and transformed to the lamp unit 940, and the lamp unit 940 flashes according to the voltage, and the brightness of the lamp unit 940 is controlled. The operation of the inverter unit 920 will be described in detail below.

According to the operation of the inverter unit 920, the light emitted from the lamp unit 940 passes through the liquid crystal layer 3, and its polarization changes according to the arrangement of the liquid crystal molecules. This change in polarization is represented by a change in the transmittance of light by the polarizer.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

Then, the inverter unit 920 according to the present invention will be described in detail with reference to FIG. 4.

4 is a waveform diagram of first and second blinking control signals used in a liquid crystal display according to an exemplary embodiment of the present invention.

The inverter unit 920 receives the first blinking control signal V _dim1 from the outside or from the signal controller 600 to control the on / off operation of the lamp unit 940.

In more detail, the first blinking control signal V _{dim1 as} shown in FIG. 3 is applied to the first inverter controller 921 of the inverter unit 920. The pulse width of the first flashing control signal V _dim1 changes according to the desired brightness level of the screen, that is, the screen becomes bright when the pulse width of the high level state increases and vice versa.

When the first flashing control signal V _dim1 is applied to the first inverter controller 921, the first inverter controller 921 is a lamp of the lamp unit 940 detected by a current detector or the like (not shown). The operation states of the first and second lamps 941 and 942 are determined using a feedback control signal such as a current flowing in the lines 941 and 942. Thereafter, the first inverter controller 921 outputs an appropriate control signal to the first and second lamp drivers 923 and 924 according to the feedback control signal and the flashing control signal V _dim1 .

The first and second lamp drivers 923 and 924 may open or close a DC voltage from a DC / DC converter (not shown) or switch a current path according to a control signal from the first inverter controller 921. A sinusoidal voltage is generated and converted into a high voltage to generate a lamp driving signal (not shown), and apply it to the first and second lamps 941 and 942. When the first inverter controller 921 applies the lamp driving signal to the first and second lamps 941 and 942 of the lamp unit 940, the first and second lamps 941 and 942 are turned on to display the lamp driving signal and the lamp driving signal. Flowing current to synchronize. In this case, the ramp driving signal has a sine wave while the control signal from the first inverter controller 921 is high level but has a constant value while it is low level. But it may be the opposite.

On the other hand, the second inverter control section 922 is applied to the a first flash control signal (V _dim1) the phase of a predetermined time delayed second flash control signal (V _dim2) than 3, the first inverter control section ( A control operation such as 921 is performed.

To this end, the first blink control signal V _dim1 is applied to the signal delay unit 927, and the second blink control signal V _dim2 delayed by a predetermined time by the operation of the signal delay unit 927 is the second inverter controller. 922 is applied. The signal delay unit 927 is a circuit composed of a phase shifter, a delay element, or the like, and may be a circuit capable of delaying the phase of the input signal as desired. Also, the first and second flashing control signals V _dim1 and V _dim2 having a predetermined phase difference from the signal controller 600 or the outside may be respectively displayed by the first inverter controller 921 and the second inverter controller 922. May be applied to. In this case, the signal delay unit 927 is not necessary.

Thus, the first flash control signal (V _dim1) than the predetermined time phase-delayed second flash control signal the operation of the second inverter control section 922 is controlled by a (V _dim2), whereby the lamp unit 940 The lighting operation of the third and fourth lamps 943 and 944 is performed. At this time, the lighting timing and the lighting timing of the third and fourth lamps 943 and 944 are delayed in proportion to the time delayed from the lighting timing and the lighting timing of the first and second lamps 941 and 942.

Therefore, the flickering periods of the first and second lamps 941 and 942 and the third and fourth lamps 943 and 944 are shifted for a predetermined time, so that all the lamps 941-944 are not turned off or lighted at the same time. There is a section in which only the second lamps 941 and 942 or the third and fourth lamps 943 and 944 are lit.

That is, when all of the lamps 941-944 are turned on, when all of the lamps 941-944 are turned off, when only the first and second lamps 941-942 are turned on, and the third and fourth times. Since there exists a time when only the lamps 943 and 944 are lit, the inclination of the brightness change of the lamp becomes gentle. Therefore, the brightness of the screen is dimmed or brightened sequentially so that finer brightness can be adjusted.

According to the exemplary embodiment of the present invention, the brightness of the screen may be sequentially changed by controlling the flashing timing of the plurality of lamps to be shifted from each other, thereby reducing the phenomenon of sudden darkening or brightening of the screen during adjustment of the screen brightness. This realizes fine screen brightness control and reduces image deterioration due to irregular screen brightness changes.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a waveform diagram of first and second blinking control signals used in a liquid crystal display according to an exemplary embodiment of the present invention.

Claims (5)

A plurality of pixels arranged in a matrix form, A plurality of light sources for supplying light to the pixels based on a plurality of flashing control signals Including; Each of the flashing control signals includes a lighting section for turning on the light source and an off section for turning off the light source, The phases between the flashing control signals for flashing the plurality of light sources respectively differ Liquid crystal display. In claim 1, The brightness of the liquid crystal display device is determined by the ratio of the lighting time and the unlit time of the light source. In claim 2, And an inverter for blinking at least two of the light sources. The plurality of blink control signals include first and second blink control signals for blinking the at least two light sources, respectively, The first and second blink control signals are applied to the inverter Liquid crystal display. In claim 3, The inverter further includes a signal delay unit configured to delay the first blinking control signal to generate the second blinking control signal. In claim 4, The inverter, A first lamp driver to apply an alternating voltage to at least one of the light sources and blink; A second lamp driving unit which blinks by applying an alternating voltage to another one of the light sources; A first inverter controller which controls the first lamp driver based on the first blinking control signal, and A second inverter controller configured to control the second lamp driver based on the second blink control signal; Liquid crystal display further comprising.