KR20050040712A - 2-dimensional graphic decoder including graphic display accelerating function based on commands, graphic display accelerating method therefor and reproduction apparatus - Google Patents

Abstract

Disclosed are a two-dimensional graphic decoder including a command-based graphic output acceleration function, a graphic output acceleration method thereof, and an image reproducing apparatus.

According to an aspect of the present invention, there is provided a method of accelerating graphic output, the method comprising: interpreting graphic data, converting the graphic data into at least one accelerated command data, and storing the same; And outputting a graphic image by executing the stored at least one acceleration command data, wherein each step is performed independently. In particular, the acceleration command data may include a horizontal drawing command or a vertical drawing command for quickly drawing a graphic image on the screen, the graphic image obtained by interpreting graphic data to generate a polygon and scan-convert the generated polygon. desirable.

Accordingly, the output processing function of the 2D graphic image can be improved by using the graphic output acceleration command using the horizontal drawing.

Description

2-dimensional graphic decoder including graphic display accelerating function based on commands, graphic display accelerating method therefor and reproduction apparatus}

The present invention relates to the reproduction of an image, and more particularly, to a two-dimensional graphics decoder including a command-based graphics output acceleration function, a graphics output acceleration method thereof, and an image reproducing apparatus.

The image reproducing apparatus has a problem in that a severe computational burden is applied to a microprocessor (Central Processing Unit) by displaying all images displayed on the screen in pixels. Therefore, it is common for an image reproducing apparatus to provide a graphic output acceleration function in order to reduce the computational load on the CPU. Graphic display accelerating function is to reduce the computational load of the CPU by separately supporting graphic output processing instructions or by making the graphic output processing function into a hardware circuit inside the graphic output adapter. This means improving the output processing.

Conventional two-dimensional or three-dimensional graphics output acceleration technology uses a method of processing complex figures and images by improving the performance of the CPU. Examples include Intel's MMX (Multimedia Extension) technology or AMD's 3D Now technology. The MMX technology uses a method of increasing the processing speed of a CPU by adding a function to add or multiply multiple registers with one instruction to the CPU instruction set to perform a matrix addition or multiplication operation quickly. Such an instruction is called a single instruction multiple data (SIMD), and a plurality of SIMD instructions are included in the CPU instruction set as shown in FIG. 1A.

Another way of providing graphics output acceleration is to relieve the computational burden on the CPU by allowing the hardware circuitry for graphics output acceleration to assume the graphics processing functions that are commonly used. A game machine incorporating a conventional 2-dimensional graphic display accelerator chip includes a hardware circuit for accelerating 2-dimensional graphic output. The two-dimensional graphics output accelerator chip has a graphics output function in the form of an output function to handle graphics output, which can dramatically increase the CPU's speed in graphics mode. 1B illustrates a structure of an image reproducing apparatus including a 2D graphic output accelerator chip.

However, two-dimensional graphics output accelerator chips differ in form and implementation technology, such as line drawing, polygons, rectangle drawing, and block copy, which are supported by the graphics card manufacturers. In addition, it is difficult to perform a function when performing a graphic output operation that is not embedded in the graphic output accelerator chip, for example, drawing a figure including a curve. In addition, when the resolution is different from the resolution supported by the 2D graphics accelerator chip or when the true color is to be expressed at a high resolution, it is difficult to increase the graphics processing speed.

Another method of providing graphics acceleration is a three-dimensional geometry of the CPU using a three-dimensional graphic display accelerator chip that processes three-dimensional vector operations, as shown in FIG. 1C. This is a way to reduce the overhead of processing and rendering for output. Vector graphics are the smallest units constituting the screen and use polygons such as circles, rectangles, triangles, lines, etc., and are graphics expressed in the form of equations, and are also referred to as polygon graphics. Vector graphics use various special effects such as rendering, shading, and texturing to express delicate feelings such as curves and tones, and use 3D graphics accelerators to reduce the computational burden on the CPU.

However, when using a 2D vector graphic in a 3D graphic output acceleration environment, a vertex processing using a complex 3D vector is required when representing a shape including a circle or a curve constituting the figure. Therefore, a high performance graphics processor is required for the 3D operation and the image mapping operation of the texture image filling the vertices.

On the other hand, conventional consumer electronics (hereinafter, abbreviated as CE) has come to be combined with Internet technology, and requires a powerful graphic output function such as two-dimensional vector animation represented on an Internet web page. However, a conventional home appliance, for example, a video reproducing apparatus such as a DVD reproducing apparatus is provided with a CPU level of 150 MIPS rather than an 800 MIPS Pentium-class high performance CPU, thereby limiting graphic output processing performance. That is, only a limited range of graphic representations including text or simple images are possible, and there is a problem in that it is difficult to implement a 2D vector graphic animation function like an internet web page.

In addition, even if the conventional two-dimensional graphics output acceleration technology is used, hardware circuit design is complicated because complex two-dimensional vector computation and various curve processing functions must be included in the graphics output accelerator chip. In addition, it is not possible to include all two-dimensional curve processing functions in the hardware circuit. This is because there are various problems such as the size limitation of the hardware circuit, the increase in the price of the hardware circuit and peripheral components, the operation noise, and the noise generated by the fan due to the heat generation.

Accordingly, an object of the present invention is to provide a two-dimensional graphics decoder including a command-based graphics output acceleration function to solve the above problems.

In addition, another technical problem of the present invention is to provide a method for implementing a graphics output acceleration function.

Furthermore, another technical problem of the present invention is to provide an image reproducing apparatus having a two-dimensional graphics decoder including a command-based graphics output acceleration function.

In accordance with an aspect of the present invention, there is provided a method of accelerating graphic output, the method comprising: interpreting graphic data and converting the graphic data into at least one accelerated command data; And outputting a graphic image by executing the stored at least one acceleration instruction data, wherein each step is achieved by a method which is performed independently.

The acceleration command data may include a horizontal drawing command or a vertical drawing command for quickly drawing at least one graphic image on a screen obtained by analyzing graphic data to generate a polygon and scanning and converting the generated polygon. .

The converting and storing may be performed through separate software for interpreting various graphic data.

In the converting and storing, the converted at least one acceleration command may be stored in a predetermined memory area.

The outputting of the graphic image may be performed through a separate hardware circuit to increase the output speed of the graphic image.

The acceleration instruction data includes a pixel drawing instruction, a horizontal line drawing instruction in one color, a horizontal line applying bitmap image pattern, a horizontal line applying linear gradient image pattern, and a horizontal line applying radial gradient image pattern. Command, a command that repeats the previous command to a predetermined horizontal coordinate by increasing or decreasing the vertical or horizontal coordinates of the previous horizontal drawing command, and the fill data applied to the horizontal drawing command, or the size of a bitmap image or gradient pattern, AffineTranslate command to adjust the position, ColorTranslate command to convert the color of pixels drawn on the horizontal line, and branch to the acceleration instruction data location of another address to execute the acceleration instruction of the corresponding address.For example, the command to specify the output location and layer of the video output blended with the graphic image, the color of the background area except the video area blended with the graphic image, and the color of the video area when there is no video signal It is preferable to include at least one of the instructions.

On the other hand, according to another field of the present invention, the above technical problem, an acceleration command conversion unit for decoding the graphic data read through the external channel to convert to at least one acceleration command data simplified and stored in a predetermined memory area; And an acceleration command processor configured to execute at least one stored acceleration command data to output a graphic image, wherein the acceleration command converter and the acceleration command processor operate independently of each other using a predetermined memory area. Is achieved by.

The acceleration command conversion unit may generate a polygon by analyzing graphic data, convert the graphic data into at least one acceleration command data obtained as a result of scan conversion of the generated polygon, and store the result in a predetermined memory area. It is preferable to include a horizontal drawing command or a vertical drawing command to quickly draw a graphic image on the screen.

In addition, the acceleration command conversion unit is preferably implemented in a separate software for interpreting a variety of graphic data.

The acceleration command processor is preferably implemented as a separate hardware circuit to increase the output speed of the graphic image.

The external channel preferably includes a removable storage medium that can be easily separated from the playback device, a storage medium built into the playback device, or a network medium.

On the other hand, according to another field of the present invention, the above-described technical problem is achieved by a reproduction device comprising the above-described graphic decoder.

In addition, the reproduction apparatus preferably outputs a single image by overlaying the graphic image output through the graphic decoder and the video output by decoding the AV data read from the external channel.

On the other hand, according to another field of the present invention, the above-described technical problem is achieved by a recording medium which records a program for performing on the computer the method for accelerating the aforementioned graphic output.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The two-dimensional graphic decoder including a command-based graphic output acceleration function according to the present invention is a graphic data presentation engine for interpreting graphic data input from an external channel, converting the graphic data into an acceleration command, and storing the same. It includes a two-dimensional graphics output acceleration command processor for outputting graphics to the screen. In particular, the two-dimensional graphics output acceleration command processor is preferably implemented in hardware circuitry to improve the graphics output processing performance. Also, the graphic output acceleration instruction is preferably implemented as a horizontal drawing instruction. Accordingly, the command-based graphic output acceleration function can be implemented, and the graphic output processing performance is improved. Furthermore, a method of directly receiving horizontal drawing commands from an external channel and inputting the horizontal drawing commands to a 2D graphic output acceleration command processor without conversion by the graphic data presentation engine may be provided.

2 is a block diagram of an image reproducing apparatus having a two-dimensional graphics decoder including a command-based graphics output acceleration function according to a preferred embodiment of the present invention.

Referring to FIG. 2, the image reproducing apparatus 1 according to the present invention includes a reader 210 and 212, an input controller 213, memories 220, 222 and 224, an AV decoder 240, and two-dimensional graphics. The decoder 200 includes a frame buffer memory 260 and a DA converter 270.

The readers 210 and 212 read AV data or graphic data from external channels. The external channel refers to a medium for reading image data such as AV data (Audio-Visual Data) or graphic data, and includes a recording medium such as an optical disc or a network medium such as the Internet. The AV data refers to video data compressed and encoded according to a standard such as a moving picture expert group (MPEG). Graphic data generates graphic data such as markup documents such as HTML, image files such as Joint Photographic Experts Group (JPEG) files or Portable Network Graphics (PNG) files, Flash files from Macromedia, Java, font data, etc. Collectively, all possible application resources. The input controller 214 loads the AV data or the graphic data into each memory provided separately. If the AV data and the graphic data are multiplexed into one file, a function of demultiplexing them may be included.

The memories 220, 222, and 224 include a first memory 220, a second memory 222, and a third memory 224. The first memory 220 stores the AV data read from the external channel by the readout units 210 and 212 and the input control unit 214 as a buffer memory. The second memory 222 stores graphic data read from an external channel. The third memory 224 is a memory used by the two-dimensional graphics decoder 200 which will be described later. The third memory 224 stores graphic output acceleration instructions and fill data obtained by converting graphic data. The first memory 220, the second memory 222, and the third memory 224 may be embodied as separate memories or may be implemented by dividing addresses within a single integrated memory according to a designer's intention. have.

The AV decoder 240 decodes the AV data stored in the first memory 220 and outputs a moving image.

The two-dimensional graphics decoder 200 includes a graphic data presentation engine 250 and a two-dimensional graphics output acceleration instruction processor 252. The graphic data presentation engine 250 interprets the read graphic data, converts the graphic data into graphic output acceleration instructions and fill data, and stores the converted graphic data in the third memory 224. The graphic presentation engine is preferably implemented in software running on a CPU to flexibly interpret various types of graphic data. Hereinafter referred to as "presentation engine 250". The 2D graphic output acceleration command processor 252 outputs the 2D graphic by executing the graphic output acceleration command and the fill data stored in the third memory 224. The 2D graphic acceleration command processing unit 252 is preferably implemented as a hardware circuit in order to quickly perform the simplified graphic output acceleration command and the fill data. Hereinafter, the output acceleration command processor 252 will be abbreviated.

The frame buffer 260 stores a video output from the AV decoder 240 and a 2D graphic image output from the 2D graphic decoder 200. The video and the 2D graphic image are blended, and the blended digital signal is converted into an analog signal through the DA converter 270 and displayed on the screen. Accordingly, an image reproducing apparatus such as a DVD or a DTV may provide interactive contents displaying two-dimensional graphic images associated with a moving image together on one screen.

If a conventional two-dimensional graphics output accelerator is used, the two-dimensional graphics output accelerator such as a line, a rectangle, or a circle may be processed by analyzing the graphic data described above, for example, text or table information included in a markup document. Must be converted to an output function. You must also include a function that parses a JPEG or PNG file and outputs a bitmap. You should also include polygon and curve handling features such as other Flash files or Java curves, straight lines, or polygons. Accordingly, the hardware structure of the conventional two-dimensional graphics output accelerator is complicated.

However, the 2D graphic decoder 200 according to the present invention may implement a graphic output acceleration function more simply by using a horizontal drawing command described later as a graphic output acceleration command. Hereinafter, the two-dimensional graphics decoder 200 according to the present invention will be described in more detail.

3 is a diagram illustrating an image reproducing process using a command-based graphic output acceleration function according to a preferred embodiment of the present invention.

Referring to FIG. 3, the 2D graphic decoder 200 interprets the graphic data 322 read from an external channel, converts the graphic data 322 to the graphic output acceleration command and the fill data 324, and stores the graphic data 322 in the third memory. Also, the stored graphic output acceleration command and the fill data are read to output a two-dimensional graphic image. Hereinafter, the graphic output acceleration command and the fill data 324 stored in the third memory are collectively referred to as "graphic output acceleration command data". The screen 280 displays a video decoded by the AV decoder 240 and a 2D graphic image interpreted by the 2D graphic decoder 200 together.

More specifically, the presentation engine 250 interprets the graphic data 322 to generate and store the graphic output acceleration command data 324 in the third memory, and when the graphic output acceleration command data for the screen to be drawn is completed, The PAGE SETUP signal is sent to the output acceleration command processor 252 to display the screen. The output acceleration command processor 252 receiving the page setup signal reads the graphic output acceleration command data 324 stored from the third memory, interprets the execution, and executes the graphic output acceleration command data 324. The graphic image created by executing graphic output acceleration command data is blended with the video and stored in the frame buffer. Stored 2D graphic images and video are displayed on one screen overlayed.

4 is a view for explaining in detail the structure of the two-dimensional graphics output acceleration command processor shown in FIG.

Referring to FIG. 4, the output acceleration instruction processor 252 includes a latch unit 410 for outputting a page, a graphic instruction decoder 420, and a rendering circuit 430.

The latch unit 410 reads the page output state and selects an active page. The graphic instruction decoder 420 reads and interprets the graphic output acceleration instruction data stored by the presentation engine 250 from the third memory and executes the selected graphic output acceleration instruction in the rendering circuit 430. The graphic image output from the rendering circuit 430 is blended and stored together with the moving image in the frame buffer 260, and the 2D graphic image and the moving image stored in the frame buffer are overlaid and displayed on one screen.

More specifically, referring to FIGS. 2, 3, and 5, the presentation engine 250 stores the graphic output acceleration command data 324 generated by interpreting the graphic data for the page set-up, in the third memory 224. Store in A detailed process of converting the graphic data into the graphic output acceleration command data will be described later. In addition, the presentation engine 250 reads the page status register PAGE_STATUS_1 or PAGE_STATUS_2 to know the output state of the two-dimensional graphics page to be output to the frame buffer memory through the output acceleration instruction processor 252. If the read page state is busy, the page is being output on the screen by the output acceleration command processor 252, and thus, another page having the page state idle is selected. Also, the start address of the graphic output acceleration instruction data of the selected page in the third memory is set as a value of a register (PAGE_IP_PTR_1 or PAGE_IP_PTR_2) indicating the graphic instruction. Next, the output acceleration command processor 252 sets the selected page to a page display register (PAGE_DISPLAY) value in order to output the corresponding page to the screen. This series of steps is called the "page setup process".

On the other hand, the latch unit 410 included in the output acceleration instruction processing unit 252, as described above, selects a page to read and output the register value set by the presentation engine 250, and outputs a graphic corresponding to the selected page. Read the acceleration instruction data from the third memory. The graphic command decoder 420 included in the output acceleration command processor 252 interprets the read graphic output acceleration command data and executes the selected graphic output acceleration command through the rendering circuit 430. The graphic image output from the rendering circuit 430 is blended with the moving image in the frame buffer memory 260 and stored, and the stored graphic image and the moving image are overlaid and displayed on the screen.

5 is a diagram illustrating a page setup process of a 2D graphics decoder.

A page setup process based on the above description in FIG. 4 is summarized as follows. That is, the presentation engine 250 reads (1) the page status register (PAGE_STATUS_1) and (2) sets the register (PAGE_IP_PTR_1) indicating the graphic instruction of the page in the idle state. (3) Set a page display register (PAGE_DISPLAY) that informs the selected page as an output page. Through the page setup process, the presentation engine 250 is ready to draw two-dimensional graphics. Thereafter, the output acceleration command processor 252 analyzes the graphic output acceleration command data stored in the third memory and draws a two-dimensional graphic.

6 is a diagram illustrating a process of accelerating graphic output through a page setup process.

Referring to FIG. 6, the presentation engine 250 and the output acceleration command processor 252 may alternately output the graphic data to the frame buffer using two page control registers. That is, the presentation engine 250 alternately stores and prepares the graphic output acceleration command data in the page # 1 662 and the page # 2 664 of the third memory 260 in advance for the page in the idle state, and outputs the output. The acceleration command processor 652 may alternately execute the graphic output acceleration command data prepared in the page # 1 662 and the page # 2 664 to improve graphic processing performance. In addition, it is possible to operate a page flipping graphics animation, such a flipping page can be extended to two or more pages (triple flipping page) method.

In particular, in the case of the presentation engine 250 having a lot of considerations and having a complicated logic structure, it is preferable to implement the software through software to support the output of a plurality of curves or polygons. To create and store a combination of flexible graphical output acceleration instructions. On the other hand, the output acceleration command processor 252, which takes a long time for processing, is preferably implemented as a circuit in hardware. By using the third memory as described above, preparing and storing the output acceleration command data of the graphic to be output (polygon generation and scan conversion process described later), and reading the graphic output acceleration command data stored from the third memory in two dimensions. By separating and rendering the graphics (the pixel rendering process described later) independently, it is possible to reduce the bottleneck that occurs when outputting a graphic animation having a plurality of frames.

In addition, the present invention has been described with reference to the case of executing the graphic output acceleration command in units of pages. However, this is only one embodiment, and according to the design method of the 2D graphic decoder 200, the graphic output acceleration instruction in units of objects, such as when the polygon is generated and converted to the graphic output acceleration instruction immediately after execution, is executed. It can be implemented by modifying in various ways, such as by executing.

Hereinafter, a detailed description will be given of a graphic output acceleration command executed by the above-described two-dimensional graphics decoder 200. 7 is a diagram illustrating an example of a structure of a graphic output acceleration command used in a 2D graphic decoder according to the present invention.

Referring to FIG. 7, the graphic output acceleration instruction according to an embodiment of the present invention has a 64-bit instruction structure. Such an instruction is preferably composed of instructions for outputting various polygon data.

Specifically, the graphic acceleration command includes a command identifier (CMD), and as a parameter, the vertical position (Y) of the polygon, the horizontal start position (STX), the horizontal end position (EDX), the drawing and filling data information of the graphic ( FPTR) and the like. The above-described parameters may be modified and used according to the type of command to be executed. A specific example of the graphic output acceleration instruction is described in detail with reference to FIG. 10.

8 is a diagram illustrating an example of two-dimensional vector graphics represented by polygon data.

Referring to FIG. 8, various polygon data are displayed. (a) denotes a triangle and (b) denotes a circle. According to the conventional graphic accelerator, a triangle can be expressed using a moveto, a lineto, a horizontal line command, a vertical line draw command, or the like using a (x, y) coordinate. . In addition, the circle may be displayed using a moveto using a (x, y) coordinate and a curve drawing command indicating an intermediate waypoint. That is, in the related art, graphic output acceleration which classifies graphic data into various basic figures and adds basic figure drawing function functions, such as a move command, a line drawing command, and a horizontal line drawing command, to a graphic output accelerator circuit to rapidly draw a two-dimensional graphic. Treatment method was used.

On the other hand, in the present invention, in order to perform more various drawing process, as shown in FIG. 9, the graphic output acceleration command is generated based on the horizontal drawing command generated after scanning conversion of polygon data in the presentation engine 250 as shown in FIG. Use the way.

FIG. 9 is a diagram illustrating a result of scanning conversion of the 2D vector graphic illustrated in FIG. 8. When the vertical position Y, the horizontal start position STX, the horizontal end position EDX, the horizontal fill data information FPTR, etc. of the plurality of horizontal lines obtained by scan-converting the triangular polygon as shown in FIG. 9 are determined, You can draw the polygon. Depending on the nature of the fill data, you can draw filled polygons. This provides an advantage that a complicated figure can be drawn quickly even with a relatively much simpler instruction than the acceleration method using the conventional basic figure drawing function shown in FIG. 8.

10 is a diagram illustrating an example of a graphic output acceleration command according to the present invention.

Referring to FIG. 10, graphic output acceleration commands (ie, horizontal drawing commands) 324 according to the present invention may include the following. One color pixel drawing command (Plot), one color solid line drawing command (SolildL), tiled bitmap line drawing command (TiledL), clip bitmap line drawing command (ClippedL), linear gradient line drawing The command (LinearGL), the radial gradient line drawing command (RadialGL), and so on.

In addition, the command that repeats the horizontal coordinates of the horizontal drawing command that was executed immediately before as the auxiliary command of the horizontal drawing command, increases and decreases the starting point (STX) and the ending point (EDX) until the horizontal coordinate of Y (Repeat), An AffineTranslate command that sets the affine translation values (M0, M1, M2, M3) or position (TX, TY) in the bitmap image or gradient pattern that is applied to the horizon drawing command, and the color of the drawn horizon. This is the ColorTranslate command for the transformations (C0, C1, C2, C3, C4, C5, C6, C7).

Furthermore, as a command to control the interpretation and execution of the command, a branch instruction (Link) for branching to a designated address location and executing a horizontal drawing instruction, an end instruction (End) for interrupting execution of the instruction, and execution of the instruction for a certain period of time. That is the delayed execution delay instruction (Nop).

In addition, a command (VideoPlace) for designating the position, size, and layer of an output image of AV data, which is a video output control command used to be synthesized with a two-dimensional AV image, and has no background color and video signal except for a video screen area. That's the command (SetColor) that specifies the color of the video screen area when it's in a state.

An embodiment of the relationship between the aforementioned graphic acceleration instruction and its parameters is shown in FIG. 10. That is, Y represents the unfolded vertical position, STX represents the horizontal start position, EDX represents the horizontal end position, and FPTR represents the drawing and filling data indication information of the graphic. In particular, the FPTR is used to indicate the address of a data structure having bitmap data, gradient patterns, color indication information, and various auxiliary data. Thus, the execution of complex instructions can be simplified. The auxiliary data includes the size of the bitmap, the color color table of the bitmap data, the affine conversion value, the color conversion value, and the like.

Of course, the graphic output acceleration command 324 composed of a horizontal line drawing shown in FIG. 10 may be implemented in various forms. For example, instead of using a scan conversion in a horizontal direction to use a horizontal line drawing command as shown in FIG. 9, a scan conversion in a vertical direction may be used to use a command configured to draw a vertical line.

More specifically, FIG. 11A illustrates an example of the graphic output acceleration command and the fill data 324, and FIG. 11B illustrates the graphic image displayed when the graphic output acceleration command and the fill data shown in FIG. 11A are executed. Drawing.

Referring to FIG. 11A, in order to represent a polygon, first, a solid line drawing (SolidL) command described above with reference to FIG. 10 is performed. Draw a solid line corresponding to 101 pixels starting at vertical position 0, from horizontal start position 0 to horizontal end position 100. At this time, the fill data of the 2000H address indicated by the FPTR parameter of the solid line drawing command is applied. That is, it fills 101 pixels with a red color of 100% transparency or transparency. Next, the command repeats the same operation, that is, drawing a solid line, until the vertical position reaches 100. Third, according to the command for drawing a solid line again, a line corresponding to 1 pixel is drawn from the horizontal start position 50 and the horizontal end position 50 with respect to the vertical position 0. At this time, the fill data of the 2004H address indicated by the FPTR parameter is applied, and one pixel is filled with a blue color having 100% transparency. Fourth, the Repeat command repeats the Draw Solid Lines command until it reaches the vertical position of 50. The fifth command repeats the Draw Solid Line command until it reaches a vertical position of 50 to 100. The result of executing all of the instruction set shown in FIG. 11A is shown in FIG. 11B.

12A to 12E are examples of code implementing a horizontal drawing instruction, which is a graphic output acceleration instruction, according to the present invention.

The SolildL () function of FIG. 12A is an explanatory code of a solid line drawing command composed of one color. The TiledL () function of FIG. 12B is a description code of a tiled bitmap line drawing command, and the ClippedL () function of FIG. 12C is a description code of a clip bitmap line drawing command. In addition, the LinearGL () function of FIG. 12D is an explanatory code of a linear gradient line drawing command, and the RadialGL () function of FIG. 12E is an explanatory code of a radial gradient line drawing command.

13A to 13C illustrate an example of fill data according to the present invention. FIG. 13A is an example of a solid fill, and FIG. 13B is an example of a gradient fill whose color changes gradually, and FIG. 13C is an example of a bitmap fill and a clip fill that repeatedly fill a screen with the same image.

FIG. 14 illustrates an application example of two-dimensional graphics and AV data decoded according to an exemplary embodiment of the present invention, blended and displayed on one screen.

Referring to FIG. 14, a moving picture 1401 in which AV data compressed and encoded by MPEG is decoded and output, and a graphic image 1402 output by the 2D graphic decoder 200 based on a graphic acceleration command are blended. It is displayed on the screen. As such, an image reproducing apparatus such as a DVD or a DTV according to the present invention may provide interactive contents displaying two-dimensional graphic images associated with a moving image together. In particular, two-dimensional graphics can be provided that include high speed animation. In addition, the functions of the presentation engine 250 and the output acceleration command processor 252 may be separated from each other by using the graphic output acceleration command stored in the third memory. Accordingly, the burden on the CPU required for the rendering process during graphic output can be reduced, and the graphic output performance is improved.

As an external channel for storing video data such as AV data or graphic data according to the present invention, a removable storage medium such as an optical disk or a memory card and a storage medium built in a video reproducing apparatus such as a hard disk drive are easily removable. Storage media are included. In the case of an optical disc, a CD-ROM, a DVD, a Bluray-Disc, etc. may be included, and an optical disc developed afterwards may be included. Also included is a network medium that provides content over a network, such as the Internet.

In addition, the image reproducing apparatus of the present invention may be implemented as a single integrated circuit, or each functional block may be implemented by being divided into a plurality of systems and a distributed system connected by a network.

The invention can also be embodied as computer readable code on a computer readable recording medium. Computer-readable recording media include all kinds of recording devices that store data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical disk, and the like, and may also include those implemented in the form of carrier waves (eg, transmission over the Internet). do. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The above description is only one embodiment of the present invention, and those skilled in the art may implement the present invention in a modified form without departing from the essential characteristics of the present invention. Therefore, the scope of the present invention should not be limited to the above-described examples, but should be construed to include various embodiments within the scope equivalent to those described in the claims.

As described above, according to the present invention, a command-based two-dimensional graphic decoder or an image reproducing apparatus including the same accelerates the output of a two-dimensional graphic image by using a graphic output acceleration command using a horizontal line drawing, thereby improving the output frame rate. Two-dimensional graphic images may be provided, and interactive content may be provided by blending the decoded video together. In particular, a hardware circuit implementation method of a 2D graphics output accelerator by decoding 2D graphics data based on a graphic output acceleration command composed of a horizontal line drawing having a relatively simple structure, compared to a graphic accelerator using a conventional basic drawing function. This simplification, lower design cost, and reduced hardware circuit size offer a price / performance ratio.

Furthermore, even a video reproducing apparatus with a low speed CPU can provide a two-dimensional graphic animation including fast output and various curve representations as supported by a computer.

1A to 1C are reference drawings illustrating a conventional graphic output acceleration technique;

2 is a block diagram of an image reproducing apparatus having a two-dimensional graphics decoder including a command-based graphics output acceleration function according to a preferred embodiment of the present invention;

3 is a view illustrating an image playback process using a command-based graphic output acceleration function according to a preferred embodiment of the present invention;

4 is a view for explaining in detail the structure of the two-dimensional graphics output acceleration command processor shown in FIG.

5 is a diagram illustrating a page setup process of a 2D graphics decoder;

6 is a diagram illustrating a process of accelerating graphic output through a page setup process;

7 is a diagram illustrating an example of a structure of a graphics output acceleration instruction used in a two-dimensional graphics decoder according to the present invention;

8 is a view showing an example of two-dimensional vector graphics represented by polygon data;

FIG. 9 is a diagram illustrating a result of scanning conversion of the 2D vector graphic illustrated in FIG. 8;

10 is a diagram showing an example of a graphic output acceleration instruction according to the present invention;

11A is a diagram illustrating an example of a graphic output acceleration command and fill data;

FIG. 11B is a diagram illustrating a graphic image displayed when the graphic output acceleration command and fill data shown in FIG. 11A are executed; FIG.

12A to 12E are examples of codes implementing a horizontal drawing instruction, which is a graphic output acceleration instruction according to the present invention;

13A to 13C illustrate an example of fill data according to the present invention;

FIG. 14 illustrates an application example of two-dimensional graphics and AV data decoded according to an exemplary embodiment of the present invention, blended and displayed on one screen.

Claims (24)

In the method of accelerating the graphics output, Interpreting the graphic data and converting the graphic data into at least one accelerated instruction data to be stored; And Outputting a graphic image by executing stored at least one acceleration command data; Wherein each step is performed independently. The method of claim 1, The acceleration command data may include a horizontal drawing command or a vertical drawing command for rapidly drawing the graphic image on the screen, the at least one obtained by analyzing the graphic data to generate a polygon and scan-convert the generated polygon. How to feature. The method of claim 1, The converting and storing may be performed through separate software for interpreting the various graphic data. The method of claim 1, The converting and storing may include storing the converted at least one acceleration command in a predetermined memory area. The method of claim 1, Outputting the graphic image is performed through a separate hardware circuit to increase the output speed of the graphic image. The method of claim 2, And the acceleration instruction data includes instructions for drawing a pixel. The method of claim 2, The acceleration command data includes a command for drawing a horizontal line in one color. The method of claim 9, The acceleration instruction data may include instructions for drawing a horizontal line to which a bitmap image pattern is applied. The method of claim 2, The acceleration instruction data includes instructions for drawing a horizontal line to which a linear gradient image pattern is applied. The method of claim 2, The acceleration command data includes a command for drawing a horizontal line to which a radial gradient image pattern is applied. The method of claim 2, The acceleration instruction data may include instructions for increasing or decreasing a vertical coordinate or a horizontal coordinate of a horizontal drawing instruction that was previously executed, and repeating the previous instruction to a coordinate of a predetermined horizontal line. The method of claim 2, The acceleration command data is fill data applied to a command for drawing a horizontal line, and includes an AffineTranslate command for adjusting the size or position of a bitmap image or a gradient pattern. The method of claim 2, The acceleration instruction data includes a color translate instruction for converting colors of pixels drawn on a horizontal line. The method of claim 2, And the acceleration instruction data includes a branch instruction for branching to the acceleration instruction data position at another address to execute the acceleration instruction at the corresponding address. The method of claim 2, The acceleration command data may include a command for designating an output position and a layer of a moving image which is blended with the graphic image and output. The method of claim 2, The acceleration command data may include a command for designating a color of a background area excluding a moving picture area blended with the graphic image and a color of a moving picture area when there is no video signal. An acceleration command conversion unit to decode the graphic data read through the external channel, convert the graphic data into at least one accelerated command data, and store the converted graphic data in a predetermined memory area; And An acceleration command processor for outputting a graphic image by executing at least one stored acceleration command data, And the acceleration command conversion unit and the acceleration command processing unit operate independently of each other using the predetermined memory area. The method of claim 17, The acceleration command conversion unit may generate a polygon by interpreting the graphic data, convert the graphic data into at least one acceleration command data obtained as a result of scan conversion of the generated polygon, and store the result in the predetermined memory area. The acceleration command data may include a horizontal line drawing command or a vertical line drawing command for quickly drawing the graphic image on the screen. The method of claim 17, The acceleration command conversion unit is a graphics decoder, characterized in that implemented in separate software to interpret the various graphic data. The method of claim 17, The acceleration command processor is a graphics decoder, characterized in that implemented in a separate hardware circuit to increase the output speed of the graphic image. The method of claim 17, And the external channel comprises a removable storage medium that can be easily separated from a playback device, a storage medium built into the playback device, or a network medium. The method of claim 17, And the graphic decoder. The method of claim 22, And outputting a single image by overlaying a graphic image output through the graphic decoder and a video output by decoding and outputting AV data read from the external channel. The method of claim 1, A recording medium having recorded thereon a program for performing on the computer a method of accelerating the graphic output.