JP3735325B2 - Image generator - Google Patents

Description

[0001]
[Industrial application fields]
The present invention is an image suitable for application when high visualization performance is required in a limited hardware resource, such as a video game machine or a graphic computer. In particular, the present invention relates to a so-called translucent process.
[0002]
[Prior art]
In computer graphics, what is usually called a 3D (three-dimensional = three-dimensional) graphics system first draws a plurality of surfaces of an object when drawing a realistic object (the object to be drawn is called an object). By dividing each polygon into the frame memory (hereinafter referred to as the frame buffer) corresponding to the monitor display screen. Reconstruct an image that looks stereoscopic.
[0003]
In this type of ordinary image generating apparatus, a dedicated drawing device is provided between the CPU and the frame buffer in order to perform processing at high speed. When generating an image, the CPU does not directly access the frame buffer, but generates a command for drawing a basic figure (polygon) such as a triangle or a quadrangle (hereinafter abbreviated as a drawing command) to generate a drawing device. Send to. The drawing apparatus interprets the sent drawing command and draws a figure in the frame buffer.
[0004]
By the way, in computer graphics, pixel data of a previously displayed image (for example, composed of three primary color data; the same applies hereinafter) and pixel data of an image to be rendered next are mixed at a predetermined ratio. Therefore, semi-transparent processing is performed. This translucent process is performed by a drawing apparatus. Conventionally, the translucent processing unit of the drawing apparatus is configured as shown in FIG.
[0005]
In FIG. 11, reference numeral 10 denotes a frame buffer, and 20 denotes a drawing apparatus.
The drawing device 20 has been transferred to the drawing device 20, a mixing circuit 21 for translucent processing, a read circuit 22 that reads pixel data from the frame buffer 10, a write circuit 23 that writes pixel data to the frame buffer 10, and the drawing device 20. A drawing command decoding unit 24 that decodes a drawing command, an image generation circuit 25 that generates a drawing image according to the drawing command decoded by the drawing command decoding unit 24, a mixing ratio memory 26, and the entire translucent process. And a control unit 27.
[0006]
In this case, the drawing command includes data of the mixing ratio, and the drawing command decoding unit 24 extracts the data of the mixing ratio and stores it in the mixing ratio memory 26. The mixing ratio memory 26 stores the mixing ratio for each pixel (pixel) constituting the drawing image generated by the image generation unit 25 based on the drawing pixel position information from the image generation unit 25.
[0007]
The translucent process is performed as follows. That is, the pixel data Vm before the pixel position to be drawn is read from the frame buffer 10 by the reading circuit 22 and supplied to the mixing circuit 21. Further, the pixel data Vc to be drawn from now is supplied from the image generation unit 25 to the mixing circuit 21. Then, the mixture ratio α for the pixel to be drawn is read from the mixture ratio memory 26 and supplied to the mixing circuit 21.
[0008]
In the mixing circuit 21, the pixel data Vm and the pixel data Vc are mixed at the mixing ratio α. That is, the calculation of (1−α) Vm + αVc = Vo is performed to obtain mixed output pixel data Vo. Then, the pixel data Vo obtained as a result of the mixing is written back to the same address position as the read pixel data Vm in the frame buffer 10 by the writing circuit 23.
[0009]
In this case, the color of the previous pixel remains in the new pixel in accordance with the mixing ratio α, and is displayed as a translucent color. If the mixing ratio α = 1, it is completely opaque, and if the mixing ratio α = 0, it is completely transparent.
[0010]
[Problems to be solved by the invention]
As described above, in the conventional translucent processing, the value of the mixing ratio α is included in the drawing command and is stored in the mixing ratio memory 26 for each pixel based on the drawing command. For this reason, if the mixing ratio is to be set finely, the number of bits of the mixing ratio α increases, the amount of data of the drawing command increases, and the mixing ratio memory 26 must have a large capacity.
[0011]
In order to simplify the configuration of the drawing apparatus, it is better to be able to perform completely transparent processing and completely opaque processing using semi-transparent processing. However, as described above, in the case of semi-transparent processing, For each pixel, three steps of reading from the frame buffer 10, mixing processing, and writing back processing to the frame buffer 10 are required, which has a disadvantage that the processing time is relatively long.
[0012]
A first object of the present invention is to provide an image generation apparatus in which the data amount of a drawing command does not increase and a mixture ratio memory having a small capacity can be used.
[0013]
A second object of the present invention is to provide an image generation apparatus capable of performing a complete transparency process and a complete opaque process at high speed using a translucent process.
[0014]
[Means for Solving the Problems]
In order to solve the above-described problem, the image generation apparatus according to the first aspect of the present invention corresponds to the reference numerals in the embodiment of FIG.
In the device that transfers the drawing command generated by the CPU 42 to the drawing device unit 61 and sequentially executes drawing according to the drawing command in the drawing device unit 61 to generate an image on the frame buffer 63.
The drawing device unit 61
Means 102 for reading out the pixel data of the previously drawn image from the frame buffer 63;
A mixing circuit 101 that mixes pixel data read from the frame buffer 63 and pixel data at a corresponding position to be drawn next at a specified mixing ratio;
Writing means 103 for writing the pixel data of the mixing result of the mixing circuit 101 to the corresponding pixel position of the frame buffer 63;
A mixing ratio storage unit 106 for storing a plurality of the mixing ratios;
Selection means 107 for selecting a mixing ratio to be supplied to the mixing circuit 101 from the mixing ratio storage unit 106 in accordance with the mixing ratio selection information included in the drawing command;
It is characterized by providing.
[0015]
Further, the image generation apparatus according to the invention of claim 2 corresponds to the reference numerals of the embodiment of FIG.
In the device that transfers the drawing command generated by the CPU 42 to the drawing device unit 61 and sequentially executes drawing in accordance with the drawing command to generate an image on the frame buffer 63.
The drawing device unit 61
Reading means 102 for reading pixel data of an image previously drawn from the frame buffer 63;
A mixing circuit 101 that mixes pixel data read from the frame buffer 63 and pixel data at a corresponding position to be drawn next at a specified mixing ratio;
Writing means 103 for writing the pixel data of the mixing result of the mixing circuit 101 to the corresponding pixel position of the frame buffer 63;
A mixing ratio storage unit 106 that stores the mixing ratio supplied to the mixing circuit 101;
A flag determination means 109 for extracting a flag relating to the mixing process included in the drawing command and determining the state of the flag;
From the determination result of the flag determining means 109, when the flag is in the state of 1, the reading of the pixel data from the frame buffer 63 by the reading means 102 is omitted and the pixel data at the corresponding position to be drawn next is omitted. The writing means 103 controls the writing to the corresponding pixel position of the frame buffer 63, and when the flag is in another state, the reading means 102 reads the pixel data from the frame buffer 63 and the writing means 103 uses the frame buffer. And a control means 18 for controlling the writing to 63 to be omitted.
[0016]
[Action]
In the first aspect of the invention having the above-described configuration, the mixing ratio storage unit 106 of the drawing device unit 61 stores information on the mixing ratio in advance. The drawing command includes selection information indicating which one of the mixing ratios stored in the mixing ratio storage unit 106 is used, and the mixing ratio to be supplied to the mixing circuit 101 is determined based on the selection information. Therefore, this selection information may be prepared for each pixel unit. Since this selection information may be the number of bits that can be selected for the number of mixing ratios stored in the mixing ratio storage unit 106, the number of bits may be smaller than in the conventional case where the mixing ratio must be maintained as it is, The data amount of the drawing command can be reduced, and the memory capacity necessary for selecting the mixing ratio can be reduced.
[0017]
Further, in the invention of claim 2, in the case where the discriminating means 109 performs a completely transparent process (mixing ratio = 0) and a completely opaque process (mixing ratio = 1) according to a 1-bit flag included in the drawing command. Is determined.
[0018]
In the case of complete transparency processing, the readout circuit 102 does not read out pixel data from the frame buffer 63, and the writing circuit 103 does not write back to the frame buffer 63. For this reason, even when a translucent processing apparatus including the mixing circuit 101, the reading circuit 102, and the writing circuit 103 is used, the complete transparent processing is performed at a high speed by the amount that the reading process and the writing process are omitted. Can be done.
[0019]
In the case of complete opacity processing, pixel data is not read from the frame buffer 63 by the read circuit 102, and only new pixel data is written to the frame buffer by the write circuit 103. Accordingly, in this case as well, high-speed processing is performed by the amount that the pixel data reading processing from the frame buffer 63 is omitted.
[0020]
【Example】
An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a configuration example of an image generation apparatus according to an embodiment of the present invention. This example is an embodiment of a game machine having a 3D graphic function and a moving image reproduction function.
[0021]
In FIG. 2, reference numeral 41 denotes a system bus (main bus). A CPU 42, a main memory 43, and a sorting controller 45 are connected to the system bus 41.
[0022]
In addition, an image decompression unit 51 is connected to the system bus 41 via an input FIFO (First In First Out) buffer memory (hereinafter, FIFO buffer memory is abbreviated as a FIFO buffer) 54 and an output FIFO buffer 55. Connected. Further, the CD-ROM decoder 52 is connected to the system bus 41 via the FIFO buffer 56, and the drawing unit 61 is connected to the system bus 41 via the FIFO buffer 62.
[0023]
Reference numeral 71 denotes a control pad as operation input means, which is connected to the system bus 41 via an interface 72. Further, the system bus 41 is connected to a boot ROM 73 that stores a program for starting up the game machine.
[0024]
The CD-ROM decoder 52 is connected to a CD-ROM driver 53 and decodes application programs (for example, game programs) and data recorded on a CD-ROM disc mounted on the CD-ROM driver 53. The CD-ROM disc stores, for example, image data of moving images and still images compressed by discrete cosine transform (DCT), and image data of texture images for modifying polygons. The application program on the CD-ROM disc includes a polygon drawing command. The FIFO buffer 56 has a capacity for one sector of the recording data of the CD-ROM disc.
[0025]
The CPU 42 manages the entire system. In addition, the CPU 42 performs a part of processing when an object is drawn as a collection of many polygons. That is, the CPU 42 generates a drawing command and generates a control command on the main memory 43 as will be described later. Then, as will be described later, a drawing command example that is a mixture of these drawing commands and control commands is created on the main memory 43.
[0026]
Further, the CPU 42 has a cache memory 46, and a part of the CPU instructions can be executed without fetching from the system bus 41. Further, the CPU 42 is provided with a coordinate calculation device unit 44 as a CPU internal coprocessor for performing coordinate conversion calculation for polygons and calculation of coordinate values for control when creating drawing commands and control commands. Yes. The coordinate arithmetic unit 44 performs three-dimensional coordinate conversion and three-dimensional to two-dimensional conversion on the display screen.
[0027]
As described above, since the CPU 42 has the instruction cache 46 and the coordinate arithmetic unit 44 inside, the processing can be performed to some extent without using the system bus 41, so the system bus 41 is released. It's easy to do.
[0028]
The image decompression unit 51 performs decompression processing of compressed image data reproduced from a CD-ROM disc, and includes hardware of a Huffman code decoder, an inverse quantization circuit, and an inverse discrete cosine transform circuit. The CPU 42 may process the Huffman code decoder as software.
[0029]
In the case of this example, the image expansion device unit 51 divides one image (one frame) into small regions (hereinafter referred to as macroblocks) of about 16 × 16 pixels (pixels), for example. Performs image decompression decoding in block units. Data transfer is performed with the main memory 43 in units of macroblocks. Therefore, the FIFO buffers 54 and 55 have a capacity corresponding to a macro block.
[0030]
A frame memory 63 is connected to the drawing device unit 61 via the local bus 11. The drawing device unit 61 executes a drawing command transferred from the main memory 43 via the FIFO buffer 62 and writes the result into the frame memory 63. The FIFO buffer 62 has a memory capacity for one instruction.
[0031]
The frame memory 63 includes an image memory area for storing a drawing image, a texture memory area for storing a texture image, and a table memory area for storing a color lookup table (color conversion table CLUT).
[0032]
FIG. 3 shows the memory space of the frame memory 63. The frame memory 63 is addressed with two-dimensional addresses of columns and rows. Of this two-dimensional address space, the area AT is a texture memory area. A plurality of types of texture patterns can be arranged in the texture area AT. AC is a table memory area of the color conversion table CLUT.
[0033]
As will be described later, the data of the color conversion table CLUT is transferred from the CD-ROM disk to the frame memory 63 by the sorting controller 45 through the CD-ROM decoder 52. The texture image data of the CD-ROM is decompressed by the image decompressing unit 51 and transferred to the frame memory 63 via the main memory 43.
[0034]
In FIG. 3, AD is an image memory area, and includes a frame buffer area for two areas, a drawing area and a display area. In this example, a frame buffer area currently used for display is referred to as a display buffer, and a frame buffer area where drawing is performed is referred to as a drawing buffer. In this case, while drawing is performed using one as a drawing buffer, the other is used as a display buffer. When drawing is completed, the two buffers are switched to each other. Switching between the drawing buffer and the display buffer is performed in synchronization with vertical synchronization when drawing is completed.
[0035]
The image data read from the display buffer of the frame memory 63 is output to the image monitor device 65 via the D / A converter 64 and displayed on the screen.
[0036]
The sorting controller 45 has the same function as a so-called DMA controller, transfers image data between the main memory 43 and the image decompression unit 51, and sends a drawing command sequence from the main memory 43 to the drawing unit 61. The transfer means constitutes the transfer means. The sorting controller 45 performs the above-described transfer process without the intervention of the CPU 42 through a gap where other devices such as the CPU 42 and the control pad 71 open the system bus 41. In this case, the CPU 42 can notify the sorting controller 45 of the opening of the system bus 41, or the sorting controller 45 can forcibly request the CPU 42 to release the bus.
[0037]
The main memory 43 includes a memory area for compressed image data and a memory area for decompressed image data subjected to decompression decoding processing for moving image and still image data. The main memory 43 includes a memory area for graphics data such as a drawing command sequence (hereinafter referred to as a packet buffer).
[0038]
This packet buffer is used for setting the drawing command sequence by the CPU 42 and transferring the drawing command sequence to the drawing device unit, and is shared by the CPU 42 and the drawing device unit 61. In this example, a packet buffer for setting a drawing command sequence (hereinafter referred to as a setting packet buffer) and a packet buffer for transfer are used so that the CPU 42 and the drawing device unit 61 operate in parallel. (Hereinafter referred to as an execution packet buffer), and when one is a setting packet buffer, the other is used as an execution packet buffer. The functions of two packet buffers are exchanged.
[0039]
When the apparatus (game machine) in the example of FIG. 2 is turned on and a CD-ROM disc is loaded, the CPU 42 executes a program for performing a so-called initialization process for executing the game in the boot ROM 73. . Then, the recording data of the CD-ROM disc is captured. At this time, each user data is decoded based on the identification information ID in the user data of each sector of the CD-ROM disc, and the data is checked. Based on the check result, the CPU 42 executes a process according to the reproduction data having the contents indicated by each ID.
[0040]
That is, compressed image data, a drawing command, and a program executed by the CPU 42 are read from the CD-ROM disk via the CD-ROM driver 53 and the CD-ROM decoder 52 and loaded into the main memory 43 by the sorting controller 45. The Of the loaded data, the information of the color conversion table is transferred to the area CLUT of the frame memory 63.
[0041]
[Decompression and transfer of compressed image data]
Of the input data to the main memory 43, the compressed image data is written again into the main memory 43 by the CPU 42 after the CPU 42 decodes the Huffman code. Then, the sorting controller 45 transfers the image data after the decoding process of the Huffman code from the main memory 43 to the image expansion device unit 51 via the FIFO buffer 54.
[0042]
The expanded image data is transferred to the main memory 43 by the sorting controller 45 via the FIFO buffer 55. In this case, as described above, the image expansion device unit 51 performs image data expansion processing in units of macroblocks. Therefore, the compressed data in units of macro blocks is transferred from the main memory 43 to the input FIFO buffer 54 by the sorting controller 45. When the decompression decoding process for one macroblock is completed, the image decompressing unit 51 puts the resulting decompressed image data into the output FIFO buffer 55 and also receives the compressed data of the next macroblock from the input FIFO buffer 54. Take out and perform decompression decoding.
[0043]
The sorting controller 45 transfers the decompressed image data of one macro block to the main memory 43 unless the system bus 41 is opened and the output FIFO buffer 55 of the image decompressing device 51 is empty. One macroblock of compressed image data is transferred from the main memory 43 to the input FIFO buffer 54 of the image decompression unit 51.
[0044]
The CPU 42 transfers the decompressed data to the frame memory 63 via the drawing device unit 61 when a certain amount of macroblocks of the decompressed image data is accumulated in the main memory 43. At this time, if the decompressed image data is transferred to the image memory area AD of the frame memory 63, it is displayed on the image monitor device 65 as a background moving image as it is. Further, it may be transferred to the texture memory area AT of the frame memory 63. The image data in the texture memory area AT is used for modifying the polygon as a texture image.
[0045]
[Processing and transfer of drawing instruction sequence]
Polygons that make up the surface of an object are displayed in a three-dimensional manner on a two-dimensional image display surface by drawing in order from polygons that are deep in the depth direction according to Z data that is three-dimensional depth information. Can do. The CPU 42 creates, on the main memory 43, a sequence of drawing commands for causing the drawing device unit 61 to perform drawing in order from the polygons at deep positions in the depth direction.
[0046]
FIG. 4A shows an outline of an example of the data structure of the instruction IP in this example. That is, this data structure includes a header part and an instruction data part.
[0047]
The header part includes a tag TG and a command identification code CODE. In the tag TG, an address on the main memory 43 in which the next drawing command or control command is stored is written. The command identification code CODE includes identification data IDP indicating what kind of instruction the instruction is, and includes other information necessary for the instruction as necessary. Coordinate values and other parameters are written in the command data portion PD. The parameter of the command data part PD is determined for each command IP.
[0048]
The tag TG plays the following role. In computer graphics, since a three-dimensional image is drawn on a two-dimensional screen, it is necessary to draw in order from the deepest. For this purpose, it is necessary to sequentially transfer drawing commands according to the drawing order from the main memory 43 to the drawing device unit 61.
[0049]
When the DMA transfer from the main memory 43 to the drawing device unit 61 is performed by the conventional DMA controller, a process for rearranging the drawing commands on the main memory 43 in the execution order, that is, a process for changing the storage address position of the drawing commands must be performed. I must. However, it takes time for the rearrangement process, and real-time processing becomes difficult.
[0050]
Therefore, in this example, the tag TG as described above is provided in the drawing command, and the tag TG is rewritten so that the CPU 42 is in the order of the drawing command. The sorting control 45 traces the tag TG and transfers a drawing command to the drawing device unit 61. The CPU 42 can perform processing for determining the display priority of polygon drawing on the main memory 43 without changing the address position of the drawing command itself on the main memory 43.
[0051]
FIG. 4B shows an example of a polygon drawing command. This polygon drawing command is a triangular polygon drawing command, and in this case, the identification data IDP of the command identification code CODE has the contents indicating it. In addition, when mapping the polygon with one color, the color data (R, G, B) of the three primary colors to be mapped are included as other necessary information of the code CODE. Then, the coordinates of the three vertices (X0, Y0), (X1, Y1), (X2, Y2) are described as parameters of the instruction data. Further, the parameter includes index data INDX for translucent processing, as will be described in detail later.
[0052]
The CPU 42 calculates the movement of the object and the viewpoint based on the user's operation input from the control pad 71 and creates a drawing command on the main memory 43. Next, the drawing command tag TG is rewritten in the drawing order with the Z data, and a drawing command sequence is generated on the main memory 43. At this time, only the tag is rewritten without changing the address of each instruction on the main memory 43.
[0053]
When this drawing command sequence is completed, the sorting controller 45 sequentially follows each drawing command IP1, IP2, IP3,..., IPn according to the tags TG1, TG2, TG3,. Each instruction is transferred from the main memory 43 to the drawing device unit 61. Therefore, the FIFO buffer 62 only needs to have a capacity for one instruction.
[0054]
In the drawing device unit 61, since the transmitted data is already sorted, the commands IP1, IP2, IP3,..., IPn are sequentially executed and the result is stored in the drawing area AD of the frame memory 63. .
[0055]
At the time of polygon drawing, the data is sent to the gradient calculation unit of the drawing device unit 61 to perform gradient calculation. The gradient calculation is a calculation for obtaining the inclination of the plane of the mapping data when the inside of the polygon is filled with the mapping data in polygon drawing. In the case of texture, the polygon is filled with texture image data, and in the case of Gouraud shading, the polygon is filled with luminance values.
[0056]
When a texture is pasted on a polygon constituting the surface of an object, the texture data in the texture area AT is two-dimensionally mapped. For example, texture patterns T1, T2, and T3 as shown in FIG. 6A are converted into coordinates on a two-dimensional screen so as to match the polygons on each surface of the object as shown in FIG. 6B. The texture patterns T1, T2, T3 thus mapped are pasted on the surface of the object OB1, as shown in FIG. 6C. This is arranged in the image memory area AD and displayed on the display screen of the image display monitor 65.
[0057]
In the case of a still image texture, the texture pattern on the main memory 43 is transferred to the texture area AT on the frame memory 63 via the drawing device unit 61. The drawing device unit 61 pastes this on the polygon. Thereby, a texture of a still image is realized on the object. This still image texture pattern data can be recorded on a CD-ROM disc.
[0058]
Furthermore, moving image textures are possible. That is, in the case of moving image texture, as described above, the compressed moving image data from the CD-ROM disk is once read into the main memory 43. Then, this compressed image data is sent to the image expansion device unit 51. Image data is decompressed by the image decompression device 51.
[0059]
The expanded moving image data is sent to the texture area AT on the frame memory 63. Since the texture area AT is provided in the frame memory 63, the texture pattern itself can be rewritten for each frame. As described above, when a moving image is sent to the texture area AT, the texture is dynamically rewritten and changed every frame. If the texture mapping to the polygon is performed by the moving image in the texture area, the moving image texture is realized.
[0060]
As described above, if the image data expanded by the image expansion device unit 51 is sent to the image memory area AD on the frame memory 63, a moving image of the background image can be displayed on the screen of the image monitor device 65, It is also possible to fill the image memory area AD with only the drawing image generated by the drawing command created by the CPU 42 and draw it on the screen of the image display monitor 65. It is also possible to draw an object by polygon drawing by the CPU 42 on a still image obtained by decompressing image data from a CD-ROM disc on the image memory area AD.
[0061]
[Description of First Example of Translucent Processing]
FIG. 1 is a block diagram showing a first embodiment of a translucent processing circuit portion in the drawing device section 61. As shown in FIG.
[0062]
That is, for the translucent processing, the drawing device unit 61 includes a mixing circuit 101, a reading circuit 102 that reads pixel data from the frame buffer 63, a writing circuit 103 that writes pixel data to the frame buffer 63, and the drawing device unit 61. A drawing command decoding unit 104 that decodes the drawing command transferred to the image generation unit, an image generation circuit 105 that generates a drawing image according to the drawing command decoded by the drawing command decoding unit 104, a mixing ratio table memory 106, and a mixing ratio An index memory 107 for storing index data for designating which mixing ratio to select from the table memory 106 to supply to the mixing circuit 101, and a control unit 108 for controlling the entire translucent process are provided.
[0063]
In the mixing ratio table memory 106, for example, a mixing ratio β as shown in FIG. 7 is stored in advance. The mixing ratio β prepared here is a mixing ratio often used for translucent processing. This mixing ratio table may be set in the memory 106 from the beginning in advance, but may be transferred from a CD-ROM disk.
[0064]
The index data included in the drawing command shown in FIG. 3B is selection information for selecting each mixing ratio in the mixing ratio table. That is, the index data in the drawing command corresponds to the index number of the mixing ratio table in FIG. 7 (corresponding to the address of the memory 106), and by this, the mixing ratio of the index number is selected and read from the memory 106. be able to.
[0065]
The index data in the drawing command is extracted by the drawing command decoding unit 104, supplied to the index memory 107, and stored. In this case, the index memory 107 stores index data for each pixel (pixel) constituting the drawing image generated by the image generation unit 105 based on the drawing pixel position information from the image generation unit 105.
[0066]
In this case, the translucent process is performed as follows. That is, the pixel data Va at the pixel position to be drawn is read from the frame buffer 63 by the reading circuit 102 and supplied to the mixing circuit 101. Further, the pixel data Vb to be drawn from now is supplied from the image generation unit 105 to the mixing circuit 101.
[0067]
On the other hand, the index data for the pixel to be drawn is read from the index memory 107, and the mixing ratio β is selected from the mixing ratio table memory 106 based on the read index data and read.
[0068]
This mixing ratio β is supplied to the mixing circuit 101. In the mixing circuit 101, the pixel data Va and the pixel data Vb are mixed at the mixing ratio β. That is, the calculation of (1−β) Va + βVb = Ve is performed to obtain mixed output image data Ve. Then, the pixel data Ve obtained as a result of the mixing is written back to the same address position as the read pixel data Va in the frame buffer 63 by the writing circuit 103.
[0069]
In this case, the color of the previous pixel remains in the new pixel according to the mixing ratio β, and is displayed as a translucent color. If the mixing ratio β = 1, it is completely opaque, and if the mixing ratio β = 0, it is completely transparent.
[0070]
[Description of Second Example of Translucent Processing]
FIG. 8 is a block diagram showing a second embodiment of the translucent processing circuit portion in the drawing device section 61. In FIG. In the case of this example, the drawing command data includes a flag for complete transparency processing or complete opaque processing.
[0071]
FIG. 9 shows an example of a drawing command in this example. That is, the drawing command in this example has the flag F as 1-bit data in the portion of the command identification code CODE. The parameter of the instruction data includes the index data INDX as in the first embodiment.
[0072]
In this example, the mixing ratio table does not have mixing ratios β = 0 and β = 1 as shown in FIG.
[0073]
As shown in FIG. 8, the configuration of the drawing device unit 61 for translucent processing is provided with a flag determination circuit 109 in addition to the circuit blocks in the example of FIG. Then, the drawing command decoding unit 104 extracts a flag F from the drawing command and supplies it to the flag determination circuit 109. The flag discriminating circuit 109 has a flag F Indicates fully opaque processing Sometimes, it is recognized as a completely opaque process, and the determination result is supplied to the control unit 108. Flag F Indicates fully transparent processing In some cases, it is recognized as a completely transparent process, and the determination result is supplied to the control unit 108. The flag F from the drawing command decoding unit 104 is always supplied to the flag determination circuit 109 while an image is generated according to the drawing command.
[0074]
Based on the determination output of the flag F, the control unit 108 does not cause the readout circuit 102 to read out the pixel data from the frame buffer 63 when the process is completely opaque. Then, the control unit 108 controls to supply the pixel data from the image generation circuit 105 to the frame buffer 63 as it is through the mixing circuit 101, and writes the writing circuit 103 to the pixel position where the pixel data is to be drawn. To control. As a result, the pixel becomes only new pixel data, and the previous pixel is completely hidden by the new pixel.
[0075]
Further, the control unit 108 does not perform the pixel data reading process from the frame buffer 63 by the reading circuit 102 and the writing process by the writing circuit 103 when the completely transparent process is performed based on the determination output of the flag F. As a result, the previous pixel data remains as it is at the pixel position to be drawn, and is displayed in a completely transparent state.
[0076]
The example of FIG. 8 is an embodiment that combines the invention for reading the mixing ratio from the mixing ratio table based on the index data and the invention for high-speed processing. Such a mixing ratio α may be provided for each drawing command, and a translucent process using a memory for storing the mixing ratio α may be used.
[0077]
In the above example, image data and application programs are recorded on the CD-ROM disc. However, as the recording medium, other recording media such as a magnetic disk and a semiconductor memory such as a memory card can be used. .
[0078]
【The invention's effect】
As described above, according to the first invention, the drawing command does not need to have the mixing ratio itself for the translucent processing, and selects a desired mixing ratio in the mixing ratio table provided in the drawing apparatus unit. Since it is sufficient to have index data to do this, a small number of bits is sufficient. In addition, the drawing apparatus unit only needs to include a memory for storing the mixture ratio table and a memory for storing the index data, so that a memory with a small memory capacity can be used.
[0079]
According to the second invention, even when a semi-transparent processing circuit is used, in the case of complete opaque processing, reading of pixel data from the frame buffer can be omitted, and complete transparency is achieved. In the case of processing, reading of pixel data from the frame buffer and writing back of pixel data to the frame buffer can be omitted, so that high-speed processing is possible.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a main part of an image generating apparatus according to the present invention.
FIG. 2 is a block diagram of an overall configuration of an embodiment of an image generating apparatus according to the present invention.
FIG. 3 is a diagram for explaining a frame memory area in one embodiment of the present invention;
FIG. 4 is a diagram showing an example of the data structure of an instruction in one embodiment of the present invention.
FIG. 5 is a diagram showing a transfer example of a drawing command in one embodiment of the present invention.
FIG. 6 is a diagram for explaining texture mapping;
FIG. 7 is a diagram showing an example of a mixing ratio table in the first embodiment of the present invention.
FIG. 8 is a block diagram of an essential part of a second embodiment of the present invention.
FIG. 9 is a diagram showing an example of a drawing command in the case of the second embodiment of the present invention.
FIG. 10 is a diagram showing an example of a mixing ratio table in the case of the second embodiment of the present invention.
FIG. 11 is a block diagram for explaining a conventional translucent processing circuit.
[Explanation of symbols]
41 System bus
42 CPU
43 Main memory
44 Coordinate operation unit
45 Sorting controller
46 Cache memory
51 Image decompression unit
52 CD-ROM decoder
53 CD-ROM driver
54, 55 FIFO buffer
61 Drawing unit
62 FIFO buffer
63 frame memory
65 Image display monitor device
71 Control pad
AD image memory area
AT texture area
101 Mixing circuit
102 Read circuit
103 Writing circuit
104 Drawing command decode unit
105 Image generation circuit
106 Mixing ratio table memory
107 Index memory
108 Control unit
109 Flag discrimination circuit

Claims (3)

In a device for transferring a drawing command generated by a CPU to a drawing device unit, and sequentially executing drawing according to the drawing command in the drawing device unit to generate an image on a frame buffer.
The drawing device section
Means for reading pixel data of an image previously drawn from the frame buffer;
A mixing circuit that mixes pixel data read from the frame buffer and pixel data at a corresponding position to be drawn next at a specified mixing ratio;
Writing means for writing pixel data of the mixing result of the mixing circuit into a corresponding pixel position of the frame buffer;
Identification information discriminating means for extracting the identification information contained in the drawing command and discriminating the state of the identification information;
When the identification information indicates complete opacity processing from the determination result of the identification information determination unit, reading of the pixel data from the frame buffer by the reading unit is omitted and the corresponding position to be drawn next is omitted. And an image generation apparatus comprising: control means for controlling the pixel data to be written as it is into the corresponding pixel position of the frame buffer by the writing means. The control means includes
From the determination result of the identification information determination means, when the identification information indicates complete transparency processing, reading of pixel data from the frame buffer by the reading means and writing to the frame buffer by the writing means are omitted. The image generation apparatus according to claim 1 to be controlled. It further comprises an operation input means,
The image generation apparatus according to claim 1, wherein the CPU generates the drawing command and sets identification information in the drawing command in accordance with an operation input received by an operation input unit.

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