KR20050040054A - Programming method of a nonvolatile memory device including an oxide layer as a charge storage layer - Google Patents

Abstract

A program method of a nonvolatile memory device having an oxide film as a charge storage layer is provided. The nonvolatile memory device may include a semiconductor substrate, a source / drain formed in the semiconductor substrate with a channel region interposed therebetween, a gate electrode covering the channel region, and an oxide charge storage layer interposed between the semiconductor substrate and the gate electrode. Can be. The nonvolatile memory device may further include at least one pocket ion implantation region formed in the semiconductor substrate between the channel region and the source / drain. The program method of the nonvolatile memory device may include applying stress to the oxide charge storage layer and injecting charge into the stressed oxide charge storage layer.

Description

Programming method of a nonvolatile memory device having an oxide film as a charge storage layer {programming method of a nonvolatile memory device including an oxide layer as a charge storage layer}

The present invention relates to a nonvolatile memory device, and more particularly, to a method of programming a nonvolatile memory device having an oxide film as a charge storage layer.

Unlike a volatile memory device, a nonvolatile memory device retains previous data even when power is not supplied. Volatile memory devices, such as dynamic random access memory (DRAM), require a refresh operation for data retention, which consumes a lot of power. In contrast, nonvolatile memory devices such as flash memory / electric erasable programmable read only memory (EEPROM) are large-capacity low power consumption devices, and are mainly used in file systems, memory cards, portable devices, and the like.

Generally, nonvolatile memory devices have a charge storage layer between a semiconductor substrate and a gate electrode. According to the material of the charge storage layer, the nonvolatile memory device is classified into a floating gate memory device and an MNOS memory device. In addition, depending on the structure, the nonvolatile memory device may be classified into a stack gate type, a notched gate type, and a nano-dot type.

The floating gate-based nonvolatile memory device has a structure including a tunnel dielectric film, a floating gate, an inter-gate insulating film, and a control gate stacked on a semiconductor substrate. The floating gate in which charge is stored is made of a conductive film.

The MNOS series nonvolatile memory device has a metal nitride oxide semiconductor (MNOS) or metal oxide nitride oxide semiconductor (MONOS) structure. That is, a dielectric film serving as a charge storage layer is provided between the semiconductor substrate and the gate electrode. Nonvolatile memory devices of the MNOS series store information by using trap sites inside the dielectric layer. In particular, when the gate is made of a polysilicon film, it has a silicon oxide nitride oxide semiconductor (SONOS) structure. Chan et al. Introduced "SONOS (Silicon Oxide Nitride Oxide Silicon) type memory devices" (IEEE Electron Device Letters, Vol. 8, No. 1). 3, p. 93, 1987).

On the other hand, the program of the nonvolatile memory device uses a channel hot electron injection (CHEI) method, the current consumed in the programming process is several tens of watts to hundreds of watts per cell. In addition, the nonvolatile memory device has a disadvantage in that it takes a long time to write data.

An object of the present invention is to provide a method of programming a nonvolatile memory device having an oxide film as a charge storage layer.

The present invention for achieving the above object provides a program method for performing a program by applying a charge to the oxide film after applying stress to the oxide film of a nonvolatile memory device having an oxide film as a charge storage layer.

A nonvolatile memory device to which the method of programming a nonvolatile memory device according to an aspect of the present invention is applied includes an oxide film charge storage layer interposed between a semiconductor substrate and a gate electrode and a source / drain formed in the semiconductor substrate across the gate electrode. It includes. The program method includes applying stress to the oxide charge storage layer and injecting charge into the stressed oxide charge storage layer.

A nonvolatile memory device to which a method for programming a nonvolatile memory device according to another aspect of the present invention is applied includes a semiconductor substrate, a source / drain formed in the semiconductor substrate with a channel region therebetween, a gate electrode covering the channel region, and And an oxide charge storage layer interposed between the semiconductor substrate and the gate electrode and at least one pocket ion implantation region formed in the semiconductor substrate between the channel region and the source / drain. The program method includes applying stress to the oxide charge storage layer and injecting charge into the stressed oxide charge storage layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

1A and 1B show a program according to the present invention Sectional views showing the structure of a nonvolatile memory device to which the method is applied.

Referring to FIG. 1A, a nonvolatile memory device includes an oxide charge storage layer 20, a gate electrode 30, and the gate electrode 30 stacked on a first conductive semiconductor substrate 10. And second diffusion regions 40a and 40b formed at both ends of the semiconductor substrate 10 to form a source / drain. The channel region 11 is provided on the surface of the semiconductor substrate 10 of the diffusion regions 40a and 40b. A pocket ion implantation region 50a of a first conductivity type is formed in the semiconductor substrate 10 between the channel region 11 and at least one of the diffusion regions 40a and 40b. That is, referring to FIG. 1B, the non-volatile memory device may include pocket ion implantation regions 50a and 50b of first conductivity type formed in the semiconductor substrate 10 between the channel region 11 and each of the diffusion regions 40a and 40b. ) May be included.

Each nonvolatile memory device shown in FIGS. 1A and 1B has the following structural features.

The oxide charge storage layer 20 may be formed of at least one of a SiO film, a SiON film, an AlO film, a ZrO film, an AlO film, an HfO film, and a LaAlO film. In addition, the oxide charge storage layer of the nonvolatile memory device applied to the embedded device may be formed of the same material as the gate dielectric layer of the high voltage transistor. Accordingly, the photolithography step may be omitted in the manufacturing process of the semiconductor device including the oxide charge storage layer, which is advantageous in terms of cost reduction.

Meanwhile, a nonvolatile memory device having a nitride film as a conventional charge storage layer includes a tunnel oxide and a blocking oxide layer on and under a nitride film-based dielectric layer forming a charge storage layer. On the contrary, as shown in FIGS. 1A and 1B, the nonvolatile memory device to which the program method according to the present invention is applied may be simplified by not including the tunnel oxide film and the blocking oxide film. In addition, there is an advantage that it is easy to be embedded in logic.

The pocket ion implantation regions 50a and 50b are intended to increase program / erase efficiency. The concentration of the pocket ion implantation regions 50a and 50b having the same conductivity type as that of the semiconductor substrate 10 is relatively higher than that of the semiconductor substrate 10. Short channel effects may be suppressed according to the formation of the pocket ion implantation regions 50a and 50b. That is, the threshold voltage is locally raised by the pocket ion implantation regions 50a and 50b to prevent punch-through. In addition, the generation of hot electrons in the program mode may be optimized by the pocket ion implantation regions 50a and 50b. The pocket ion implantation regions 50a and 50b may concentrate electric fields in portions of the oxide charge storage layer adjacent to the diffusion regions 40a and 40b to increase program efficiency due to electron injection.

The nonvolatile memory device of FIGS. 1A and 1B may be manufactured according to the following procedure. That is, the oxide film charge storage layer 20 is formed on the first conductive semiconductor substrate 10. Subsequently, a conductive film is deposited and patterned on the oxide charge storage layer 20 to form a gate electrode 30. Next, ions are implanted into the semiconductor substrate 10 across the gate electrode 30 to form diffusion regions 40a and 40b forming a source / drain.

At least one contacting any one of the diffusion regions 40a and 40b in the semiconductor substrate 10 at one end or both ends of the gate electrode 30 before or after the formation of the diffusion regions 40a and 40b. Pocket ion implantation regions 50a and 50b are formed. The pocket ion implantation regions 50a and 50b are formed to have the same conductivity type as the semiconductor substrate 10. For example, when the semiconductor substrate 10 is P type, B or BF may be implanted to form the pocket ion implantation regions 50a and 50b. On the other hand, the ion implantation is formed by implanting ions in the range of 0 degrees to 45 degrees around the normal of the surface of the semiconductor substrate 10. At this time, ions may be implanted with energy of several KeV to several hundred KeV. More specifically, ions may be implanted at an energy of 5 KeV to 200 KeV.

According to the present invention, a program / read / erase of a nonvolatile memory device having a pocket ion implantation region and an oxide film charge storage layer is performed as follows.

Hereinafter, a program method will be described with reference to FIG. 9, which is viewed as a program method of a nonvolatile memory device according to the present invention.

First, stress is applied to the oxide charge storage layer (100). In an embodiment of the present invention, a voltage of −5 V and 4 V is applied to the gate electrode and the drain, respectively, to apply stress to the oxide charge storage layer for 400 kV.

Subsequently, a charge is injected into the oxide charge storage layer as follows (200).

The program of the nonvolatile memory device according to the embodiment of the present invention uses the CHEI method. That is, a potential difference is generated between the source and the drain. A channel is formed by the generated lateral electric field, and electrons move from the source to the drain along the channel. As it travels along the channel, electrons get energy, and hot electrons that are energized enough to cross the barrier between the semiconductor substrate and the charge storage layer are injected and trapped in the charge storage layer. The likelihood of injecting these hot electrons is highest near the drain where the electrons get the most energy. According to the program, when electrons are injected into the oxide charge storage layer, the threshold voltage is increased.

One or two bits can be programmed per nonvolatile memory cell.

For example, to implement 1-bit per one nonvolatile memory cell, referring to FIG. 1A, the gate electrode 30, the first diffusion region 40a serving as a source, and serving as a drain, may be used. Voltages of 4 V, 1 V, and 4.5 V are respectively applied to the second diffusion region 40b to inject electrons into one region of the oxide charge storage layer 20 by the CHEI method.

When implementing two bits per one nonvolatile memory cell, referring to FIG. 1B, separate left and right bit regions of the oxide charge storage layer 20 adjacent to the diffusion regions 40a and 40b by the CHEI method. Electrons can be injected into (L, R). Each area defines 1-bit. When programming to the left-bit region L, the first diffusion region 40a serves as a drain and the second diffusion region 40b serves as a source. In contrast, when programming to the right-bit region R, the first diffusion region 40a serves as a source and the second diffusion region 40b serves as a drain.

Hereinafter, the read method will be described.

The readout of the nonvolatile memory device is similar to the program method described above. However, a lower voltage is applied to the gate electrode during programming. The programmed nonvolatile memory device has an increased threshold voltage. Thus, if a voltage lower than the increased threshold voltage is applied, no current flows and is recognized as programmed.

For example, when implementing 1-bit per one nonvolatile memory cell, referring to FIG. 1A, a voltage lower than a program voltage is applied to the gate electrode 30 during read. When the nonvolatile memory device is programmed, since the threshold voltage is increased, the nonvolatile memory device is 'turned off' and no current flows. On the contrary, when the nonvolatile memory device is not programmed, it has a relatively low threshold voltage and thus is 'turned on' so that current flows. As shown in FIG. 1B, the read direction may be the same direction as the program direction.

Meanwhile, when two bits per one nonvolatile memory cell are implemented, referring to FIG. 1B, each read direction may be reverse to the program direction. That is, when reading information stored in the left-bit region L, the first diffusion region 40a serves as a drain and the second diffusion region 40b serves as a source. The opposite is true when information stored in the right-bit area R is read. That is, the first diffusion region 40a serves as a source and the second diffusion region 40b serves as a drain.

Hereinafter, the erase method will be described.

Erasing a nonvolatile memory device that implements 1-bit per cell is performed by applying a negative voltage to the gate electrode. In this case, a positive voltage is applied to any one of the two diffusion regions 40a and 40b. Alternatively, the diffusion regions 40a and 40b may be floated.

Meanwhile, erasure of a nonvolatile memory device implementing 2-bits per cell is performed by applying a negative voltage to the gate electrode and applying a positive voltage to the two diffusion regions 40a and 40b. In this case, positive voltages may be sequentially applied to the diffusion regions 40a and 40b.

On the other hand, since the pocket ion implantation region is provided in the semiconductor substrate between the diffusion region and the channel region, the program efficiency can be improved.

2A and 2B are graphs showing a current-voltage (I-V) relationship according to program time of a nonvolatile memory device having no pocket ion implantation region and a nonvolatile memory device having a pocket ion implantation region, respectively.

The results in FIGS. 2A and 2B were obtained by applying voltages of 4 V, 4.5 V and 1 V to the gate electrode, drain and source, respectively. The threshold voltage was measured based on the time when a current of 1 mA flows in the drain. As shown in FIG. 2A, in the nonvolatile memory device having no pocket ion implantation region, the threshold voltage hardly changed with the program time. In contrast, as shown in FIG. 2B, in the nonvolatile memory device having the pocket ion implantation region, the threshold voltage is changed according to the program time. On the other hand, the result shown in FIG. 2B is obtained by reverse read after a program.

Meanwhile, as shown in FIGS. 2A and 2B, the nonvolatile memory device including the oxide charge storage layer and the pocket ion implantation region could be programmed even at a gate voltage lower than 5V.

In addition, a relatively high voltage may be applied to a nonvolatile memory device having a pocket ion implantation region, for example, a voltage of 8 V, 6 V, and 0 V is applied to the gate electrode, the source, and the drain, respectively, for 10 ㎲. In this case, the threshold voltage changed by about 1.0 V. In addition, thresholds are applied when a voltage of -1 V, 8 V, 6 V, and 0 V is applied to the substrate, the gate electrode, the source, and the drain of the nonvolatile memory device having the pocket ion implantation region, respectively, for 10 s. The voltage changed by 2.0 V. From this, it can be seen that the program efficiency can be further improved by applying a negative voltage to the substrate.

In addition, since the pocket ion implantation region is provided in the semiconductor substrate between the diffusion region and the channel region, the erase efficiency can also be improved.

FIG. 3 is a graph showing I-V variation with erase time of a nonvolatile memory device having no pocket ion implantation region. The results shown in FIG. 3 were obtained by applying voltages of −4 V and 4 V to the gate electrode and the drain, respectively. In the nonvolatile memory device having no pocket ion implantation region, as shown in FIG. 3, the change of the threshold voltage hardly changed with the erase time, and the current drivability is increased when the gate voltage becomes 2.5 V or more. ) Is reduced.

FIG. 4 is a graph showing I-V changes when a nonvolatile memory device having a pocket ion implantation region is preprogrammed (1), programmed (2), and erased (3) for 1 second. Unlike the nonvolatile memory device having no pocket ion implantation region, the nonvolatile memory device having the pocket ion implantation region is 1.2 at a program threshold voltage of 2.45 V (drain current of 1 mA) as shown in FIG. A voltage change of 1.25V occurred with the erase threshold voltage of V.

As such, it can be seen that a pocket ion implantation region is required to increase the efficiency of programming and erasing the nonvolatile memory device including the oxide charge storage layer.

As described above, the program efficiency can be improved by applying stress to the oxide film forming the charge storage layer prior to the program of the nonvolatile memory device. 5 is a graph showing a change in program speed according to a stress condition applied before executing a program.

FIG. 5 shows a case in which an erase stress is applied for 400 kV by applying voltages of -5 V and 4 V to the gate electrode and drain (A) and voltages of -4 V and 3 V respectively to the gate electrode and drain. Erasing stress was applied for 400 ms (B). When a relatively high voltage was applied (A), the program speed was found to be fast.

FIG. 6 shows the program speed as an I-V curve when stress is applied for 400 kV by applying voltages of -5 V and 4 V to the gate electrode and the drain, respectively. On the other hand, as shown in Fig. 6, a stress voltage is applied to a nonvolatile memory device having only an oxide film as a charge storage layer under the above-described conditions, and then a program is performed to obtain a threshold voltage of about 4 V at a program time of 1 kHz. there was.

7A is a graph showing endurance measurement results under low program voltage conditions. The program was programmed for 10 kV with 4 V, 4.5 V and 1 V applied to relatively low voltage conditions, namely the gate electrode, drain and source. Erasure was performed for 2 kV by applying voltages of -4 V and 4 V to the gate and the drain, respectively. A good threshold voltage window of 0.7 V was obtained in 100,000 cycles despite the low voltage conditions below 6 V. In addition, when the oxide film is used as the charge storage layer, an over-erase problem does not occur and thus the endurance efficiency does not decrease.

7B is a graph showing endurance measurement results under high program voltage conditions. The program was programmed for 100 kV with 6 V, 5 V, and 0.5 V applied to relatively high voltage conditions, namely the gate electrode, drain, and source. Erasure was performed for 1 kHz by applying voltages of -5 V and 4 V to the gate and drain, respectively. It was expected that under these conditions a threshold voltage window of greater than 1.3 V could be obtained. In addition, under the above conditions, no drop of the program threshold voltage or excessive rise of the erase threshold voltage was observed at the end of the endurance. This property is believed to be suitable for low read voltage conditions of 2 V or less.

8 is a graph showing bake retention characteristics. Results (1) and (3) of FIG. 8 are obtained from the same initial threshold voltage and different bake temperatures, i. Results (2) and (3) of Figure 8 are obtained at different initial threshold voltages and the same bake temperature, i.e. 85 ° C. From the results of FIG. 8, it is expected that the threshold voltage will decrease to 1.5 V after 10 years at 85 ° C. and 125 ° C. bake conditions when the initial voltage is 3.3 V to 3. 8 V. FIG. From this, it is expected that the baking characteristic can be further improved by increasing the initial threshold voltage to about 5V.

In the above-described method of programming a nonvolatile memory device having an oxide film charge storage layer, program efficiency can be improved by applying a charge to the oxide film after applying stress to the oxide film to perform a program.

1A and 1B are cross-sectional views illustrating a structure of a nonvolatile memory device to which a program method according to the present invention is applied.

2A is a graph showing I-V characteristics according to program time of a nonvolatile memory device having no pocket ion implantation region.

2B is a graph showing I-V characteristics according to program time of a nonvolatile memory device having a pocket ion implantation region.

FIG. 3 is a graph showing I-V variation with erase time of a nonvolatile memory device having no pocket ion implantation region.

4 is a graph showing I-V variation of a nonvolatile memory device having a pocket ion implantation region.

5 is a graph showing a change in program speed according to a stress condition applied to an oxide film before the program is executed.

6 is a graph showing a change in program speed after stress is applied to an oxide film.

7A is a graph showing the results of endurance measurements under low program voltage conditions.

7B is a graph showing endurance measurement results under high program voltage conditions.

8 is a graph showing bake retention characteristics.

9 is a program flowchart of a nonvolatile memory device according to the present invention.

Explanation of reference numerals for the main parts of the drawing

10: semiconductor substrate 20: charge storage layer

30: gate electrode 40a, 40b: diffusion region

50a, 50b: pocket ion implantation region

Claims (7)

A method of programming a nonvolatile memory device comprising an oxide charge storage layer interposed between a semiconductor substrate and a gate electrode and a source / drain formed in the semiconductor substrate across the gate electrode. , Applying stress to the oxide charge storage layer; And And injecting charge into the stressed oxide charge storage layer. A semiconductor substrate, a source / drain formed in the semiconductor substrate with a channel region interposed therebetween, a gate electrode covering the channel region, an oxide charge storage layer interposed between the semiconductor substrate and the gate electrode, and the channel. A program method for a nonvolatile memory device comprising at least one pocket ion implantation region formed in the semiconductor substrate between a region and a source / drain, wherein the program method comprises: Applying stress to the oxide charge storage layer; And And injecting charge into the stressed oxide charge storage layer. The method of claim 2, And said semiconductor substrate and said pocket ion implantation region have the same conductivity type. The method according to any one of claims 1 to 3, And the oxide charge storage layer comprises at least one of a SiO film, a SiON film, an AlO film, a ZrO film, an AlO film, an HfO film, and a LaAlO film. The method according to any one of claims 1 to 3, And in the stressing step, applying a negative voltage to the gate and a positive voltage to the drain. The method of claim 5, wherein And injecting the charge, applying a positive voltage to the source and the drain, and generating a potential difference between the source and the drain. The method of claim 6, And injecting the charge, applying a negative voltage to the semiconductor substrate.