KR20050039168A - Thin film transistor with asymmetric dual gate and method for fabricating thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors. In particular, two gate electrodes are formed asymmetrically to suppress the kink current of a polycrystalline silicon thin film transistor so that holes formed in the drain junction reach the source electrode. A thin film transistor having an asymmetric dual gate in which a quench current is suppressed in a saturation region and a method of manufacturing the same.

Description

Thin film transistor having an asymmetric dual gate and a manufacturing method therefor {THIN FILM TRANSISTOR WITH ASYMMETRIC DUAL GATE AND METHOD FOR FABRICATING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors. In particular, two gate electrodes are formed asymmetrically to suppress the kink current of a polycrystalline silicon thin film transistor so that holes formed in the drain junction reach the source electrode. A thin film transistor having an asymmetric dual gate in which a quench current is suppressed in a saturation region and a method of manufacturing the same.

Low-temperature polycrystalline silicon thin film transistors (poly-Si thin-film transistors) are the driving ability and density in flat panel displays such as the active matrix liquid crystal display (AMLCD) and the active matrix organic light emitting diode (AMOLED). It is expected to be adopted for high quality flat panel display because of its excellent analog circuitry.

However, polycrystalline silicon thin film transistors may cause an analog circuit malfunction due to a kink phenomenon in which the drain current suddenly increases due to parasitic bipolar action in the operating range of the saturation region, thereby failing to maintain a constant output resistance. . This is because the polycrystalline silicon thin film transistor is a three-terminal element of the gate 1, the source 2, and the drain 3, as shown in FIG. 1, because the lower portion of the channel 4 has a floating voltage. In the mode), the hole h ⁺ generated at the drain junction accumulates in the lower portion of the channel having the floating potential, and as a result, when the potential at the lower portion of the channel rises to be higher than the source portion and the predetermined potential, the hole is injected into the source and at the same time, the electron (e ^- ) Is injected into the bottom of the channel to increase the drain current. Therefore, such a kink phenomenon must be suppressed to stabilize the output resistance of the transistor so that the analog circuit can operate normally.

Since the kink current is generated in the saturation operating region of the transistor, when it is operated in the linear region, the kink phenomenon can be suppressed. In addition, there is also a structure to prevent the accumulation of holes in the channel by forming additional electrodes to artificially fix the potential of the lower portion of the channel or by placing the gate above and below the channel. However, all of them have a disadvantage in that it is difficult to produce low-cost production costs because additional wiring is required or the process is complicated.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and an object of the present invention is to provide a thin film transistor having an asymmetric dual gate which can effectively suppress the generation of kink current of a polycrystalline silicon thin film transistor, and a method of manufacturing the same. In providing.

Another object of the present invention is to provide a thin film transistor having an asymmetric dual gate which can prevent a malfunction in an analog circuit by forming a constant output resistance and a method of manufacturing the same.

In order to achieve the above object, the thin film transistor having the asymmetric dual gate of the present invention is a thin gate transistor having a dual gate structure including a first gate and a second gate, and a source and a drain. The channel under one gate operates in a linear operating mode and the channel below the second gate adjacent to the drain operates in a saturation operating mode. It is formed longer than the length, characterized in that a high concentration doped region having a floating potential is formed between the first gate and the second gate to suppress the kink current (kink current).

At least one or more gates may be further included between the first gate and the second gate.

In addition, to achieve the above object, a method of manufacturing a thin film transistor having an asymmetric dual gate of the present invention includes the steps of: (a) forming a polycrystalline silicon thin film on a substrate; (b) depositing a gate insulating layer and a gate electrode layer on the polycrystalline silicon thin film; (c) forming a dual gate electrode having an asymmetrical structure by etching the gate electrode layer and the gate insulating layer through photolithography and etching processes for gate patterning so that the length of the first gate is longer than that of the second gate. and; (d) implanting and activating impurities to form a source on the first gate side, a drain on the second gate side, and forming a highly doped region between the first gate and the second gate; And (e) forming an interlayer insulating layer and a metal wiring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the same components in the drawings are represented by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a plan view of a polycrystalline silicon thin film transistor having an asymmetric dual gate according to the present invention, and FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 2.

2 and 3, the polycrystalline silicon thin film transistor having an asymmetric dual gate of the present invention includes an asymmetric dual gate 10, a source 20, a drain 30, a highly doped region 40, and a gate insulating layer. It consists of 50.

The asymmetric dual gate 10 includes a first gate electrode 11 and a second gate electrode 12 having different lengths, and the first gate electrode 11 is positioned in the source direction and the second gate electrode 12 is disposed. ) Is the drain direction. The two gate electrodes 11 and 12 are electrically connected to have the same potential, and the length L1 of the first gate electrode 11 is necessarily longer than the length L2 of the second gate electrode 12 ( L1> L2) is set.

The heavily doped region 40 is formed between the first gate electrode 11 and the second gate electrode 12 and has a floating potential.

The source 20 and the drain 30 are highly doped regions having a floating potential, and are disposed below the first gate electrode 11 and the second gate electrode 12 between the source 20 and the drain 30. Two channels 61 and 62 are formed therein.

Referring to the operation of the polycrystalline silicon thin film transistor having an asymmetric dual gate according to the present invention having the above configuration is as follows. FIG. 4 is a schematic diagram of the voltage distribution in the saturation region of the polycrystalline silicon thin film transistor having the asymmetric dual gate of FIG. 3.

3 and 4, when operating the thin film transistor in a saturation operating mode (V _GS <V _DS ), the channel 62 under the second gate 12 operates in the saturation operating region. On the other hand, the channel 61 under the first gate 11 operates in a linear operating mode. This is because the voltage 20V between the source 20 and the drain 30 is mostly applied to the drain junction in the saturation operation region, so that the voltage drop at the drain junction occupies most of the voltage drop between the source and the drain. Thus, as shown in the voltage distribution of FIG. 3, the heavily doped region 40 between the gates has a potential of about 4V. At this time, since the transistor operates in the linear operating region V _GS <V _FS in the channel 61 under the first gate electrode 11, the formation of the electron-hole pair is suppressed, and thus the kink current generated from the accumulation of holes Suppressed.

5 shows the results of the simulation of the operation region with the semiconductor device simulator. As in FIG. 4, it can be seen that most of the voltage is applied to the drain junction and occupies most of the voltage drop.

 FIG. 6 is a view for comparing the operation of a polycrystalline silicon thin film transistor having an asymmetric dual gate according to the present invention and a conventional single gate polycrystalline silicon thin film transistor. FIG. 6A illustrates a single gate structure, and FIG. 6B illustrates an asymmetric dual gate structure.

Referring to FIG. 6 (a), in general, contributing to the formation of kink current in a silicon thin film transistor having a single gate 1 is the formation of electron-holes by impact ionization at the drain junction. The generated hole moves to the lower potential of the lower part of the channel 4 and accumulates in the lower part of the channel without exceeding the potential of the source 2. Continuous accumulation of holes increases the potential at the accumulated position and when this potential is high enough that the hole rises above the source potential, holes and electrons cross this potential barrier and electrons entering the channel flow into the drain 3 and drain current Will increase. However, the asymmetric dual gate structure according to the present invention can suppress the kink current since the generation of electron-hole pairs in the channel under the long gate is essentially suppressed. Referring to FIG. 6B, an electron-hole pair is generated in the channel 62 under the short gate 12, but the parasitic bipolar is formed by recombination of holes and electrons in the heavily doped region 40 between the gate electrodes. Even if the operation is suppressed and the current increases, the current that can flow in the channel 61 under the long gate electrode 11 is limited, so that the increase in the current can be suppressed. The gate layout is also asymmetrical and can form multiple gate fingers. However, the device only needs to operate in the linear operating region in the channel under the gate electrode adjacent to the source.

7A to 7D are cross-sectional views illustrating a manufacturing process of a polycrystalline silicon thin film transistor having an asymmetric dual gate according to an embodiment of the present invention.

First, as shown in FIG. 7A, 800 nm of amorphous silicon 101 is deposited on a glass or quartz wafer 100 on which an oxide film is deposited, or plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition. (low pressure chemical vapor deposition, LPCVD) and the like. If plasma chemical vapor deposition is used, dehydrogenation is carried out in a furnace at a temperature of 450 ° C. for 3 hours. In the case of using the low pressure chemical vapor deposition method, the hydrogen content in the thin film is extremely small, so it is not necessary to perform dehydrogenation. Subsequently, the XeCl (λ = 308 nm) excimer laser annealing process (ELA) is performed to recrystallize the amorphous silicon thin film, and the polycrystalline silicon thin film is patterned through a photolithography process.

In Fig. 7B, a tetraethoxysilane (TEOS) oxide film 102 to be used as the gate oxide film is deposited to 1000 m thick, followed by a 3000 m thick aluminum thin film 103. The photolithography process forms an asymmetric gate electrode pattern, and continuously etches the aluminum thin film and the TEOS oxide film.

In FIG. 7C, phosphors (Phosphorous) or boron (Boron) ions are implanted and irradiated with a laser beam to activate the implanted ions to form the source 104, the drain 105, and the heavily doped region 106. At this time, the ion implantation process conditions are 30 keV and 5x10 ¹⁵ atoms / cm ^{2 for} phosphorus, and 10 keV and 1x10 ¹⁵ atoms / cm ² for boron.

Lastly, in FIG. 7D, a silica (SiO ₂ ) oxide layer 107, which is an interlayer insulating layer, is deposited on the entire structure, and then a contact hole for connecting to an external circuit through a photo and oxide layer 107 etching process. To form. Subsequently, after the aluminum metal thin film is deposited, the metal wiring 108 is formed by patterning using a photo and etching process, and then an oxide film (not shown) for device protection is deposited.

The maximum process temperature of the present invention described above is a low temperature process that can be applied to AMLCD using a glass substrate at 450 ° C. when plasma chemical vapor deposition is used, and no additional thermal process is required.

8 is a current-voltage transfer curve of a polycrystalline silicon thin film transistor having an asymmetric dual gate and a conventional single gate thin film transistor according to the present invention. The driving current (V _GS > 15 V, V _DS = 5 V) of a thin film transistor having an asymmetric dual gate is not significantly different from a thin film transistor by a single gate and exhibits substantially the same characteristics when the thin film transistor is in an on state. And it can be seen that the leakage current (V _GS <0V, V _DS = 5V) is lower than in the device invented. This is similar to the generally known symmetrical dual gate, and because of the additional formation of (highly doped regions) / (undoped regions) between the source and drain, the strength of the effective field applied to the drain junction is reduced. Because. The low leakage current brings about an improvement in the on / off current ratio of the thin film transistor, which is more advantageous for the device applied to the pixel.

FIG. 9 illustrates an n-channel thin film transistor as an output curve of an asymmetric dual gate thin film transistor and a single gate thin film transistor. When comparing the characteristics of two kinds of thin film transistors with the same channel length, the proposed asymmetric dual gate thin film transistor does not increase the drain current rapidly even at high drain voltage, whereas the drain current increases rapidly in the thin film transistor with single gate. You can check it. The phenomenon in which the drain current rapidly increases is generally referred to as a kink phenomenon, and at this time, the current is referred to as a kink current. The kink phenomenon is suppressed in the asymmetric dual gate thin film transistor structure according to the present invention.

FIG. 10 is a graph obtained by differentiating FIG. 9 with respect to the drain voltage. From this, it can be seen that the output resistance changes with the change of the drain voltage. In the single gate thin film transistor, as the drain voltage increases, a minimum value of the derivative value exists and after the minimum value, the derivative value increases. The derivative value is the inverse of the output resistance r _o . An increase in the derivative value means a decrease in the output resistance. In order to be applied to an analog circuit, the output resistance must be kept constant, but the variation of the output resistance occurs in a commonly used single gate thin film transistor. On the other hand, after the asymmetric dual gate thin film transistor reaches its minimum value, the asymmetric dual gate thin film transistor maintains the value almost so that there is no decrease in output resistance. This shows that the proposed structure effectively suppresses the kink phenomenon.

FIG. 11 is a graph illustrating output characteristics of p-channel polycrystalline silicon thin film transistors. The kink suppression phenomenon by this invention can be confirmed.

Therefore, the polycrystalline silicon thin film transistor according to the present invention can effectively suppress the kink current in the p-channel as well as the n-channel.

As described above, the polycrystalline silicon thin film transistor having the asymmetric dual gate according to the present invention can effectively suppress the kink current to form a constant output resistance to prevent malfunction in the analog circuit. This is a structure that can be applied to existing thin film transistor-LCD peripheral circuits as well as an active matrix organic light emitting diode (AM-OLED), which can be manufactured without an additional mask process. The advantage is that it is not necessary.

1 is a view for explaining a kink current generation mechanism in a conventional single gate polycrystalline silicon thin film transistor,

2 is a plan view of an asymmetric dual gate polycrystalline silicon thin film transistor according to the present invention;

3 is a cross-sectional view taken along the line AA ′ of FIG. 2;

4 is a schematic diagram of the voltage distribution in the saturation region of the polycrystalline silicon thin film transistor having the asymmetric dual gate of FIG.

5 is a simulation result of voltage distribution in a saturation region of a polycrystalline silicon thin film transistor having an asymmetric dual gate of FIG.

FIG. 6 is a schematic diagram illustrating a mechanism in which the king current is suppressed in the asymmetric dual gate polycrystalline silicon thin film transistor of the present invention compared with a conventional single gate polycrystalline silicon thin film transistor;

7A to 7D are cross-sectional views illustrating a manufacturing process of a polycrystalline silicon thin film transistor having an asymmetric dual gate according to an embodiment of the present invention;

8 is a current-voltage transfer curve of an asymmetric dual gate polycrystalline silicon thin film transistor and a conventional single gate polycrystalline silicon thin film transistor according to the present invention;

9 is an output curve of an asymmetric dual gate polycrystalline silicon thin film transistor and a single gate polycrystalline silicon thin film transistor in an n-channel polycrystalline silicon thin film transistor,

10 is a graph obtained by differentiating FIG. 9 with respect to a drain voltage;

11 is an output curve of an asymmetric dual gate polycrystalline silicon thin film transistor and a single gate polycrystalline silicon thin film transistor in an n-channel polycrystalline silicon thin film transistor.

Claims (5)

In a thin gate transistor having a dual gate including a first gate and a second gate, and a source and a drain, The channel under the first gate adjacent to the source operates in a linear operating mode and the channel under the second gate adjacent to the drain operates in a saturation operating mode. The length is formed longer than the length of the second gate, A thin film transistor having an asymmetric dual gate, wherein a high concentration doped region having a floating potential is formed between the first gate and the second gate to suppress a kink current. A substrate; A source, a drain formed on the substrate, and a highly doped region formed between the source and the drain; A first channel region formed between the source and the heavily doped region; A second channel region formed between the heavily doped region and a drain; First and second gates formed on the first channel region and the second channel region, respectively; And A first gate insulating layer and a second gate insulating layer respectively formed between the first gate and the first channel region and between the second gate and the second channel region, The thin film transistor having an asymmetric dual gate, wherein the length of the first gate is longer than the length of the second gate. The method of claim 2, wherein the first channel region and the second channel region is A thin film transistor having an asymmetric dual gate, characterized in that the polycrystalline silicon thin film layer. 3. The thin film transistor of claim 2, further comprising at least one or more gates formed between the first and second gates. (a) forming a polycrystalline silicon thin film on the substrate; (b) depositing a gate insulating layer and a gate electrode layer on the polycrystalline silicon thin film; (c) forming a dual gate electrode having an asymmetrical structure by etching the gate electrode layer and the gate insulating layer through photolithography and etching processes for gate patterning so that the length of the first gate is longer than that of the second gate. and; (d) implanting and activating impurities to form a source on the first gate side, a drain on the second gate side, and forming a highly doped region between the first gate and the second gate; And (e) a method of manufacturing a thin film transistor having an asymmetric dual gate, comprising forming an interlayer insulating layer and a metal wiring.