KR20050038847A - Circuit of generating high voltage in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage generation circuit of a semiconductor device. In a pumping circuit including a plurality of pumps, a ripple may be reduced by sequentially enabling the pumps during a regulation operation, thereby reducing power consumption. To provide a high voltage generation circuit.

Description

Circuit of generating high voltage in a semiconductor device

The present invention relates to a high voltage generation circuit of a semiconductor device, and more particularly to a high voltage generation circuit of a semiconductor device that can prevent the ripple of the pump output during the regulation of the pump.

After the pumping operation of the NAND flash, the pumps of each stage are simultaneously enabled during the regulation, causing a ripple phenomenon, resulting in a large current consumption.

1 is a block diagram of a conventional high voltage generation circuit.

2 is a graph illustrating an output of a conventional high voltage generation circuit.

Referring to FIGS. 1 and 2, a conventional high voltage generation circuit includes a regulator 10 that outputs a constant enable signal EN according to a band gap voltage Vbg and an external reference voltage Vref, and an enable signal. A plurality of logic units 20 for outputting the control clock signal CCLK according to the logic state of the EN and the clock signal CLK, and a plurality of pumping voltages Vpumpout according to the control clock signal CCLK. Pump 30.

The operation of the conventional high voltage generation circuit will be briefly described. The regulator 10 regulates an external band gap voltage Vbg and a reference voltage Vref to generate a constant enable signal EN. Each of the plurality of logic units 20 receives the enable signal EN and the clock signal CLK at the same time to generate the control clock signal CCLK of the same period. The pump 30 for generating the pumping voltage Vpumpout is simultaneously operated by receiving the control clock signal CCLK, which is the output of the same logic unit 20, to transmit the pumping voltage Vpumpout to the outside. However, since a plurality of pumps 30 are enabled at the same time, there is a problem that a ripple phenomenon occurs in the pumping voltage (Vpumpout) output of the pump.

Accordingly, the present invention provides a high voltage generation circuit of a semiconductor device that can reduce the occurrence of ripple by sequentially enabling the pump during regulation in order to solve the above problems.

A regulator for outputting a constant enable signal according to a bandgap voltage and a reference voltage according to the present invention, delay means for delaying the enable signal and outputting a plurality of delay signals, the enable signal, the plurality of delay signals, A logic means for outputting a plurality of control clock signals through a logic combination of clock signals and a pump means for outputting a pumping voltage by a plurality of pumps that are respectively delayed and operated according to each of the plurality of control clock signals. Provide a high voltage generation circuit.

A high voltage generation circuit of a semiconductor device comprising a regulator for outputting an enable signal and first to sixth pumps for generating a pump voltage, wherein the first pump is controlled according to the enable signal and a clock signal. A first logic unit generating a first clock control signal, a first delay unit delaying the enable signal to apply a first delay signal, and a second pump according to the first delay signal and the clock signal. A second logic section for generating a second clock control signal to control; a second delay section for delaying the first delay signal to apply a second delay signal; and the second delay section according to the second delay signal and the clock signal. A third logic section for generating a third clock control signal for controlling a third pump, a third delay section for delaying the second delay signal and applying a third delay signal, the third delay signal and the clock signal; A fourth logic section for generating a fourth clock control signal for controlling the fourth pump according to the call; a fourth delay section for applying a fourth delay signal by delaying the third delay signal; and the fourth delay signal. And a fifth logic unit for generating a fifth clock control signal for controlling the fifth pump according to the clock signal, a fifth delay unit for delaying the fourth delay signal, and applying a fifth delay signal; A high voltage generation circuit of a semiconductor device includes a sixth logic unit configured to generate a sixth clock control signal for controlling the sixth pump according to a delay signal and the clock signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

3 is a block diagram of a high voltage generation circuit of a semiconductor device according to the present invention.

4 is a graph showing the output of the high voltage generation circuit according to the present invention.

3 and 4, the high voltage generation circuit of the present invention includes a regulator 100 that outputs a constant enable signal EN according to an external band gap voltage Vbg and a reference voltage Vref. A delay means 200 for delaying the signal EN and outputting a plurality of delay signals DEN <0: N>, an enable signal EN, a plurality of delay signals DEN <0: N>, and a clock. Logic means 300 for outputting a plurality of control clock signals CCLK <0: M> through a logic combination of the signals CLK, and pumping voltages according to the plurality of control clock signals CCLK <0: M>. And pump means (400) for outputting Vpumpout.

The delay means 200 includes first to fifth delay parts 210 to 250 connected in series between the output terminal of the regulator 100 and the fifth output terminal of the delay means 200. The first delay unit 210 is connected between the output terminal of the regulator 110 and the first output terminal of the delay means 200 to delay the enable signal EN and output the first delay signal DEN1. The second delay unit 220 is connected between the first output terminal and the second output terminal to delay the first delay signal DEN1 again and output the second delay signal DEN2. The third delay unit 230 is connected between the second output terminal and the third output terminal to delay the second delay signal DEN2 again and output the third delay signal DEN3. The fourth delay unit 240 is connected between the third output terminal and the fourth output terminal to delay the third delay signal DEN3 again and output the fourth delay signal DEN4. The fifth delay unit 250 is connected between the fourth output terminal and the fifth output terminal to delay the fourth delay signal DEN4 again and output the fifth delay signal DEN5.

The logic means 300 is connected between the enable signal EN and the clock signal CLK input terminal and the first output terminal of the logic means 300 to logically combine the enable signal EN and the clock signal CLK. The first AND gate 310 to output the first control clock signal CCLK1, the first to fifth delay signal input terminals of the clock signal input terminal and the logic unit 300, and the second to sixth output terminals. Each of the second to sixth end gates 320 to 360 connected in series. The second AND gate 320 outputs the second control clock signal CCLK2 according to the clock signal CLK and the first delay signal DEN1. The third and gate 330 outputs the third control clock signal CCLK3 according to the clock signal CLK and the second delay signal DEN2. The fourth AND gate 340 outputs the fourth control clock signal CCLK4 according to the clock signal CLK and the third delay signal DEN3. The fifth and gate 350 outputs the fifth control clock signal CCLK5 according to the clock signal CLK and the fourth delay signal DEN4. The sixth AND gate 360 outputs the sixth control clock signal CCLK6 according to the clock signal CLK and the fifth delay signal DEN5.

The pump means 400 is connected between an input terminal of the first to sixth control clock signals CCLK1 to CCLK6 and an output terminal of the pump means 400, respectively, and outputs a predetermined pumping voltage. To 460).

The plurality of delay units 210 to 240 in the delay unit 200 may delay the signal by a value obtained by dividing one cycle of the clock signal CLK by the number of pumps in the pump unit 400. For example, if there are six pumps of the pump means 400, each of the delay units 210 to 240 delays by one sixth of one clock. Thereby, the pumps in the pump means can be driven sequentially within one period of the clock. It is possible to reduce the ripple of the pump voltage during the regulation operation.

The operation of the high voltage generation circuit of the present invention having the above-described configuration will be described below.

When an external band voltage Vbg and a reference voltage Vref are applied to the regulator 100, the regulator 100 generates an enable signal EN having a constant level. It is preferable to use a voltage of about 1V as the band voltage Vbg. The reference voltage Vref is preferably generated by an external reference voltage generator (not shown) and applied thereto. The regulator 100 may generate the enable signal EN having a constant level using the resistor divider.

The enable signal EN is transmitted to the first delay unit 210 and the first and gate 310. The first AND gate 310 generates the first control clock signal CCLK1 according to the enable signal EN and the clock signal CLK. The first pump 410 is enabled by the first control clock signal CCLK.

On the other hand, the enable signal EN applied to the first delay unit 210 is delayed by the first delay unit 210 and becomes the first delay signal DEN1, thereby causing the second delay unit 220 and the second end. Sent to gate 320. The second AND gate 320 generates the second control clock signal CCLK2 according to the first delay signal DEN1 and the clock signal CLK. The second pump 420 is enabled after a predetermined time delay after the first pump 410 is enabled by the second control clock signal CCLK2. The predetermined time refers to the time delayed by the first delay unit 210.

The first delay signal DEN1 applied to the second delay unit 220 is delayed by the second delay unit 220 to become the second delay signal DEN2, and thus the third delay unit 230 and the third AND gate are applied. 330 is sent. The third AND gate 330 generates the third control clock signal CCLK3 according to the second delay signal DEN2 and the clock signal CLK. The third pump 430 is enabled after a predetermined time delay after the second pump 420 is enabled by the third control clock signal CCLK3.

The second delay signal DEN2 applied to the third delay unit 230 is delayed by the third delay unit 230 to become the third delay signal DEN3 to form the fourth delay unit 240 and the fourth and gate. 340 is sent. The fourth AND gate 340 generates the fourth control clock signal CCLK4 according to the third delay signal DEN3 and the clock signal CLK. The fourth pump 440 is enabled after a predetermined time delay after the third pump 430 is enabled by the fourth control clock signal CCLK4.

The third delay signal DEN3 applied to the fourth delay unit 240 is delayed by the fourth delay unit 240 to become the fourth delay signal DEN4 to form the fifth delay unit 250 and the fifth and gate. Is sent to 350. The fifth AND gate 350 generates the fifth control clock signal CCLK5 according to the fourth delay signal DEN4 and the clock signal CLK. After the fourth pump 440 is enabled by the fifth control clock signal CCLK5, the fifth pump 450 is enabled after a predetermined time delay.

The fourth delay signal DEN4 applied to the fifth delay unit 250 is delayed by the fifth delay unit 250 to become the fifth delay signal DEN5 and transmitted to the sixth AND gate 360. The sixth AND gate 360 generates the sixth control clock signal CCLK6 according to the fifth delay signal DEN5 and the clock signal CLK. After the fifth pump 450 is enabled by the sixth control clock signal CCLK6, the sixth pump 460 is enabled after a predetermined time delay. In this way, it is possible to reduce the occurrence of ripple by sequentially enabling the pump at each stage. Reducing ripple reduces power consumption.

As described above, in the high voltage generation circuit including the plurality of pumps, the present invention can sequentially enable the pumps during the regulation operation to reduce the occurrence of ripple, thereby reducing the power consumption.

1 is a block diagram of a conventional high voltage generation circuit.

2 is a graph illustrating an output of a conventional high voltage generation circuit.

3 is a block diagram of a high voltage generation circuit of a semiconductor device according to the present invention.

4 is a graph showing the output of the high voltage generation circuit according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 100: regulator 20: logic section

30, 410 to 460: pump 200: delay means

210 to 250: delay unit 300: logic means

310 to 360: end gate 400: pump means

Claims (4)

A regulator for outputting a constant enable signal in accordance with the bandgap voltage and the reference voltage; Delay means for delaying the enable signal and outputting a plurality of delay signals; Logic means for outputting a plurality of control clock signals through a logic combination of the enable signal, the plurality of delay signals, and a clock signal; And a pump means for outputting a pumping voltage by a plurality of pumps which are respectively delayed and operated according to each of the plurality of control clock signals. The method of claim 1, The plurality of delay signals are respectively delayed by a period of the clock signal divided by the number of the pump, the high voltage generation circuit of the semiconductor device. In the high voltage generation circuit of a semiconductor device comprising a regulator for outputting an enable signal, and the first to sixth pump for generating a pump voltage, A first logic unit configured to generate a first clock control signal for controlling the first pump according to the enable signal and a clock signal; A first delay unit configured to delay the enable signal and apply a first delay signal; A second logic unit configured to generate a second clock control signal for controlling the second pump according to the first delay signal and the clock signal; A second delay unit which applies the second delay signal by delaying the first delay signal; A third logic unit configured to generate a third clock control signal for controlling the third pump according to the second delay signal and the clock signal; A third delay unit which applies the third delay signal by delaying the second delay signal; A fourth logic unit generating a fourth clock control signal for controlling the fourth pump according to the third delay signal and the clock signal; A fourth delay unit which applies the fourth delay signal by delaying the third delay signal; A fifth logic unit generating a fifth clock control signal for controlling the fifth pump according to the fourth delay signal and the clock signal; A fifth delay unit which applies the fifth delay signal by delaying the fourth delay signal; And And a sixth logic unit configured to generate a sixth clock control signal for controlling the sixth pump according to the fifth delay signal and the clock signal. The method of claim 1, And the first to fifth delay units delay one cycle of the clock signal by a value divided by six.