KR20050027261A - Semiconductor device - Google Patents

Abstract

A semiconductor device having a circuit which can be rewritten dynamically and a function for maintaining software compatibility in spite of the dynamically rewritable configuration. Simultaneously with software execution, data for rewriting a dynamically rewritable circuit and driver software for operating this are automatically generated and the latter part of an original program is replaced by the generated data. Thus, by maintaining software compatibility and diverting an existing software resource, it is possible to use the same software in various devices.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a configuration of a semiconductor device equipped with a dynamically rewritable circuit and a method of using the same.

Background Art Conventionally, with the spread of information processing apparatuses and high performance, various applications have emerged. These applications are described in software, and the forms executed in general-purpose processors have become mainstream. By the way, some applications require higher processing power than general-purpose processors, and the processor is required to further increase processing power.

For this reason, there is an example in which processing capacity is improved by mounting a dedicated circuit specialized for a specific application in one chip in addition to a general-purpose processor. Further, an example in which this dedicated circuit is constituted by a dynamically reconfigurable circuit (hereinafter referred to as DRC) is disclosed in Japanese Patent Laid-Open Nos. 10-4345 and 10-335462.

In this prior art, the DRC rewritable data is created in advance at the time of software creation of the application. By rewriting the DRC with the DRC rewrite data, the DRC functions as a dedicated circuit for a particular application. Software running on a general purpose processor includes DRC rewrite data and rewrite instructions.

As a result, the general-purpose processor can improve its processing capacity by rewriting the DRC while the application is running and functioning as a dedicated circuit.

As described above, the inventors of the present application prepare in advance according to the DRC and chip configuration using DRC rewritable data and driver software, and describe the DRC rewrite command and DRC rewrite data in software. I knew there was a problem with the software being unable to run. This limits the range of software that can be applied by the configuration of the DRC, and causes the situation that the software cannot be used because the processor software having the same instruction set and the configuration of the DRC are different.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device capable of ensuring software compatibility without improving the processing capacity by using the DRC, regardless of the DRC configuration.

1 is a block diagram showing the configuration of a semiconductor integrated circuit device of the present invention.

2 is a diagram illustrating timing of generation and execution of a DRC driver SW.

3 is a block diagram illustrating an exemplary configuration of a DRC.

4 is a block diagram showing an example of the configuration of an input / output register cell (IORC) that is a component of a DRC.

5 is a block diagram showing an example of a configuration of a computing cell (CC) that is a component of a DRC.

6 is a block diagram showing a configuration example of a rewrite determination unit (CDU).

7 is a block diagram showing the operation of a rewrite determination unit (CDU).

8 (A) is a normal SW, FIG. 8 (B) is a normal SW cut out from the normal SW by the HW / SW generation unit GU, and FIG. 8 (C) is a DRC created by the HW / SW generation unit GU. The driver SW, Fig. 8D, shows a list of operations of the instructions in the program.

9 is a flowchart illustrating the operation of the HW / SW generation unit GU.

10 is an example of a CDFG.

11 is an example of a CDFG subjected to a reduction process.

12 is an example of a CDFG scheduled using an As Late As Possible (ALAP) algorithm.

13 is an example of a CDFG scheduled using another As Soon As Possible (ASAP) algorithm.

Fig. 14 is a block diagram showing another configuration of the semiconductor integrated circuit device of the present invention.

Fig. 15 is a block diagram showing another configuration of the semiconductor integrated circuit device of the present invention.

Briefly, an outline of typical ones of the inventions disclosed in the present application will be described below.

A semiconductor device that executes software including arithmetic instructions, comprising: a plurality of arithmetic cells and a plurality of register cells, the type of arithmetic operations executed by arithmetic cells and wiring connections between a plurality of arithmetic cells and a plurality of register cells can be set; The calculation circuit includes setting data for setting the calculation type and wiring connection of the calculation cell based on software, and a control circuit for generating a driver / software for performing processing equivalent to software using the calculation circuit.

The types of operations include the executable OR of cell operations, the AND, the logical OR of exclusive OR, the arithmetic and LAM, and the comparative operation. Such a configuration makes it possible to generate driver software on a semiconductor device, thereby ensuring software compatibility. In addition, by creating the driver software during the execution of the software, high-speed processing using an arithmetic circuit can be performed without the user being aware of the overhead of creating the driver software.

Also, a semiconductor device for executing software including arithmetic instructions, comprising a register, an arithmetic unit, a plurality of arithmetic cells, and a plurality of register cells, the type of arithmetic operations executed by arithmetic cells, a plurality of arithmetic cells, and a plurality of registers. An arithmetic circuit capable of establishing wiring connections between cells, a first memory area for storing software, a second memory area for storing drivers and software for performing processing equivalent to software using the arithmetic circuit, and With a control circuit for controlling software, the processing of the software is repeated n times, and the processes from the first to i times (i <n) execute the software read from the first memory using registers and arithmetic operators. The control circuit receives the i-th processing and switches the software to be executed by the driver software to obtain the i-th control circuit. The processes from +1 to n times are performed by executing the driver software read out from the second memory area by using a calculation circuit. Such software and driver software are stored in different memory areas, and the control circuit switches the software and the driver software, thereby ensuring software compatibility.

This configuration is particularly effective for software that is repeated a plurality of times (e.g., software that forms a loop), and this loop is a process that appears well in image processing and audio processing.

EMBODIMENT OF THE INVENTION Hereinafter, typical embodiment by this invention is described in detail according to drawing. In addition, below, the same reference number shows the same or similar thing.

In the present invention, the DRC driver software for executing a part of the application software in the DRC from the application software (hereinafter referred to as "software SW") executed in the general-purpose processor without using the DRC (hereinafter referred to as The same software is automatically generated ("DRC driver SW"), and the general-purpose processor usually improves processing capacity by replacing part of the SW with the DRC driver SW and executing it.

The relationship between normal SW and DRC driver SW is demonstrated using FIG. 8 (A)-(D). 8A is a part of the fast Fourier transform program. Fast Fourier Transform is a process that is best used in multimedia processing. The program of Fig. 8A is described by the instruction set of the general purpose processor. The meaning of each instruction of the program is shown in Fig. 8D. The instruction set used in FIG. 8 is an example, and it will be apparent from the following description that the present invention is not limited to the instruction set.

In this embodiment, a software portion (loop) that is repeatedly executed in SW is usually executed by DRC. This is because, in order to automatically generate the DRC driver SW during the execution of the normal SW, it is considered to be effective to execute the software portion executed multiple times by the DRC. In the example of FIG. 8 (A), the program from the 4th line to the 18th line becomes the target (FIG. 8 (B)).

In the present invention, the DRC rewrite data and the DRC driver SW (Fig. 8 (C)) are generated based on the normal SW of Fig. 8B. The DRC rewrite data is data for setting the DRC so that the DRC executes an operation executed in the program of Fig. 8B. The DRC driver SW is a program for executing instructions that cannot be executed in the DRC among the programs of the SW, inputting data from the general-purpose processor to the DRC, and returning the result executed in the DRC to the general-purpose processor. Therefore, instead of executing FIG. 8 (B) using the general register GR and the operator ALU, the general purpose processor executes the operation by using the DRC by executing FIG. 8 (C), thereby processing capacity. To improve.

1 shows the configuration of the LSI chip 100 of the present invention. The LSI chip 100 includes a bus state controller (BSC), a direct memory access controller (DMAC), an on-chip memory (OCM), a DRC driver SW storage memory (DSM), and an instruction cache (ICH). ), The data cache DCH, the cache control unit CCN, and the CPU 101. The CPU 101 includes a DRC control unit 102, an instruction buffer IBF, an instruction patch unit IFU, a selector SEL, an instruction decoder IDC, a general purpose register GR, and an operator. (ALU) and DRC. The DRC control unit 102 is composed of a rewrite determination unit (CDU) and a hardware / software generation unit (GU) (hereinafter referred to as a HW / SW generation unit).

The instructions executed by the CPU 101 are stored in the instruction cache ICH, and the instructions stored in the instruction cache ICH are transmitted to the instruction buffer IBF according to the instruction load signal of the instruction patch unit IFU. . At the same time, the rewrite determination unit CDU always monitors the commands transmitted from the command cache ICH to the command buffer IBF.

In the example of Fig. 8A, the rewrite determination unit CDU detects the conditional branch instruction BF, and cuts the software portion shown in Fig. 8B as a program to be a candidate to be executed in the DRC based on it. Pay and save. When determining the software portion to be executed in the DRC, the rewrite determination unit (CDU) instructs the HW / SW generation unit (GU) to create DRC rewrite data, DRC rewrite and DRC driver SW.

The HW / SW generation unit GU generates DRC rewrite data from the cut program, and performs DRC rewrite. In addition, a DRC driver SW for using the rewritten DRC is generated, and the generated DRC driver SW is stored in the driver SW storage memory DSM. When these processes are finished, the HW / SW generation unit GU notifies the rewrite determination unit CDU of the end and notifies the head address where the DRC driver SW is stored.

In general, SW is usually stored in an on-chip memory (OCM) or an external memory chip (EXTM).

The execution of the program by the CPU 101 is as follows. It demonstrates by the example of FIG. Initially, the normal SW of FIG. 8A is executed as it is. After receiving the termination notice from the HW / SW generation unit (GU), the rewrite determination unit (CDU) is a program in which a command during execution of a normal SW transmitted from the command cache ICH to the command buffer IBF is replaced with a DRC driver SW. When the processing advances to the 15th line of the conditional branch instruction (corresponding to the 18th line of FIG. 8A) of the conditional branch instruction of FIG. 8 (B), the selector (through the command patch unit IFI) SEL) is switched, and the command inputted to the command decoder IDC is switched from the command buffer IBF to the determination unit CDU. Next, the instruction which converted the branch line address of the conditional branch instruction into the head address stored in the DRC driver SW is output to the instruction decoder IDC via the selector SEL. In the next CPU clock cycle, the rewrite determination unit CDU switches the selector SEL through the instruction patch unit IFU, and receives the instruction inputted from the determination unit CDU from the instruction buffer. Switch to (IBF). By these, the DRC driver SW is subsequently executed. The last instruction of the DRC driver SW is an unconditional branch instruction (the 15th line in Fig. 8C) to the address where the next instruction of the cut-out normal SW is stored, and execution of this instruction returns to the execution of the normal SW.

Here, the instruction is stored in the instruction cache ICH by execution of the instruction decoder IDC and executed by the cache controller CCN. The cache controller (CCN) is an on-chip memory (OCM) module that is a module on the processor bus (PRCB), a direct memory access controller (DMAC), and a bus controller (BSC) (external memory chip (EXTM)). One feature is that the memory SW is configured to be executable in the driver SW storage memory (DSM).

2 shows the timing of generation and execution of the DRC driver SW.

First, when a normal SW is executed and a conditional branch to an address preceding the address of the currently executing instruction stored in the program counter in the instruction patch unit IFU occurs (line 18 in Fig. 8A). The rewrite determination unit (CDU) temporarily determines that there is a loop in SW.

The rewrite determination unit (CDU) acquires and stores the instructions to be loaded into the instruction buffer IBF from the instruction cache ICH in the subsequent execution, that is, the instructions in the fourth to eighteenth lines of Fig. 8A. In the case of returning to the first instruction stored by the conditional branch instruction, the stored instruction is determined to form a loop, and the use of the DRC is formally determined.

In the third loop, the HW / SW generation unit GU creates the DRC rewrite data, the DRC driver SW, and the DRC rewrite. Since the DRC can be used in the third loop, the CPU 101 can perform the operation by the DRC by executing the DRC driver SW instead of the operation by the operation unit ALU. do. If the rewriting of the DRC does not end during the third loop, the CPU 101 executes the normal SW to the end of the loop including the time point at which the rewriting of the DRC ends.

Next, the structure of the DRC will be described in detail with reference to Figs. 3 shows the internal structure of the DRC. The input / output register cell IORC, the operation cell CC, the data input port 200 to the input / output register cell IORC, the register designation input port 201, the cell input lines 203a, 203b, 203c, And a data output port 202 of the DRC, cell output lines 204a and 204b from each cell, a wiring region 205, and a wiring program element 206. The wiring program element 206 is provided in a switch element for determining wirings among the wiring regions 205 and a storage element (for example, SRAM, Flash memory, etc.) not shown in order to store the on / off states of these switch elements. It is composed by.

When data is input to the DRC, a register designation signal is input from the instruction decoder IDC to the register designation input port 201, and one input / output register cell IOC is selected. Data is input by the data input port 200 and is input only to the selected input / output register cell IORC. When the data is output from the DRC, a register designation signal is input to the register designation input port 201 by the instruction decoder IDC. These switch the output selector OSEL and select the output of one input / output register cell IORC. Data enters the output selector OSEL from the cell output line 204a, and only selected data is output from the data output port 202.

FIG. 4 shows the configuration of the input / output register cell IOC of FIG. 3. The input / output register cell IORC is constituted by the input selector ISEL and the cell register CR. The input selector ISEL switches to the cell input line 203a from the wiring or the input from the data input port 200 in accordance with the input from the register designation input port 201. Data input via the input selector ISEL is held in the cell register CR. This cell register CR operates in synchronization with the clock input 301 and is reset by the reset input 302. In addition, although the wiring of a clock and a reset is abbreviate | omitted in FIG. 3, it is connected to the whole input / output register cell IORC and arithmetic cell CC. Data held in the cell register CR is output to the outside from the cell output line 204a.

In the present embodiment, data is input and output in units of 8 bits, but the size is not limited.

FIG. 5 shows the configuration of arithmetic cells CC of FIG. 3. The operation cell CC is composed of a cell operation unit CALU, a flip-flop FF, and an operation program element 400. The cell operation unit CALU has the same function as the ALU in the CPU and sets which calculation function is used by the calculation program element 400. Among the operable ORs, ANDs, and exclusive ORs of the cell operation units CALU, the arithmetic operations called addition and subtraction, and the comparison operation, the operation program element 400 sets an operation performed by the cell operation unit CALU.

In this way, the calculation contents of the calculation cell CC can be determined by setting the calculation program element 400 of the calculation cell CC. In addition, by setting the wiring program element 206, that is, data is inputted to the input / output register cell IORC and the operation cell CC, or the data of the input / output register cell IORC or the operation cell CC. You can set where to output the result. In this manner, the DRC rewrite data includes the setting value of the operation program element 400 and the setting value of the wiring program element 206, thereby enabling the desired calculation to be executed.

6 shows the configuration of the rewrite determination unit (CDU), and FIG. 7 shows the operation of the rewrite determination unit (CDU). The rewrite determination unit (CDU) includes a branch address storage buffer (BAB), a loop counter (LC), an instruction address determination unit (IADU), a DRC status register (DSR), a normal SW temporary buffer (TBF), , Branch controller (BCL). Moreover, the DRC status register DSR replaces an address having a portion indicating the state of the HW / SW generating unit GU, a portion storing a branch address to the DRC driver SW, and a next instruction of the normal SW to be replaced by the DRC driver SW. It consists of three parts of the part to be stored.

Hereinafter, the operation of the rewrite determination unit (CDU) is described in FIG. First, an instruction sent from the instruction cache ICH to the instruction buffer IBF is read into the instruction address determination unit IADU (500). The instruction address determination unit (IADU) extracts an address in the program counter PC from the instruction patch unit IFU, and whether the address of the currently executing instruction corresponds to the address area of the driver SW storage memory DSM. (501).

In this case, it means that the DRC driver SW is currently running. At this time, if the loop counter LC is any other value (502), the loop counter LC is set because the instruction of the first row of the DRC driver SW (that is, the MOV instruction of the first row of FIG. 8C). Reset to zero, branch controller BCL switches selector SEL to command buffer IBF side. Do nothing if the loop counter LC is zero. In the loop counter LC, the number of loops that are normally executed in SW is kept and reset by the reset signal.

If it is not applicable, it means that the normal SW is currently being executed, so the instruction address determination unit (IADU) determines whether the instruction is a conditional branch instruction. If it is not a conditional branch instruction and the value of the loop counter LC is 1 at this time, the second loop is executed. Therefore, in order to acquire the normal SW (see Fig. 2), the instruction address determination unit IADU stores the instruction in the normal SW temporary storage buffer TBF.

In step 505, the command address determining unit IADU checks the DRC status register DSR. The DRC status register (DSR) is a first register indicating the state of the DRC, a second register for storing a branch address (for example, an address where the MOV instruction in the first row of FIG. 8C is stored) to the DRC driver SW, and a DRC It consists of a 3rd address which stores the next address (for example, L003: (19th line) of FIG. 8 (A)) of the normal SW switched to the driver SW. The first register stores one of three states: "DRC unavailable", "DRC ready" and "DRC ready". Receives a CPU reset and updates it to the value of "DRC not available", updates it to the value of "DRC ready to use" at the start of DRC ready by the HW / SW generation unit (GU), and at the completion of DRC ready to use DRC ready to use ”is updated. Upon completion of the DRC usage preparation, the second address is updated, and upon notification of the start of operation to the GU, the third address is updated.

 If the first register of the DRC status register DSR is the value of "DRC ready to use", the branch controller BCL switches the selector SEL to the DRC control unit CDU via the command patch unit IFU. The output from the rewrite determination unit (CDU) is connected to the command decoder (IDC). Thereafter, a branch instruction is performed in which the branch line address of the branch instruction is changed to the head address of the DRC driver SW in the driver SW storage memory (DSM).

If the first register of the DRC status register (DSR) is other than the value of &quot; DRC ready to use &quot;, the existence of a loop is determined (temporary decision processing in Fig. 2). First, the instruction address determination unit IADU compares the current program counter PC with the branch line address (513). If the branch line address is larger, since there is no loop, the loop counter LC is set to 0 (514). When the program counter PC is larger, the instruction address determination unit IADU further compares the branch line address stored in the branch address buffer BAB with the branch line of the branch instruction. The branch address buffer (BAB) is a buffer which holds the branch line address up to date when a branch instruction is executed. Therefore, if the branch line is the same as the address of the branch address buffer BAB, the existence of the loop is determined, and the process moves to the generation process of the DRC rewrite data and the DRC driver SW. Specifically, 1 is added to the loop counter (509), and if the value is 2 (510), the instruction address determination unit (IADU) stores the branch instruction in the normal SW temporary storage buffer (TBF), and the DRC state. A value obtained by advancing one current PC value (e.g., address L003: (19th line) in Fig. 8A) into the third register of the register DSR is inputted to the HW / SW generation unit GU. In response to the start of the DRC ready signal is sent (511).

On the other hand, if the branch line is different from the address of the branch address buffer BAB, there is a possibility that a new loop exists. By the way, the instruction address determination unit IADU substitutes 1 into the loop counter LC to clear the normal SW temporary storage buffer TBF collectively.

The above operation will be described based on the program example of FIG. 8.

In the first loop execution, the instruction in the first to seventeenth lines of FIG. 8A is 0 in the loop counter LC, and nothing is executed in the flow of FIG. When the conditional branch instruction BF of the 18th line is accepted, the loop counter LC is set to 1 (508), and the branch line address (fourth line) is updated in the branch address buffer BAB.

In the second loop execution, the instructions of the fifth to seventeenth lines are stored in the SW temporary storage buffer TBF because the loop counter LC is 1 (504). When the conditional branch instruction BF of the eighteenth line is accepted, the branch line address and the address stored in the branch address buffer BAB match (507), so that the loop counter LC is set to 2 (509), The conditional branch instruction BF is sent to the normal SW temporary storage buffer TBF, and the HW / SW generation unit GU starts to prepare for DRC use (510, 511).

In the third loop execution, since the loop counter LC is 2 for each of the fifth to seventeenth lines, nothing is executed in the flow of FIG. If the conditional branch instruction BF of the eighteenth row is accepted and the DRC is in a usable state, the branch line address of the branch instruction is changed to the head address of the DRC driver SW (the first row in Fig. 8C). The subsequent loop execution is done using DRC.

In the execution of the DRC driver SW, the program branches to L003 (the 19th line in FIG. 8A) of the normal SW by a JMP instruction (the 15th line in FIG. 8C), and returns to the execution of the normal SW.

Next, the operation of the HW / SW generation unit GU will be described based on the flowchart of FIG. The HW / SW generation unit (GU) receives a command from the rewrite determination unit (CDU), acquires the normal SW (Fig. 8 (B)) from the normal SW temporary storage buffer TBF, and simultaneously stores the DRC status register DSR. A value of "DRC ready for use" is input to the first register (600).

The HW / SW generation unit GU first creates a CDFG (Control Data Flow Graph) from the acquired normal SW as shown in FIG. 10 (601). In the CDFG, each command of the inputted normal SW is represented at the node (command), and the data dependency relation of the command operand is indicated at the edge (arrow). In Fig. 10, numerals in parentheses in the block indicate the number of rows corresponding to Fig. 8B.

Fig. 10 shows the CDFG as it is from the normal SW of Fig. 8B. There are two types of dependency relationships: "dependency on control" and "dependency on data". The "control dependency" is a dependency relationship that sets the value of the register R0 by a DT instruction and executes the conditional branch instruction BF in accordance with the value of the register R0. This depends on the instruction set of the general purpose processor and needs to register the dependency in advance. The "dependency relationship on data" is a dependency relationship that, for example, performs calculation in the SUB using data transmitted by the MOV instruction. Therefore, it is necessary to determine by the contents of the program. The operand does not have any dependencies with the operands of other instructions, and it is located at the top and lower according to the dependency. The "dependency on data" is specifically determined as follows.

8 (B) The operands of the instructions in the second to fourth and tenth lines are located in the same column because they have no dependency on the operand of the instruction preceding it. "MOV @ R6, R2" means "transferring the data stored at the address indicated by the register R6 to the register R2." That is, the MOV instruction whose right value of the operand contains @ is an instruction to read data from the outside into a register, and since the operand according to @ first appears in FIG. It is located at the top. Since the instruction "MUL" in the fifth row uses the data in the registers R2 and R3, it has a dependency relationship with the instructions in the third to fourth rows. The instruction in the seventh line is for transferring the data of the register MACL to the register R7 because the execution result of "MUL" is input to the register MACL.

Similarly, the following program is used to determine the dependency relationship. However, it is necessary to note that the contents of the same register name may be updated when determining the edge. For example, "SUB R7 and R1" in the eighth row means "store the difference between the data of the register R7 and the data of the register R1 in the register R1". Since the data is updated by the execution of the instruction in the eighth row, "MOW R1 and @ R5" in the ninth row is dependent on the instruction in the eighth row, but is different from the "MOW @ R4 and R1" in the sixth row. There is no dependency.

In this way, the CDFG can be created by setting a dependency relationship with an instruction having a common register name among the instructions executed before the instruction to be considered. However, when there are a plurality of instructions having a common register name, a dependency relationship is set between the instructions executed immediately before in consideration of the possibility of updating the register data.

CDFG in FIG. 10 is abbreviated as CDFG in FIG. In short, the circuit configuration of the DRC is simplified, and the arithmetic processing in the DRC is performed at high speed.

The first form of abbreviation is to abbreviate 2 instructions (FIG. 10) of 701 to 1 instructions (FIG. 11) of 801. FIG. The STS instruction is an instruction to transfer data between registers without performing any operation processing. Such a transfer may be performed by an instruction set required by the instruction set when the general purpose processor processes it. However, when a DRC process is performed, the register stored in the necessary data and the operation cell may be directly connected. It does not need to be reflected in the composition of the DRC. In this way, the command for transferring data between registers is a command to be abbreviated in advance, and is registered in advance, so that the first abbreviation can be executed.

The second form of abbreviation is to abbreviate 4 instructions 702 (FIG. 10) to 802 3 instructions (FIG. 11). In general-purpose processors, because they are processed in time series, the contents of the register can be the same even if the register names are different. In the case of processing by the DRC, it is not necessary to reflect such a difference in register names in the structure of the DRC because the registers and data cells stored in necessary data may be connected. Therefore, for arithmetic instructions (MUL instruction, ADD instruction, and SUB instruction in the example of FIG. 8), the contents of the data of the registers are compared, and abbreviated when the same data is stored even if the registers are different. For example, the operands of the SUB instruction in the eighth row and the ADD instruction in the eleventh row have a common register R7 and are different in the registers R1 and R3. However, if the dependence on each data is taken, the contents stored in any register are &quot; data stored at the address indicated by the register R4, &quot;

Next, the HW / SW generation unit GU allocates a clock cycle to each node of the CDFG shown in FIG. 11 created in step 601 after scheduling, that is, considering hardware resource constraints. (602).

12 and 13 show examples in which the ALAP algorithm and the ASAP algorithm are used in combination with the CDFG of FIG. 11 as a method of scheduling. As Late As Possible (ALAP) algorithm is a scheduling that fills the back of concurrently executable instructions. The first of the commands that cannot be executed at the same time is the commands that are in interdependence. The second is that only one instruction that accesses the outside of the DRC can be executed in the cycle. This result is shown in FIG.

Moreover, FIG. 13 applies the As Soon As Possible (ASAP) algorithm that fills the concurrently executable instructions from the front with respect to the scheduling of FIG. 12. As much as possible, the processing time is spared by prepending the cycle of executing the instruction.

Instructions included in one cycle can be executed in one clock cycle, and the entire instruction can be executed in eight clock cycles in cycles 1 to 8.

The HW / SW generation unit GU generates DRC rewritable data in the scheduled CDFG shown in FIG. Specifically, it is as follows. The node portion is allocated to the input / output register cell (IORC) and arithmetic cell (CC). The input / output register cell (IORC) is allocated to the MOV instruction, and the operation cell (CC) is allocated to the operation instruction. According to the contents of the calculation instruction, setting data of the calculation program element 400 for setting the calculation contents of the calculation cell is created. In addition, since the edge of the CDFG represents the flow of data, the setting data of the wiring program element 206 is set so that the input / output register cell IORC and the operation cell CC are interconnected in accordance with the connection relationship of the edges of the CDFG. (603). The setting data of the arithmetic program element 400 and the setting data of the wiring program element 206 are DRC rewrite data.

The HW / SW generation unit GU rewrites the operation program element 303 and the wiring program element 206 of the DRC according to the DRC rewrite data (604). In parallel with this, a DRC driver SW is created (605).

How to create a DRC driver SW is described. The DRC driver SW shown in FIG. 8C is generated from the CDFG in FIG.

First, it is necessary to move the data stored in the general-purpose register GR to the input / output register cell IORC of the DRC. For example, the instruction "MOV @ R6, R3" in the third line of FIG. 8B is a "transfer data stored in the address indicated by the general register R6 to the general purpose register R3" instruction. In order to execute this instruction in the DRC, it is necessary to first move the data in the general register R6 during the DRC. Therefore, the instruction "MOV R6, dR6" of the 1st line of FIG. 8C is provided. This instruction means "transfer the data (address) stored in the general register R6 to the I / O register cell dR6 of the DRC." Such an instruction is provided in the first to third lines of Fig. 8C.

Subsequently, among the nodes shown in FIG. 13, a command to be executed other than the DRC is provided in the DRC driver SW. The commands in the fifth to twelfth rows in FIG. 8C correspond to nodes included in cycles 1 to 8 in FIG. 13, respectively.

(C) Fifth line "MOV @ dR6, dR3" is a "transfer data stored at the address indicated by the input / output register cell dR6 to the input / output register cell dR3" command, which is the same as that of FIG. It corresponds to "MOV @ R6, R3" of cycle 1. Although the same applies below, for example, in Cycle 3, two nodes, "MOV @ R4, R1" and "MUL" exist, and the latter is a command executed by the DRC, and thus does not appear in the DRC driver SW. In addition, cycle 6 contains only instructions executed by the DRC called "ADD". In that case, an empty operation has occurred, and a no operation instruction (NOP) is added.

In order to execute arithmetic instructions in the DRC, data required for arithmetic operations are stored in the I / O register cell IRC of the DRC, not in the general purpose register GR. Therefore, it is necessary to return the value after the calculation execution to the general purpose register GR. Therefore, the instructions of the thirteenth row and the fourteenth row of Fig. 8C are provided. For example, "MOV dR5 and R5" is a "transfer data stored in the input / output register cell dR5 to the general purpose register R5" instruction.

Finally, in order to return to the execution of the normal SW, the unconditional branch instruction JMP (the 15th line in FIG. 8C) from the normal SW to the next address of the conditional branch instruction is provided. The branch line of this unconditional branch instruction is an address stored in the third register of the DRC status register.

In this way, the scheduled CDFG of FIG. 13 is generated by the DRC driver SW of FIG. 8C. Taking into account external factors such as cache misses and interrupts, the core portion of the loop is originally required for 14 cycles in a single loop execution (lines 5 to 12 of Fig. 8C). Can be run in 8 cycles.

The created DRC driver SW is stored in the driver SW storage memory (DSM). The storage destination is the first address of the driver SW storage memory (DSM) if it is the first time, and the data is recorded after the last recorded part. If there is not enough recording area, data is written again from the head address of the driver SW storage memory (DSM).

Upon completion of step 605, the HW / SW generation unit GU writes a value of "DRC ready to use" in the first register of the DRC status register DSR, and steps to the second register of the DRC status register DSR. The head address of the memory stored in the DRC driver SW created in step 605 is recorded (606).

By operating the HW / SW generation unit GU in accordance with the above-described flow, DRC rewrite data creation and rewriting and DRC driver SW creation can be performed automatically at the time of program execution.

The modification of the structure of FIG. 1 is demonstrated using FIG. This embodiment is an example in which the DRC, rewrite determination unit (CDU), and HW / SW generation unit (GU) of the first embodiment shown in FIG. 1 are separated from the CPU 101. Specifically, the DRC is connected to the processor bus PRCB, and the rewrite determination unit CDU directly controls the control of the selector SEL. The command buffer IBF is placed behind the selector SEL.

The difference in operation from the configuration in FIG. 1 is that access to the input / output register cell (IORC) of the DRC is performed by designating an address. For example, an instruction that accesses an input / output register cell (IORC) of a DRC such as [MOW R6 dR6] on the first line of the DRC driver SW in FIG. Since it is connected to, the address of the input / output register cell (IORC) is not directly specified, but indirectly. For example, addressing such as [MOV R6 @ R12] is performed. This instruction means that the data of the general purpose register R6 is transferred to the input / output register cell IORC indicated by the general purpose register R12.

In this modification, by arranging the DRC outside the CPU, it is possible to increase the size of the DRC as compared with the configuration of FIG. In addition, since the DRC, the rewrite determination unit (CDU), and the HW / SW generation unit (GU) are separated from the CPU 101, the design can be easily changed. Moreover, it is also possible for modules other than the CPU to use the DRC. For example, the direct memory access controller (DMAC) can access the input / output register cell (IOR) on the DRC to use the DRC. In this case, it is also possible to execute different processes simultaneously in the DRC and the CPU 101.

Another modification of the structure of FIG. 1 is demonstrated using FIG. In this configuration example, the function of the DRC control unit 102 shown in FIG. 1 is realized by the DRC control dedicated processor (DCP). In this configuration example, since the functions of the DRC control unit 102 are implemented in a DRC control dedicated processor (DCP), the operations of the internal rewrite determination unit (CDU) and the HW / SW generation unit (GU) are realized in software. do. Therefore, the DRC control unit 102 can be easily updated by simply replacing the software of the DRC control dedicated processor (DCP), and the function of the LSI can be improved even after the LSI chip is manufactured using the present technology. Of course, it is also possible to implement combining the structure of FIG. 14 and the structure of FIG.

Moreover, the present invention can be modified in various ways. For example, the normal SW to be executed may be preliminarily executed, and the DRC rewrite data and the DRC driver SW may be registered in advance. In this case, since the process of generating the DRC rewrite data and the DRC driver SW becomes unnecessary during execution of the normal SW, the arithmetic processing using the DRC is performed from the second loop.

According to the configuration of the present invention, it is possible to automatically generate DRC rewritable data and DRC driver SW from software in a semiconductor device equipped with a processor and a DRC. With this configuration, even when using the DRC, it is not necessary to describe a dedicated program suitable for the DRC, and software compatibility can be maintained. As such, maintaining the compatibility of the software allows the same software to be used as long as the processor is useful and will function at least with the same instruction set.

The present invention is particularly effective for software that is repeated a plurality of times (e.g., software that forms a loop), and such a loop is a process well represented in image processing or audio processing.

Claims (12)

A semiconductor device that executes software containing operation instructions, Registers, With a calculator, An arithmetic circuit comprising a plurality of arithmetic cells and a plurality of register cells, the arithmetic circuit capable of setting the types of arithmetic operations executed by the arithmetic cells and wiring connections between the arithmetic cells and the plurality of register cells; Based on the software, the setting data for setting the operation type and the wiring connection of the operation cell, and a control circuit for generating driver software for performing processing equivalent to the software using the operation circuit. Semiconductor device. The method of claim 1, And the control circuit is configured to generate the setting data and the driver software during a period of executing the software using the register and the calculator. The method of claim 2, The processing of the software is repeated n times, Processing from the first to i times (i <n) is performed by executing the software using the register and the calculator, The semiconductor device from the i + 1 th time to the n th time is performed by executing the driver software using the arithmetic circuit. The method of claim 1, And the driver software includes at least a data transfer instruction from the register to the register cell of the arithmetic circuit and a data transfer instruction from the register cell of the arithmetic circuit to the register. The method of claim 1, The control circuit generates the setting data and the driver software by executing software for generating the setting data and the driver software. The method of claim 1, And said computing circuit is connected to a bus. The method of claim 1, A semiconductor device, wherein the number of clock cycles required to execute the software is smaller than the number of clock cycles required to execute the driver software. A semiconductor device that executes software containing operation instructions, Registers, With a calculator, An arithmetic circuit comprising a plurality of arithmetic cells and a plurality of register cells, the arithmetic circuit capable of setting the types of arithmetic operations executed by the arithmetic cells and wiring connections between the arithmetic cells and the plurality of register cells; A first memory area for storing the software; A second memory area for storing driver software for performing processing equivalent to the software by using the arithmetic circuit; Has a control circuit that controls the software to execute, The processing of the software is repeated n times, Processing from the first to i times (i <n) are performed by executing the software read from the first memory area using the register and the calculator, The control circuit receives the i-th processing and switches the software to be executed to the driver software. A semiconductor device carried out by executing the driver software read in the. The method of claim 8, The control circuit generates setting data for setting the operation type and the wiring connection of the calculation cell based on the software, and a driver software for performing processing equivalent to the software using the calculation circuit. Semiconductor device. The method of claim 8, The control circuit has setting data for setting the calculation type and the wiring connection of the calculation circuit, And said computing circuit sets said operation type of said computing cell and said wiring connection by said setting data during said software execution period. The method of claim 8, And the driver software includes at least a data transfer instruction from the register to the register cell of the arithmetic circuit and a data transfer instruction from the register cell of the arithmetic circuit to the register. The method of claim 8, A semiconductor device, wherein the number of clock cycles required to execute the driver software is smaller than the number of clock cycles required to execute the software.