KR20050024846A - switching circuit and plasma display panel including the same - Google Patents

Abstract

PURPOSE: A switching circuit and a plasma display panel with the same are provided to reduce the manufacturing cost by reducing the number of FETs with an excellent quality. CONSTITUTION: A switching circuit includes a ramp waveform generation unit(20) and a gate switching unit(30). The ramp waveform generation unit has at least two shift slopes by outputting the switching signals to the gate terminals of the FET. The gate switching unit selects the switching signal generated at the ramp waveform generation unit so as to input the selected switching signal to the gate terminal of the FET.

Description

Switching circuit and plasma display panel including the same

The present invention relates to a switching circuit and a plasma display panel including the same, and more particularly, to a switching circuit for outputting an output waveform having two or more transition groups and a plasma display panel including the same.

A plasma display panel (hereinafter referred to as a "PDP") is a flat panel display that displays characters or graphics by light emitted from plasma generated during gas discharge. PDP can be classified into DC and AC type. Among them, surface discharge type AC type based on ADS (Address Display-period Separation) driving method is widely commercialized.

The AC type PDP is a structure in which several cells are arranged in a matrix form and is generally driven by an ADS method that emits a cell by applying a low voltage.

Structurally, each cell of the PDP is surrounded by windshield, back glass and partition walls and has three electrodes-a scanning electrode, a sustain electrode and an address electrode.

The ADS driving method is a driving method consisting of a cycle of a reset step, an addressing step, and a sustain discharge step.

Looking at each step briefly, a reset step is an initialization step of uniformly erasing all wall charges of all PDP cells, an addressing step is a step of forming wall charges in a specific cell, and a sustain discharge step is performed by forming a plasma to emit light. Step.

The cell can be selected by the external driving IC, and the reset step, the addressing step, and the sustain discharge step are sequentially repeated to display characters and the like. In particular, since the wall charges are charged to the walls of each cell through the addressing step, the plasma may be generated even when a voltage is applied to the sustain electrode in the sustain discharge step.

In order to obtain various methods of erasing wall charges, the voltage applied to the electrodes in the reset step of the ADS has a waveform with various rising or falling transitions. This voltage waveform can be obtained by biasing a multi-step voltage on the gate terminal of the FET, and the bias voltage is applied from the ramp generation circuit.

However, when the conventional PDP is intended to have several transitions of the output signal, it has to be provided with as many ramp generation circuits and FETs as the number of transitions. FETs used for PDPs driven by high voltages and high currents of about 250V are required to be of high quality, and there is a problem in that the manufacturing cost of PDP driving circuits using a plurality of FETs is high.

It is an object of the present invention to provide a switching circuit having a minimum number of expensive FETs and a plasma display panel including the same.

The above object is a switching circuit comprising a switching FET for outputting an output waveform having two or more transition slopes according to the present invention, wherein the output waveform has two or more transition slopes by outputting a switching signal to a gate terminal of the FET. And at least one ramp waveform generator configured to have a gate switching unit, and a gate switching unit configured to select a switching signal generated by the ramp waveform generator to be input to a gate terminal of the FET. Can be.

The gate switching unit may include one or more BJTs, wherein the ramp waveform generating unit includes a capacitor, and the capacitor is connected to an output terminal of the FET so that a switching signal output to the gate switching unit is two or more transitions. You can have it.

In addition, the above object is a plasma display panel including a driving circuit having a switching FET for outputting an output waveform having two or more transitions according to the present invention, the output waveform by outputting a switching signal to the gate terminal of the FET At least one ramp waveform generator to have two or more transition slopes, and a gate switching unit to select a switching signal generated by the ramp waveform generator and to be input to the gate terminal of the FET. It may be achieved by a plasma display panel.

The gate switching unit may include one or more BJTs, wherein the ramp waveform generating unit includes a capacitor, and the capacitor is connected to an output terminal of the FET so that a switching signal output to the gate switching unit is two or more transitions. You can have it.

1 is a block diagram of a switching circuit according to an embodiment of the present invention.

As shown in FIG. 1, the switching circuit includes an output FET 10, a ramp waveform generator 20, and a gate switch 30.

The output FET 10 switches the input / output of the control signal input to the system through the output terminal 11.

The ramp waveform generator 20 is provided so as to match a desired number of transitions by outputting a switching signal to the gate terminal of the output FET 10 so that the output waveform of the output FET 10 has one or more transitions. The ramp waveform generator 20 includes a capacitor, which is connected to the output terminal 11 of the FET 10 so that the switching signal output to the gate switching unit 30 has one or more transitions. have.

The gate switching unit 30 selects a switching signal generated by the ramp waveform generating unit 20 and outputs the switching signal to the gate terminal of the FET 10 so as to receive an external control signal.

2 is a switching circuit diagram according to an embodiment of the present invention.

As shown in Fig. 2, the switch circuit has an output FET 10, a ramp waveform generator 20, and a gate switch 30.

The output FET 10 is used as an element for switching, and when used in a PDP, it needs to be able to withstand high voltage and high current. The drain terminal of the FET 10 is connected to the output terminal 11 outputting the output waveform, the source terminal is connected to the ground terminal, the gate terminal receives a switching signal.

One or more ramp waveform generators 20 are provided according to the transition of the desired output waveform, and each ramp waveform generator 20 includes resistors R20a to R21b, VR20a and VR20b, capacitors C20a and C20b, and It has diodes D20a and D20b.

The ramp waveform generator 20 receives a control signal and outputs a switching signal having one or more transition slopes to the gate terminal of the output FET 10 so that the output waveform of the drain terminal has one or more transition slopes. The transition of the switching signal is determined by the time constant by the resistors R20a to R21b, VR20a and VR20b and the capacitors C20a and C20b, and the variable resistors VR20a and VR20b are used to adjust the time constant. The diodes D20a and D20b are used as freewheeling diodes for extinguishing the voltage introduced by bypassing through the capacitors C20a and C20b at the output terminal 11 during the sustain discharge phase.

The gate switching unit 30 includes resistors R30a to R31b, pnp type BJTs Q31 and Q33, and npn type BJTs Q32 and Q34.

The resistors R30a to R31b are pull-up resistors so that a proper current flows to the base terminal of the BJT, and the pnp type BJTs Q31 and Q33 are switching signals generated by the ramp waveform generator 20. Acts as a switch for conducting / blocking input to the gate terminal of the output FET 10. The npn type BJTs (Q32, Q34) are BJTs that output control signals for turning on / off the pnp type BJTs (Q31, Q33).

When the high level signal is input from the ramp input terminal 40, the npn type BJTs Q32 and Q34 are turned on and the low level signal is input to the gate terminal of the pnp type BJTs Q31 and Q33. Accordingly, pnp type BJTs Q31 and Q33 are turned on, and a signal input to the emitter terminal is applied to the output FET 10.

Figure 3 is an output waveform diagram of the switching circuit shown in Figure 2, Figure 3 (a) is an input waveform input to the ramp input terminal A (40a), Figure 3 (b) is an input input to the ramp input terminal B (40b) 3 (c) is a waveform of the voltage input to the gate terminal of the output FET 10, and FIG. 3 (d) is a waveform of the voltage output from the output terminal 11. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

When a low level signal is input to the lamp input terminals A 40a and B 40b in the section ①, the capacitors C20a and C20b are charged by the high level signal flowing through the output terminal 11, and the BJT (Q31) is applied. Q34) and the output FET 10 are turned off.

When a high level signal is input to the ramp input terminal A 40a in the section ②, as time passes, the BJTs Q31 and Q32 are turned on and the voltage applied to the gate terminal of the output FET 10 gradually increases. . The output FET 10 is not turned on until the voltage at the gate terminal reaches the threshold voltage. However, when the voltage at the gate terminal reaches the threshold voltage, the output FET 10 is turned on to lower the voltage at the output terminal 11.

At this time, the decreasing slope of the output voltage becomes an important factor of circuit design. Even when the output FET 10 is turned on, the voltage of the output terminal 11 does not suddenly change to a low level signal due to the charging voltage stored in the capacitor C20a, and the resistors R20a, R21a, VR20a and the capacitor C20a are It is gradually decreased by the time constant determined by.

It can be seen that the waveform of the output terminal 11 reaches a low level as the capacitor C20a voltage is completely discharged in the section ③. Therefore, the input signal of the ramp input terminal A 40a completely charges the capacitor C20a in the direction opposite to the conventional charging direction, and is transferred to the gate terminal of the output FET 10 to gradually increase the gate voltage of the output FET 10. This rises.

In the period ④, all the transistors Q31 to Q34 are turned off while the high level of the ramp input terminal A 40a transitions to a low level signal. At this time, as the pnp type BJT (Q31) is turned off, the voltage of the output terminal 11 rises rapidly. In the section ⑤, the stable state is maintained as in the section ①.

In the section ⑥, the input signal transitions from the low level to the high level to the ramp input terminal B 40b. In the section ②, the phenomenon caused by the input signal of the lamp input terminal A 40a is repeated in the same manner. However, the rising slope of the gate voltage in the sections ② and ⑥ and the transition slope of the output terminal 11 vary depending on the time constant by the circuit elements of the respective ramp waveform generators 20.

In addition, as the capacitor C20b voltage is completely discharged in the section ⑦, the waveform of the output terminal 11 is stabilized to a low level, and as in the section ③, the voltage of the gate terminal of the output FET 10 gradually increases. At this time, the transition slope is determined by the time constant according to the circuit elements of the ramp waveform generator, and thus the waveform of the gate terminal voltage may have a transition slope different from that of the section ③.

The npn type BJTs Q32 and Q34 of the gate switching unit 30 use the input signal of the ramp input terminal 40 as a bias voltage, but use a separate enable signal as an input to prevent malfunction due to noise or the like. It would also be possible.

In addition, it is possible to have a variable resistor to adjust the time constant of the resistor and the capacitor for the slope of the output terminal 11, in particular for the fast transition of the capacitor (C20b) of the ramp waveform generator 20b of the present embodiment and It goes without saying that the resistor R21b to be connected may be omitted.

As an embodiment different from the above embodiment, the lamp input stage is switched, and the variable resistor or variable capacitor of the ramp waveform generator is varied according to the switching to generate a bias voltage having various transitions using one ramp waveform generator. It may be. That is, when there are several lamp input stages, an appropriate lamp input stage may be selected and output, and accordingly, the integer value of the circuit element of the ramp waveform generator may be changed. As the integer value of the circuit element changes according to the input signal input to the lamp input terminal, the transition gradient changes.

The above embodiment is a switching circuit for outputting a transition waveform having one or more slopes, and the present invention can be used in all products in which such switching circuit is used. In particular, in the reset driver of the PDP using a high voltage, the number of expensive output FETs 10 can be reduced, which can be very useful. In the above embodiment, the wall charges charged in all the cells of the PDP are erased according to the low level or high level signal of the output terminal 11. At this signal level, the wall charge cancellation will depend on the circuit design.

Although some embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that the embodiments may be modified without departing from the spirit or spirit of the invention. . It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

According to the present invention, the number of high quality FETs excellent in high heat, high voltage, etc. can be reduced, thereby reducing manufacturing costs.

1 is a block diagram of a switching circuit according to an embodiment of the present invention;

2 is a switching circuit diagram according to an embodiment of the present invention;

3 is an output waveform diagram of the switching circuit shown in FIG. 2 according to the embodiment of the present invention;

3 (a) shows an input waveform input to the ramp input terminal A of FIG.

FIG. 3 (b) shows an input waveform input to the ramp input terminal B of FIG.

FIG. 3C is a waveform of a voltage input to the gate terminal of the output FET of FIG.

3D is a waveform of a voltage output from the output terminal of FIG.

<Description of the symbols for the main parts of the drawings>

10: output FET 11: output stage

20: ramp waveform generator 30: gate switching unit

40: Lamp input terminal Q31, Q33: pnp BJT

Q32, Q34: npn BJT D20a, D20b: diode

R20a to R31b: resistors C20a and C20b: capacitors

Claims (6)

A switching circuit comprising a switching FET for outputting an output waveform having two or more transition slopes, One or more ramp waveform generators for outputting a switching signal to the gate terminal of the FET such that the output waveform has two or more transition slopes; And a gate switching unit for selecting a switching signal generated by the ramp waveform generator and inputting the switching signal to a gate terminal of the FET. The method of claim 1, The gate switching unit comprises at least one BJT. The method of claim 1, The ramp waveform generating unit includes a capacitor, and the capacitor is connected to an output terminal of the FET so that the switching signal output to the gate switching unit has two or more transitions. A plasma display panel comprising a driving circuit having a switching FET for outputting an output waveform having two or more transition slopes, One or more ramp waveform generators for outputting a switching signal to the gate terminal of the FET such that the output waveform has two or more transition slopes; And a gate switching unit for selecting a switching signal generated by the ramp waveform generator and inputting the switching signal to the gate terminal of the FET. The method of claim 4, wherein And the gate switching unit includes one or more BJTs. The method of claim 4, wherein The ramp waveform generating unit includes a capacitor, and the capacitor is connected to an output terminal of the FET so that the switching signal output to the gate switching unit has two or more transitions.