KR20050019621A - Repair apparatus of semiconductor memory device capable of selectively programming in wafer test and in post package test and repair method of the same - Google Patents

Abstract

PURPOSE: A repair apparatus of semiconductor memory device is provided to repair lots of fail memory cells with small occupancy by being programmed for both wafer test mode and post package test mode selectively. CONSTITUTION: A repair apparatus of semiconductor memory device comprises a repair control circuit(253) for programming one of the first fail memory cell address signal during the wafer test process or the second fail memory cell address signal during the post package test process; a redundancy memory cell array(251) for repairing one of a first fail memory cell or a second fail memory cell by being activated; a redundancy row decoder(252) for activating some of the redundancy memory cells by being enabled. Wherein, a normal decoder is disabled when the redundancy row decoder is enabled.

Description

Repair apparatus of semiconductor memory device capable of selectively programming in wafer test and in post package test and repair method of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a repair apparatus for a semiconductor memory device and a repair method thereof.

In recent years, as semiconductor memory devices are highly integrated and miniaturized, the manufacturing process of semiconductor memory devices is becoming more and more complicated. As a result, the number of fail memory cells generated during the manufacturing process of the semiconductor memory device is further increased. Accordingly, most semiconductor memory devices are designed to have a relatively small number of redundancy memory cell arrays that repair defective cells of the main memory cell array. A repair apparatus of a conventional semiconductor memory device having such a redundant memory cell array is described in US Pat. No. 5,576,999.

The row line or column line of the main memory cell array with one or more defective cells may be replaced with redundancy memory cells. To do this, the address of the defective cell must be programmed in advance in the repair control circuit of the repair apparatus. The repair control circuit programs the address of the defective cell by selectively cutting the fuses included therein. The fuse included in the repair control circuit may be generally implemented as a laser fuse cut by a laser beam or an electrical fuse cut electrically.

Next, a repair apparatus according to the prior art will be described with reference to FIG. 1. 1 illustrates a semiconductor memory device 100 including a repair device 150 according to the prior art. In FIG. 1, other internal circuits of the semiconductor memory device 100 are omitted for simplicity of the drawings. Referring to FIG. 1, the semiconductor memory device 100 may include a main memory cell array 110, a normal row decoder 120, a row address buffer 130, a row predecoder 140, and a repair. Device 150.

The repair device 150 may include a first redundancy memory cell array 151, a second redundancy memory cell array 152, a first redundancy row decoder 153, a second redundancy row decoder 154, and a repair control circuit ( 155). The repair control circuit 155 includes a first comparator 161, a second comparator 162, and a fuse box 163.

The first redundancy memory cell array 151, the first redundancy row decoder 153, and the first comparator 161 are defective cells of the main memory cell array 110 detected during a test process of a wafer state. (Hereinafter referred to as first defective cell) is repaired. In addition, the second redundancy memory cell array 152, the second redundancy row decoder 154, the second comparator 162, and the fuse box 163 may be packaged (hereinafter, referred to as post package). The defective cell (hereinafter referred to as a second defective cell) of the main memory cell array 110 detected in the test process of the package) is repaired.

The first comparator 161 includes a plurality of fuses F1 to F24 of FIG. 2, and the addresses of the first defective cells are preprogrammed in the fuses F1 to F24. The first comparison unit 109 will be described later in more detail with reference to FIG. 2. The address of the second defective cell is preprogrammed in the fuse box 163.

Referring to FIG. 2, the first comparator 161 includes an address comparison circuit 91 and a logic circuit 92. The address comparison circuit 91 includes a plurality of transistors 21 to 49 and a plurality of fuses F1 to F24.

The above-described repair apparatus 150 according to the related art includes parts 151, 153, and 161 for repairing a defect cell detected in a wafer state test process, and a portion 152 for repairing a defect cell detected in a post package test process. 154, 162, and 163 are separated into two repair parts. In addition, the redundancy memory cell array is divided into two redundancy memory cell arrays 151 and 152 used in each of the two repair parts. In order for the separated redundancy memory cell arrays 151 and 152 to occupy less area in a semiconductor memory device, the number of redundancy memory cells included in each of them is limited.

Accordingly, the repair apparatus according to the related art has a problem in that only a small number of memory cells capable of repairing defective cells detected in a wafer state test process and a post package test process, respectively, are limited. In addition, the repair apparatus according to the prior art has a problem in that timing control for the repair portions is performed separately because the signal paths of the two repair portions are different from each other.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a repair apparatus and a repair method for a semiconductor memory device that can be selectively programmed in a wafer test and a post package test.

According to another aspect of the present invention, a repair apparatus includes a main memory cell array including a plurality of main memory cells, a predecoder for first decoding an external address signal, and a first decoded address signal. 2. A repair apparatus of a semiconductor memory device including a second decoder for decoding and selecting and activating a part of the plurality of main memory cells, the repair apparatus comprising: a repair control circuit, a redundant memory cell array, and a redundancy decoder. The repair control circuit includes an address signal (hereinafter referred to as a first address signal) of a first defect cell detected in a wafer test process and an address signal (hereinafter referred to as a second address signal) of a second defect cell detected in a post package test process. Program a predetermined control signal in response to the first decoded address signal. The redundancy memory cell array includes a plurality of redundancy memory cells, and when activated, repairs any one of the first defective cell and the second defective cell of the main memory cell array. The redundancy decoder is enabled or disabled in response to the control signal and activates some of the redundant memory cells when enabled. When the redundancy decoder is enabled, the normal decoder is disabled in response to the control signal.

The repair method of the semiconductor memory device according to the present invention for achieving the above technical problem, the address signal (hereinafter referred to as the first address signal) of the first defective cell detected during the wafer test process is detected during the post-package test process A repair control circuit for programming any one of the address signals (hereinafter referred to as a second address signal) of the second defective cell and outputting a predetermined control signal in response to the decoded address signal received from the predecoder; 10. A repair method of a repair apparatus including a redundancy memory cell array including redundancy memory cells, and a redundancy decoder activating some of the redundancy memory cells in response to the control signal.

(a) determining whether an address signal programmed in the repair control circuit is the first address signal;

(b) when the first address signal is programmed in step (a), comparing the decoded address signal with the first address signal and outputting the control signal as a result of the comparison;

(c) comparing the decoded address signal with the second address signal when the first address signal is not programmed in step (a), and outputting the control signal as a result of the comparison; And

and (d) when the control signal is enabled, the redundancy decoder is enabled to activate some of the plurality of redundancy memory cells.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram illustrating a semiconductor memory device 200 including a repair device 250 selectively programmable in a wafer test and a post package test, according to an exemplary embodiment. In FIG. 3, other internal circuits of the semiconductor memory device 200 are omitted for simplicity of the drawing. Referring to FIG. 3, the semiconductor memory device 200 may include a main memory cell array 210, a normal row decoder 220, a row address buffer 230, a row predecoder 240, and a repair device 250. Include. The main memory cell array 210 includes a plurality of memory cells (not shown) arranged in a matrix form, and the plurality of memory cells store predetermined data. The row address buffer 230 receives a row address signal RADD from the outside and outputs the row address signal RADD to the row predecoder 240. The row predecoder 240 decodes the row address signal RADD and outputs the decoded address signal DRA. The normal row decoder 220 is enabled or disabled in response to a predetermined control signal REN. When the normal row decoder 220 is enabled, the decoded address signal DRA is decoded, and a specific word line (not shown) of the main memory cell array 210 is selected and activated.

The repair device 250 includes a redundancy memory cell array 251, a redundancy row decoder 252, and a repair control circuit 253. The repair control circuit 253 includes a wafer repair information generator 261, a fuse box 262, a controller 263, and a comparator 264. The redundancy row decoder 252 is enabled or disabled in response to the control signal REN. Here, when the redundancy row decoder 252 is enabled, the normal row decoder 220 is disabled.

When the redundancy row decoder 252 is enabled, a specific word line (not shown) of the redundancy memory cell array 251 is selected and activated. As a result, the word line including the defective cell of the main memory cell array 210 is replaced with the specific word line of the redundancy memory cell array 251.

The wafer repair information generation unit 261 is a wafer repair signal indicating whether or not an address signal of a defect cell (hereinafter, referred to as a first defect cell) detected in a test process of a wafer state is programmed in the comparison unit 264. Output (WRP) For example, when an address signal of the first defective cell is programmed in the comparison unit 264, the wafer repair information generation unit 261 enables the wafer repair signal WRP. In addition, when the address signal of the first defective cell is not programmed in the comparison unit 264, the wafer repair information generation unit 261 disables the wafer repair signal WRP.

The fuse box 262 includes a plurality of fuses (not shown), and an address signal of a defective cell (hereinafter, referred to as a second defective cell) detected in the post package test process is preprogrammed. Here, the program of the address signal for the second defective cell is made by selectively cutting the plurality of fuses. The plurality of fuses included in the fuse box 262 may be implemented as a laser fuse cut by a laser beam or an electrical fuse cut electrically.

When the address signal PRA of the second defective cell is programmed in the fuse box 262, the fuse box 262 is enabled during the repair operation of the repair apparatus 250. The fuse box 262 continuously outputs the programmed address signal PRA of the second defective cell during the repair operation of the repair apparatus 250. In contrast, when the address signal PRA of the second defective cell is not programmed in the fuse box 262, the fuse box 262 is disabled during the repair operation of the repair apparatus 250.

The controller 263 receives the wafer repair signal WRP from the wafer repair information generator 261, and receives an address signal PRA of the second defective cell from the fuse box 262. Here, when the address signal PRA of the second defective cell is not programmed in the fuse box 262, the controller 263 receives only the wafer repair signal WRP.

The controller 263 may determine a plurality of mode determination signals B1 ˜, which determine an operation mode of the repair apparatus 250 in response to the wafer repair signal WRP and the address signal PRA of the second defective cell. Bi) and the repair enable signal S are output. That is, the repair apparatus 250 operates to repair the first defective cell or repairs the second defective cell by the plurality of mode determination signals B1 to Bi and the repair enable signal S. FIG. To work. Here, the repair apparatus 250 operates to repair only one of the first defective cell and the second defective cell.

The comparator 264 receives the decoded row address signal DRA from the row predecoder 240. An address signal of a defective cell programmed in the comparator 264 as a comparison target between the mode determination signals B1 to Bi and the decoded row address signal DRA in response to the repair enable signal S. FIG. Is determined. That is, according to the mode determination signals B1 to Bi and the repair enable signal S, the address signal of the first defective cell is programmed in the comparing unit 264 or the second defective cell is programmed. The address signal PRA is programmed. The configuration and specific operation of the comparison unit 264 related to this will be described later in more detail with reference to FIG. 4. The comparison unit 264 compares the decoded row address signal DRA with an address signal of the first defective cell or an address signal PRA of the second defective cell, and as a result of the comparison, the control signal REN. )

Next, the operation of the repair apparatus 250 according to an embodiment of the present invention configured as described above is as follows.

First, when the address signal of the first defective cell is programmed in the comparator 264, the wafer repair information generator 261 enables the wafer repair signal WRP. At this time, the fuse box 262 is in a disabled state. The controller 263 enables the mode determination signals B1 to Bi in response to the wafer repair signal WRP, and disables the repair enable signal S. FIG. The comparison unit 264 compares the decoded row address signal DRA with an address signal of the first defective cell in response to the mode determination signals Bi to Bi and the repair enable signal S. The control signal REN is output as a result of the comparison. The comparator 264 enables the control signal REN when the decoded row address signal DRA and the address signal of the first defective cell are the same, and decodes the control signal REN when they are different. Enable it.

When the control signal REN is enabled, the redundancy row decoder 252 is enabled and the normal row decoder 220 is disabled. The redundancy row decoder 252 selects and activates a word line of the redundancy memory cell array 251. As a result, the word line including the defective cell of the main memory cell array 210 is replaced with the word line of the redundancy memory cell array 251.

In addition, when the control signal REN is disabled, the redundancy row decoder 252 is disabled and the normal row decoder 220 is enabled. As a result, the main memory cell array 110 operates normally.

On the other hand, when the address signal of the first defective cell is not programmed in the comparator 264, the wafer repair information generator 261 disables the wafer repair signal WRP. At this time, an address signal PRA of the second defective cell is programmed in the fuse box 262 in advance. The fuse box 262 maintains an enabled state during the repair operation of the repair apparatus 250 and outputs an address signal PRA of the second defective cell. The controller 263 partially enables the mode determination signals B1 to Bi in response to the address signal PRA and the wafer repair signal WRP of the second defective cell, and enables the repair. Disable signal S. The comparator 264 is configured to program the address signal PRA of the second defective cell in response to the mode determination signals Bi to Bi and the repair enable signal S. FIG. The comparison unit 264 compares the decoded row address signal DRA with the address signal PRA of the second defective cell, and outputs the control signal REN as a result of the comparison. The subsequent operation is the same as that described above, and thus will be omitted.

Next, a configuration and detailed operation of the comparison unit 264 will be described with reference to FIG. 4. 4 is a circuit diagram illustrating in detail the comparison unit 264 shown in FIG. 3.

As shown in FIG. 4, the comparison unit 264 includes an address comparison circuit 270 and a logic circuit 280. The address comparison circuit 270 includes a plurality of transistors T1 to T29 and a plurality of fuses F1 to F24. The plurality of fuses F to F24 may be implemented as a laser fuse cut by a laser beam or an electrical fuse cut electrically. The transistors T1 to T24 are turned on or turned off in response to the mode determination signals B1 to B24. The transistors T25 to T29 are turned on or turned off in response to the repair enable signal S. In FIG. 4, the address comparison circuit 270 includes the transistors T1 to T29 and the fuses F1 to F24 as an example. However, the address comparison circuit 270 may be further configured as necessary. It may further include transistors and fuses. At this time, the address comparison circuit 270 further receives the same number of mode determination signals as the number of fuses to be added. The address comparison circuit 270 further receives an additional decoded address signal DRA.

Drains of the transistors T1 to T8 are connected to the node ND1, and sources are connected to the node ND2 through the fuses F1 to F8. In addition, the mode determination signals B1 to B8 are input to gates of the transistors T1 to T8. The transistors T1 to T8 are turned on or turned off in response to the mode determination signals B1 to B8. The fuses F1 to F8 are selectively cut in advance so as to indicate an address signal of the first defective cell. In this case, all of the mode determination signals B1 to B8 are enabled.

In addition, when all of the fuses F1 to F8 are not blown, the transistors in response to the mode determination signals B1 to B8 which are partially enabled in response to the address signal of the second defective cell. Some of T1 to T8) are turned on. As a result, the same effect as that in which the address signal of the second defective cell is programmed in the transistors T1 to T8 and the fuses F1 to F8 is obtained.

The transistors T1 to T8 are connected to the node ND2 when the decoded row address signal DRA234 received through the node ND1 matches the address signal of the first or second defective cell. Outputs the high level internal signal FRA234. Also, when the decoded row address signal DRA234 does not match the address signal of the first or second defective cell, the transistors T1 to T8 output the low level internal signal FRA234. .

Drains of the transistors T9 to T12 are connected to the node ND3, and sources are connected to the node ND4 through the fuses F9 to F12. In addition, the mode determination signals B9 to B12 are input to gates of the transistors T9 to T12. The transistors T9 to T12 are turned on or turned off in response to the mode determination signals B9 to B12. The fuses F9 to F12 are selectively cut in advance so as to indicate an address signal of the first defective cell. In this case, all of the mode determination signals B9 to B12 are enabled.

In addition, when all of the fuses F9 to F12 are not blown, the transistors in response to the mode determination signals B9 to B12 that are partially enabled in response to the address signal of the second defective cell. Some of T9 to T12) are turned on. As a result, the same effect as that in which the address signal of the second defective cell is programmed in the transistors T9 to T12 and the fuses F9 to F12 is obtained.

The transistors T9 to T12 are connected to the node ND4 when the decoded row address signal DRA56 received through the node ND3 matches an address signal of the first or second defective cell. Outputs the high level internal signal FRA56. When the decoded row address signal DRA56 does not match the address signal of the first or second defective cell, the transistors T9 to T12 output the low level internal signal FRA56. .

Drains of the transistors T13 to T16 are connected to the node ND5, and sources are connected to the node ND6 through the fuses F13 to F16. In addition, the mode determination signals B13 to B16 are input to gates of the transistors T13 to T16. The transistors T13 to T16 are turned on or turned off in response to the mode determination signals B13 to B16. The fuses F13 to F16 are selectively cut in advance so as to indicate an address signal of the first defective cell. In this case, all of the mode determination signals B13 to B16 are enabled.

In addition, when all of the fuses F13 to F16 are not blown, the transistors in response to the mode determination signals B13 to B16 that are partially enabled in response to the address signal of the second defective cell. Some of T13 to T16) are turned on. As a result, the same effect as that in which the address signal of the second defective cell is programmed in the transistors T13 to T16 and the fuses F13 to F16 is obtained.

The transistors T13 to T16 are connected to the node ND6 when the decoded row address signal DRA78 received through the node ND5 matches the address signal of the first or second defective cell. Outputs the high level internal signal FRA78. Also, when the decoded row address signal DRA78 does not match the address signal of the first or second defective cell, the transistors T13 to T16 output the low level internal signal FRA78. .

Drains of the transistors T17 to T20 are connected to the node ND7, and sources are connected to the node ND8 through the fuses F17 to F20. In addition, the mode determination signals B17 to B20 are input to the gates of the transistors T17 to T20. The transistors T17 to T20 are turned on or turned off in response to the mode determination signals B17 to B20. The fuses F17 to F20 are selectively cut in advance so as to indicate an address signal of the first defective cell. In this case, all of the mode determination signals B17 to B20 are enabled.

In addition, when all of the fuses F17 to F20 are not blown, the transistors in response to the mode determination signals B17 to B20 that are partially enabled in response to the address signal of the second defective cell. Some of T17-T20) turn on. As a result, the same effect as that in which the address signal of the second defective cell is programmed in the transistors T17 to T20 and the fuses F17 to F20 is obtained.

The transistors T17 to T20 are connected to the node ND8 when the decoded row address signal DRA910 received through the node ND7 matches the address signal of the first or second defective cell. The high level internal signal FRA910 is output. Also, when the decoded row address signal DRA910 does not match the address signal of the first or second defective cell, the transistors T17 to T20 output the low level internal signal FRA910. .

Drains of the transistors T21 to T24 are connected to a node ND9, and sources are connected to the node ND10 through the fuses F21 to F24. In addition, the mode determination signals B21 to B24 are input to gates of the transistors T21 to T24. The transistors T21 to T24 are turned on or turned off in response to the mode determination signals B21 to B24. The fuses F21 to F24 are selectively cut in advance so as to indicate an address signal of the first defective cell. In this case, all of the mode determination signals B21 to B24 are enabled.

In addition, when all of the fuses F21 to F24 are not blown, the transistors in response to the mode determination signals B21 to B24 that are partially enabled in response to the address signal of the second defective cell. Some of T21 to T24) are turned on. As a result, the same effect as that in which the address signal of the second defective cell is programmed in the transistors T21 to T24 and the fuses F21 to F24 is obtained.

The transistors T21 to T24 are connected to the node ND10 when the decoded row address signal DRA1112 received through the node ND9 matches the address signal of the first or second defective cell. Output the high level internal signal FRA1112. Further, when the decoded row address signal DRA1112 does not match the address signal of the first or second defective cell, the transistors T21 to T24 output the low level internal signal FRA1112. .

In addition, drains of the transistors T25 to T29 are connected to the nodes ND2, ND4, ND6, ND8, and ND10, and sources are connected to a ground voltage. The repair enable signal S is input to the gates of the transistors T25 to T29. The transistors T25 to T29 are turned on or turned off in response to the repair enable signal S. The repair enable signal S is disabled when the repair device 250 performs a repair operation, and is enabled when the repair device 250 does not perform a repair operation. In addition, when the repair enable signal S is enabled, the mode determination signals B1 to B24 are all disabled.

In addition, the logic circuit 280 outputs the control signal REN in response to the internal signals FRA234, FRA56, FRA78, FRA910, and FRA1112. The logic circuit 280 may be implemented with NAND gates 281 and 282 and a NOR gate 283. The NAND gate 281 logically operates the internal signals FRA234, FRA56, and FRA78 and outputs the result. The NAND gate 282 logically operates the internal signals FRA910 and FRA1112 and outputs the result. The NOR gate 283 outputs the control signal REN in response to the output signals of the NAND gates 281 and 282. In addition, when the address comparison circuit 270 further includes additional transistors and fuses, the logic circuit 280 may further include additional NAND gates and NOR gates.

The operation of the comparator 264 configured as described above is as follows.

First, the case where the address signal of the first defective cell is programmed in the fuses F1 to F24 of the address comparison circuit 270 will be described. In this case, all of the mode determination signals B1 to B24 are enabled, and the repair enable signal S is disabled.

For example, for the address signal of the first defective cell that is DRA234 <000>, DRA56 <01>, DRA78 <01>, DRA910 <10>, and DRA1112 <10>, the fuses F1 to F24 are next. Is cut as follows.

First, since the DRA234 is <000>, the fuses F2 to F8 except the fuse F1 are cut. In addition, since the DRA56 is the fuses F9, F11, and F12 except the fuse F10, the fuses F9, F11, and F12 are cut. Next, since the DRA78 is a fuse (F13, F15, F16) other than the fuse (F14) is cut. In addition, since the DRA910 is <10>, the fuses F17, F18, and F20 except the fuse F19 are cut. In addition, since the DRA1112 is <10>, the fuses F21, F22, and F24 except the fuse F23 are cut. Since all of the mode determination signals B1 to B24 are enabled, all of the transistors T1 to T24 are turned on. When the input decoded address signals DRA234, DRA56, DRA78, DRA910, and DRA1112 are the same as the address signal of the first defective cell, the transistors T1, T10, T14, T19, and T23 have a high level. The internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 are output. Further, when the decoded address signals DRA234, DRA56, DRA78, DRA910, and DRA1112 that are input are not the same as the address signal of the first defective cell, the transistors T1, T10, T14, T19, and T23. Outputs the internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 at a low level.

The logic circuit 280 enables the control signal REN in response to the internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 at a high level. In addition, the logic circuit 280 disables the control signal REN in response to the internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 at a low level.

Next, the case where the address signals of the first defective cells are not programmed in the fuses F1 to F24, that is, the fuses F1 to F24 are not all cut off. In this case, the mode determination signals B1 to B24 cause the address signal of the second defective cell programmed in the fuse box (see 262 in FIG. 3) to be the same as that programmed in the address comparison circuit 270. do. At this time, only some of the mode determination signals B1 to B24 are enabled, and the repair enable signal S is disabled. In more detail, for example, for the address signals of the second defective cells DRA234 <000>, DRA56 <01>, DRA78 <01>, DRA910 <10>, and DRA1112 <10>, the control unit (FIG. 3, reference 263) enables the mode determination signals B1, B10, B14, B19, and B23, and the remaining mode determination signals B2 to B9, B11 to B13, B15 to B18, B21, B22, and B24. Disable).

The transistors T1, T10, T14, T19, and T23 are turned on in response to the mode determination signals B1, B10, B14, B19, and B23. In addition, the transistors T2 to T9, T11 to T13, T15 to T18, T21, T22, and T24 in response to mode decision signals B2 to B9, B11 to B13, B15 to B18, B21, B22, and B24. Is turned off. As a result, the same effect as that in which the address signal of the second defective cell is programmed in the address comparison circuit 270 is obtained.

When the input decoded address signals DRA234, DRA56, DRA78, DRA910, and DRA1112 are the same as the address signal of the second defective cell, the transistors T1, T10, T14, T19, and T23 are at a high level. The internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 are output. Further, when the decoded address signals DRA234, DRA56, DRA78, DRA910, and DRA1112 that are input are not the same as the address signal of the second defective cell, the transistors T1, T10, T14, T19, and T23. Outputs the internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 at a low level.

The logic circuit 280 enables the control signal REN in response to the internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 at a high level. In addition, the logic circuit 280 disables the control signal REN in response to the internal signals FRA234, FRA56, FRA78, and FRA910 FRA1112 at a low level.

In FIGS. 3 and 4, the repair apparatus according to an embodiment of the present invention has been described for repairing a low line including a defective cell of the main memory cell array, but the repair apparatus is a defect of the main memory cell array. It may be implemented to repair a column line containing a cell.

As described above, in the repair control circuit of the repair apparatus according to the present invention, an address signal of a defective cell detected in a wafer state test process may be programmed or an address signal of a defective cell detected in a post package test process may be programmed. . That is, the repair apparatus may repair a defect cell detected in a wafer process test or repair a defect cell detected in a post package test process.

In addition, since the repair apparatus according to the present invention includes a single redundant memory cell array that is not separated, the number of redundant memory cells capable of repairing defective cells while occupying a small area in the semiconductor memory device may be increased.

In addition, since the repair apparatus according to the present invention selectively repairs the defective cells detected in the wafer state test process or the defective cells detected in the post package test process, the paths of the signals for the repair operation are the same. Therefore, the repair apparatus according to the present invention does not need any separate timing control.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the repair apparatus and the repair method according to the present invention have the effect of repairing the defective cells detected in the wafer state test process or the defective cells detected in the post package test process.

In addition, since the repair apparatus and the repair method according to the present invention use a single redundant memory cell array that is not separated, it is possible to repair a relatively large number of defective cells while occupying a small area in the semiconductor memory device. .

1 is a diagram illustrating a semiconductor memory device including a repair device according to the prior art.

FIG. 2 is a circuit diagram illustrating in detail the first comparator shown in FIG. 1.

3 is a diagram illustrating a semiconductor memory device including a repair device selectively programmable in a wafer test and a post package test according to an embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating in detail the comparison unit illustrated in FIG. 3.

Claims (15)

A main memory cell array including a plurality of main memory cells, a predecoder for first decoding an external address signal and a second decoding of the first decoded address signal, and selecting and activating some of the plurality of main memory cells In a repair apparatus for a semiconductor memory device comprising a normal decoder to Any one of an address signal (hereinafter referred to as a first address signal) of the first defective cell detected in the wafer test process and an address signal (hereinafter referred to as a second address signal) of the second defective cell detected in the post package test process A repair control circuit for programming one and outputting a predetermined control signal in response to the first decoded address signal; A redundancy memory cell array comprising a plurality of redundancy memory cells, the redundancy memory cell repairing any one of the first defective cell and the second defective cell of the main memory cell array when activated; And A redundancy decoder that is enabled or disabled in response to the control signal and activates some of the redundancy memory cells when enabled; And when the redundancy decoder is enabled, the normal decoder is disabled in response to the control signal. According to claim 1, wherein the repair control circuit, A wafer repair information generator for outputting a wafer repair signal indicating whether the programmed first address signal exists; A fuse box including a plurality of first fuses, a part of the plurality of first fuses being cut by an external program control signal to program the second address signal, and outputting the programmed second address signal; A controller configured to output a plurality of mode determination signals and a repair enable signal in response to the wafer repair signal and the second address signal; And In response to the plurality of mode determination signals and the repair enable signal, one of the first address signal and the second address signal is determined as a comparison reference address signal, and the first decoded address signal is compared with the comparison enable signal. A comparison section for comparing with a reference address signal and outputting the control signal as a result of the comparison; And the fuse box is disabled when the programmed first address signal is present and does not output the second address signal. The method of claim 2, The wafer repair information generator may enable the wafer repair signal when the programmed first address signal exists, and disable the wafer repair signal when the programmed first address signal does not exist. The controller enables all of the plurality of mode determination signals when the wafer repair signal is enabled, and the plurality of mode determination signals in response to the second address signal received from the fuse box when the wafer repair signal is disabled. A repair device of a semiconductor memory device, characterized in that enabling some of the mode determination signals. The method of claim 3, wherein the comparison unit, An address comparison circuit that outputs a plurality of internal signals when the first decoded address signal is the same as the comparison reference address signal; And And a logic circuit configured to output the control signal in response to the plurality of internal signals. The method of claim 4, wherein the address comparison circuit, A plurality of second fuses connected in parallel to each other; A plurality of first switching circuits connected in series between an input of each of the plurality of second fuses and an output of the predecoder; And And a plurality of second switching circuits connected in series between an output and a ground voltage of each of the plurality of second fuses. The method of claim 5, The plurality of first switching circuits are turned on or off in response to the plurality of mode determination signals, The plurality of second switching circuits are turned on or off in response to the repair enable signal, The second switching circuits are all turned off when some or all of the first switching circuits are turned on. The method of claim 6, Some of the plurality of second fuses are disconnected when the plurality of mode determination signals are all enabled, and when the some of the plurality of mode determination signals are enabled, the plurality of second fuses are all A repair apparatus for a semiconductor memory device, which is in a non-cut state. The method of claim 1, And the first address signal and the second address signal are row address signals. The method of claim 1, And the first address signal and the second address signal are column address signals. The semiconductor memory device comprising the repair device of claim 1. Any one of an address signal (hereinafter referred to as a first address signal) of the first defective cell detected in the wafer test process and an address signal (hereinafter referred to as a second address signal) of the second defective cell detected in the post package test process A repair control circuit for programming one and outputting a predetermined control signal in response to the decoded address signal received from the predecoder, a redundant memory cell array including a plurality of redundant memory cells, and in response to the control signal; A repair method of a repair apparatus including a redundancy decoder to activate some of the redundancy memory cells, (a) determining whether an address signal programmed in the repair control circuit is the first address signal; (b) when the first address signal is programmed in step (a), comparing the decoded address signal with the first address signal and outputting the control signal as a result of the comparison; (c) comparing the decoded address signal with the second address signal when the first address signal is not programmed in step (a), and outputting the control signal as a result of the comparison; And (d) when the control signal is enabled, the redundancy decoder is enabled to activate some of the plurality of redundancy memory cells. The method of claim 11, wherein step (b) comprises: (b1) enabling all of the plurality of mode determination signals; (b2) determining the first address signal as a comparison reference address signal of the decoded address signal in response to the plurality of mode determination signals; (b3) comparing the first address signal with the decoded address signal; And and (b4) enabling the control signal when the first address signal and the decoded address signal are the same in step (b3). The method of claim 11, wherein step (c) comprises: (c1) enabling some of the plurality of mode determination signals in response to the second address signal; (c2) determining the second address signal as a comparison reference address signal of the decoded address signal in response to the plurality of mode determination signals; (c3) comparing the second address signal with the decoded address signal; And and (c4) enabling the control signal when the second address signal and the decoded address signal are the same in step (c3). The method of claim 11, And the first address signal and the second address signal are row address signals. The method of claim 11, And the first address signal and the second address signal are column address signals.