KR20050018424A - A thin film transistor array panel and a method for manufacturing the same - Google Patents

Abstract

PURPOSE: A TFT(thin film transistor) array substrate is provided to obtain a data interconnection of low resistance and stably form a contact hole by making the data interconnection formed of a dual metal layer structure composed of an upper metal layer and a lower metal layer and by forming a resistive contact layer and a semiconductor layer under the data interconnection. CONSTITUTION: A gate interconnection including a gate line and a gate electrode is formed on an insulation substrate. The gate interconnection is covered with a gate insulation layer. A data interconnection(171) has a lower layer(701) and an upper layer(702) formed on the lower layer, including a semiconductor layer pattern(152), a data line formed on the semiconductor layer pattern, a source electrode(173) and a drain electrode. A pixel electrode is connected to the lower layer of the drain electrode. A photolithography process is performed to make the upper layer have a contact hole that connects the data line and the source/drain electrode and connects the drain electrode and the pixel electrode. A photoresist layer pattern for forming the semiconductor layer pattern is formed. The lower layer is etched. The semiconductor layer is etched.

Description

 A thin film transistor array substrate and a method of manufacturing the same {A THIN FILM TRANSISTOR ARRAY PANEL AND A METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate and a method of manufacturing the same, and more particularly, to a thin film transistor array substrate having a data wiring having a double metal layer structure of an upper metal layer and a lower metal layer, and an ohmic contact layer and a semiconductor layer thereunder. It relates to a manufacturing method.

 The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In such a liquid crystal display, in order to prevent signal delay, a data line for transmitting an image signal generally uses a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of forming the pixel electrode using indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, aluminum or aluminum at a contact portion where a drain electrode of aluminum or an aluminum alloy and a pixel electrode of ITO or IZO contact The wiring of the alloy may be corroded or the contact resistance of the contacts may be problematic. In addition, in the case where the data wiring connected to the semiconductor layer made of silicon is formed of aluminum or an aluminum alloy, aluminum may be diffused into the semiconductor layer to damage the wiring. Therefore, it is preferable to remove the aluminum layer or the aluminum alloy layer from the contact portion through the ITO or IZO or another metal having excellent contact characteristics with the semiconductor layer.

However, in the process of laminating the semiconductor layer and the metal layer and then etching, when the line width of the semiconductor layer is relatively large with respect to the metal layer, screen shaking may occur on the panel during light projection from the backlight. . However, when the photoresist pattern is formed such that the line width of the semiconductor layer has a line width substantially the same as that of the metal layer, the metal layer may be etched during the etching of the semiconductor layer, thereby increasing wiring resistance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate having a low resistance on data wirings while preventing screen shaking, and a method of manufacturing the same.

The above object is to form a gate wiring including a gate line and a gate electrode on an insulating substrate according to the present invention, forming a gate insulating film covering the gate wiring, a semiconductor layer pattern and the semiconductor layer pattern Forming a data line including a data line, a source electrode, and a drain electrode on the upper layer, the data line including a lower layer and an upper layer on the lower layer; and forming a pixel electrode connected to the lower layer of the drain electrode. In the method of manufacturing a thin film transistor array substrate, the forming of the semiconductor layer pattern and the data line may include contacting the upper layer to connect the data line, the source and drain electrodes, the drain electrode, and the pixel electrode by a photolithography process. And having a hole therein, and a photoresist pattern for forming the semiconductor layer pattern. The method may include forming a thin film, etching the lower layer, and etching the semiconductor layer.

The forming of the semiconductor layer pattern and the data wiring may further include removing the photoresist layer covering a portion where the channel portion is to be formed, and removing the lower layer exposed to the channel. The method may further include forming an ohmic contact layer doped with an impurity between the semiconductor layer pattern and the lower layer, removing the photoresist pattern, and removing the ohmic contact layer.

The photoresist pattern may include a photoresist pattern for the first semiconductor pattern covering the end portion of the data line and the contact hole and a photoresist pattern for the second semiconductor pattern using a slit mask at a portion where the channel portion is to be formed. The forming of the semiconductor layer pattern and the data line may further include removing the lower layer by being exposed to the channel covering the portion where the channel portion is to be formed after the etching of the lower layer.

In the method of manufacturing the thin film transistor array substrate, it is preferable that the line width of the semiconductor layer under the data line has a difference value within a predetermined allowable range from the line width of the upper layer of the data line. The lower layer may be formed of a barrier metal, and the upper layer may be formed of aluminum or an aluminum alloy.

In addition, the above object is formed on an insulating substrate according to the present invention, a gate wiring having a gate line and a gate electrode, a gate insulating film covering the gate wiring, a semiconductor layer pattern formed on the gate insulating film, and A data line formed on the semiconductor layer pattern and having a lower layer formed of a barrier metal and an upper layer positioned on the lower layer, the data line intersecting the gate line and the lower layer formed by a pattern similar to the semiconductor layer pattern; A data line including a source electrode and a drain electrode, a passivation layer covering the semiconductor layer pattern, and a pixel electrode connected to the drain electrode in contact with the lower layer on the exposed lower layer of the drain electrode. By a thin film transistor array substrate Can be achieved.

The thin film transistor array substrate may further include an ohmic contact layer doped with an impurity between the semiconductor layer pattern and the data line, and the line width of the semiconductor layer below the data line is equal to that of the upper layer of the data line. It is preferable to be in a predetermined allowable range from the line width.

Then, with reference to the accompanying drawings with respect to the contact structure of the wiring according to an embodiment of the present invention, a method for manufacturing the same, and a thin film transistor array substrate including the same and a method for manufacturing the same having a common knowledge in the art to which the present invention belongs. It will be described in detail so that it can be easily performed. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a thin film transistor array substrate for wiring according to an embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

Next, a thin film transistor array substrate and a manufacturing method according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate shown in FIG. 1 taken along the line II-II '.

A gate wiring including a conductive film made of silver or a silver alloy having a low resistance or a metal material of aluminum or an aluminum alloy is formed on the insulating substrate 110. The gate line is connected to the gate line 121 and the gate line 121 which extend in the horizontal direction, and the gate line end portion 125 and the gate line 121 which receive a gate signal from the outside and transfer the gate signal to the gate line. It includes a gate electrode 123 of the thin film transistor connected to. The gate line 121 overlaps the conductor pattern 177 for the storage capacitor connected to the pixel electrode 190 to be described later to form a storage capacitor that improves the charge storage capability of the pixel. When the storage capacitor is insufficient, the gate The storage electrode may be added to be parallel to the line 121 and receive a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside.

On the substrate 110, a gate insulating layer 140 made of silicon nitride (SiNx) covers the gate lines 121, 125, and 123.

Semiconductor layer patterns 152 and 157 made of a semiconductor such as amorphous silicon are formed on the gate insulating layer 140 of the gate electrode 125, and silicide or n-type impurities are formed on the semiconductor layer patterns 152 and 157. Resistive contact layers 163, 165 and 167 made of a material such as highly doped n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 163, 165, and 167, a bottom layer made of a barrier metal such as molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), titanium (Ti), or the like A data line is formed that includes 701 and an upper film 702 made of low resistance aluminum (Al) or aluminum alloy (Al alloy). The data line is formed in the vertical direction and crosses the gate line 121 to define a pixel, which is a branch of the data line 171 and the data line 171 and extends to the upper portion of the ohmic contact layer 163. ), Which is connected to one end of the data line 171 and is separated from the data line end portion 179 and the source electrode 173 to which an image signal from the outside is applied, and the source electrode 173 with respect to the gate electrode 123. And a drain electrode 175 formed on the opposite ohmic contact layer 165. The data line also includes a conductor pattern 177 for a storage capacitor that overlaps the gate line 121.

At this time, the upper layer 702 made of aluminum or an aluminum alloy among the data wires 171, 173, 175, 177, and 179 has a contact portion, that is, a conductor pattern 177 for a storage capacitor, a drain electrode 175, and an end of the data wire. Some of the portions 179 have been removed, and the contacts where the top layer 702 has been removed have good contact properties with other materials, and aluminum or aluminum alloy diffuses into the silicon layers 150, 157, 163, 165, and 167. A lower layer 701 made of a barrier metal is exposed to prevent the barrier layer 701 from being exposed, and a boundary line of the upper layer 702 is positioned above the lower layer 701.

The contact layer patterns 163, 165, and 167 lower the contact resistance between the semiconductor layer patterns 152 and 157 below and the data lines 171, 177, 173, 175, and 179 above the data. It has the same shape as the wirings 171, 177, 173, 175, and 179. That is, the data line part intermediate layer pattern 163 is the same as the data line parts 171, 179, and 173, the drain electrode intermediate layer pattern 165 is the same as the drain electrode 175, and the storage capacitor intermediate layer pattern 167 is formed. It is the same as the conductor pattern 177 for holding capacitors.

The semiconductor layer patterns 152 and 157 may include the data wires 171, 177, 173, 175, and 179 except for the thin film transistor unit in which the gate electrode 123, the drain electrode 175, and the source electrode 173 are located. It has the same shape as the ohmic contact layer patterns 163, 165, and 167. Specifically, the semiconductor capacitor pattern 157 for the storage capacitor, the conductor pattern 177 for the storage capacitor, and the contact layer pattern 167 for the storage capacitor have the same shape, but the semiconductor layer pattern 152 for the thin film transistor has a data wiring. And slightly different from the rest of the contact layer pattern. That is, in the thin film transistor unit, the data line units 171, 179, and 173, in particular, the source electrode 173 and the drain electrode 175 are separated, and the data line intermediate layer 163 and the contact layer pattern 165 for the drain electrode are also separated. However, the semiconductor layer pattern 152 for thin film transistors is connected here without being disconnected.

 On top of the data lines 171, 173, 177, 175, and 179 and the semiconductor layers 152 and 157 that are not covered by these materials, organic materials having excellent planarization characteristics, or coating or plasma enhanced chemical vapor deposition (PECVD) A protective film 180 formed of silicon nitride or a low dielectric constant insulating material including a-Si: C: O film or an a-Si: O: F film and the like is formed.

In the passivation layer 180, contact holes 185, 187, and 189 are formed to expose the drain electrode 175 as a contact portion, the conductor pattern 177 for the storage capacitor, and the lower layer 701 of the data line end portion 179, respectively. The contact hole 182 exposing the gate wiring end portion 125 is formed together with the gate insulating layer 140.

A pixel electrode 190 is formed on the passivation layer 180 to receive an image signal from the thin film transistor and generate an electric field together with the electrode of the upper plate. The pixel electrode 190 is made of a transparent conductive material such as IZO or ITO, and is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive an image signal. The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap. The pixel electrode 190 is also connected to the conductive capacitor conductor pattern 177 through the contact hole 187 to transmit an image signal to the conductive capacitor conductor pattern 177. On the other hand, the auxiliary gate pad 92 and the auxiliary data pad 97 are formed on the gate wiring end 125 and the data wiring end 179 through the contact holes 182 and 189, respectively. These are not essential to complement the adhesion between the wiring ends 125 and 179 and the external circuit device and to protect the pads, and their application is optional.

Herein, although the transparent IZO or ITO is mentioned as an example of the material of the pixel electrode 190, the transparent electrode may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.

Next, a method of manufacturing the TFT array substrate for a liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, a single film of aluminum or an aluminum alloy, which is a low resistance conductive material, or a multilayer film including the same, is stacked on the glass substrate 110, and patterned by a photolithography process using a mask. Thus, the gate wiring including the gate line 121, the gate electrode 123, and the gate wiring end portion 125 is formed in a tapered structure.

Next, as shown in FIG. 4, three-layer films of the gate insulating film 140 made of silicon nitride, the semiconductor layer 150 made of amorphous silicon, and the doped amorphous silicon layer 160 are sequentially stacked. Here, the gate insulating film 140 is preferably formed by stacking silicon nitride to a thickness of about 2,000 to 5,000 Pa at a temperature range of 250 to 400 ° C.

Next, the molybdenum or molybdenum alloy or chromium among the barrier metals having excellent contact properties with other materials such as ITO or IZO, while preventing the diffusion of other materials into the semiconductor layer 150 or the doped amorphous silicon layer 160 thereon. The lower layer 701 having a thickness of about 500 GPa, and the upper layer 702 at about 150 GPa by using a target of Al-Nd alloy containing 2 at% Nd of aluminum or aluminum alloy having low resistance. Laminate by sputtering in order to a thickness of about 2,500Å.

Next, as shown in FIGS. 5A and 5B, the upper layer 702 is patterned by a photolithography process using a data wiring mask. A data line 171 crossing the gate line 121, a source electrode 173 connected to the data line 171 and extending to an upper portion of the gate electrode 123, and one end of the data line 171. A data wiring end 179, a drain electrode 175 which is separated from the source electrode 179, and faces the source electrode 173 around the gate electrode 123, and the drain electrode 175 and the pixel electrode. The lower layer 701 is exposed by forming a pattern of a data line including a contact hole to connect the interconnection and a conductor pattern 177 for a storage capacitor.

Next, as shown in FIGS. 6A and 6B, the photoresist for the semiconductor layer patterns 150, 152, and 157 is patterned. The lower layer 701 is etched using the pattern of the photoresist layer as a mask, but since the pattern of the photoresist layer covers the channel, the lower layer 701 located in the channel is not etched. The exposed doped amorphous silicon layer 160 and the semiconductor layer 150 are etched to complete the semiconductor layer patterns 152 and 157 and leave the doped amorphous silicon layer 160 thereon.

As illustrated in FIG. 7, the photoresist pattern 210 may be partially formed on the drain electrode and the channel where the end portion and the contact portion of the data line are to be formed. In addition, it is preferable to use a slit mask for the portion where the channel is to be formed and to adjust the lower layer etching process conditions to omit the process of removing the photoresist layer during the etching of the lower layer located in the channel in a later process.

In the next process, as shown in FIG. 8, the photoresist layer covering the channel is removed, and the lower layer positioned in the channel and the doped amorphous silicon layer pattern 160 are etched to separate the gate electrode 123 from both sides. The semiconductor layer pattern 152 between the doped amorphous silicon layers 163 and 165 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer pattern 152, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 9A and 9B, an organic material having excellent planarization characteristics and photosensitivity may be coated on top of the substrate 110 or a-Si may be formed by a plasma enhanced chemical vapor deposition (PECVD) method. A low dielectric constant CVD film, such as a C: O film or an a-Si: O: F film, is deposited to form a passivation layer 180, and is patterned by dry etching together with the gate insulating layer 140 by a photolithography process using a mask to form a drain electrode. 175, contact holes 182, 185, 187, and 189 exposing the lower layer 701 of the conductive pattern 177 for organic capacitors, respectively, are formed.

Next, as shown in FIGS. 1 and 2, the IZO or ITO film is laminated by sputtering and patterned using a mask to perform drain electrode 175 and through contact holes 185 and 187. The lower portion of the gate wiring end 125 and the data wiring end 179 through the pixel electrode 190 and the contact holes 182 and 189 connected to the lower layer 701 of the conductive capacitor pattern 177 for the storage capacitor. The auxiliary gate pad 92 and the auxiliary data pad 97 respectively connected to the film 701 are formed. In the exemplary embodiment of the present invention, a target for forming the IZO films 190, 92, and 97 is a product called indium x-metal oxide (IDIXO) manufactured by Imitsu, and the target includes In 2 O 3 and ZnO. In addition, the content of Zn in In + Zn is preferably in the range of 15-20 at%. In addition, in order to minimize contact resistance, the IZO film is preferably laminated in a range of 250 kPa or less.

The structure of the thin film transistor array substrate according to the exemplary embodiment of the present invention may include a conductive film of aluminum or aluminum alloy in which the gate lines 121, 125, 123 and the data lines 171, 173, 175, 177, and 179 have low resistance. At the same time, the metal layer of the data line, the lower semiconductor layer, and the ohmic contact layer have a line width difference within a predetermined allowable range. In this case, the predetermined allowable range will mean the same line width having the same minute difference as that of forming the pattern through the same mask. Through such a structure, the resistance state of the data line can be kept low and the screen shake can be prevented.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. Fall within the scope of the

According to the present invention, screen shaking can be prevented, data wiring with low resistance can be obtained, and contact holes can be formed stably.

1 is a thin film transistor array substrate for a liquid crystal display according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line II-II. FIG.

3A, 5A, 6A, and 9A are layout views of a thin film transistor array substrate in which an intermediate process of manufacturing a thin film transistor array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention is performed according to a process sequence thereof.

4 is a cross-sectional view of successively stacking three-layer films of a gate insulating film, a semiconductor layer, and a doped amorphous silicon layer according to an embodiment of the present invention;

FIG. 3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 3A;

FIG. 5B is a cross-sectional view taken along the line IVb-IVb 'in FIG. 5A and is a cross-sectional view showing the next step of FIG. 3B;

FIG. 6B is a cross-sectional view taken along the line Vb-Vb 'in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

7 illustrates a photoresist pattern for forming a semiconductor layer pattern according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along the line Vb-Vb 'of FIG. 6a and is a cross-sectional view showing the next step of FIG. 6b;

FIG. 9B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 9A, and is a cross-sectional view showing the next step in FIG. 8.

Claims (11)

Forming a gate wiring including a gate line and a gate electrode on the insulating substrate; Forming a gate insulating film covering the gate wiring; Forming a data line including a data layer, a source electrode, and a drain electrode on the semiconductor layer pattern and the semiconductor layer pattern, the data line having a lower layer and an upper layer on the lower layer; A method of manufacturing a thin film transistor array substrate comprising forming a pixel electrode connected to the lower layer of the drain electrode. Forming the semiconductor layer pattern and the data wiring, The upper layer has a contact hole connecting the data line, the source and drain electrodes, the drain electrode and the pixel electrode in a photolithography process; Forming a photoresist pattern for forming the semiconductor layer pattern; Etching the lower layer; And etching the semiconductor layer. The method of claim 1, Forming the semiconductor layer pattern and the data wiring, Removing the photosensitive film covering a portion where a channel portion is to be formed; And removing the lower layer exposed to the channel. The method according to claim 1 or 2, And forming an ohmic contact layer doped with impurities between the semiconductor layer pattern and the lower layer. The method of claim 3, Forming the semiconductor layer pattern and the data wiring, And removing the photoresist pattern and removing the ohmic contact layer. The method of claim 1, The photoresist pattern may include a photoresist pattern for the first semiconductor pattern covering the end portion of the data line and the contact hole and a photoresist pattern for the second semiconductor pattern using a slit mask at a portion where the channel portion is to be formed. Method of manufacturing a substrate. The method of claim 5, Forming the semiconductor layer pattern and the data wiring, And removing the lower layer by being exposed to the channel covering the portion where the channel unit is to be formed after the etching of the lower layer. The method of claim 1, And a line width of the semiconductor layer below the data line has a difference value within a predetermined allowable range from a line width of the upper layer of the data line. The method of claim 1, And the lower layer is formed of a barrier metal and the upper layer is formed of aluminum or an aluminum alloy. A gate wiring formed on an insulating substrate and having a gate line and a gate electrode; A gate insulating film covering the gate wiring; A semiconductor layer pattern formed on the gate insulating film; A data line formed on the semiconductor layer pattern and having a lower layer formed of a barrier metal and an upper layer positioned on the lower layer, the data line intersecting the gate line and the lower layer formed by a pattern similar to the semiconductor layer pattern; Data wiring including a source electrode and a drain electrode; A protective film covering the semiconductor layer pattern; And a pixel electrode contacting the lower layer on the exposed lower layer of the drain electrode and connected to the drain electrode. The method of claim 9, And a resistive contact layer doped with impurities between the semiconductor layer pattern and the data line. The method of claim 9, And a line width of the semiconductor layer below the data line is within a predetermined allowable range from the line width of the upper layer of the data line.