KR20050015375A - Method of forming a via contact structure using a dual damascene process - Google Patents

Abstract

PURPOSE: A method of forming a via contact structure using a dual damascene process is provided to prevent erroneous application of copper by enlarging process margin required to remove a via protection layer. CONSTITUTION: A lower interconnection(55) is formed on a semiconductor substrate(51). An etch stopping layer(59) and an interlayer dielectric(61) are sequentially formed on the substrate. The interlayer dielectric is formed by using an in-situ process. A preliminary via hole for exposing the etch stopping layer is formed by patterning the interlayer dielectric. A via protection layer for filling the preliminary via hole is formed. The interlayer dielectric is patterned to form a trench region(67) which penetrates an upper portion of the preliminary via hole. The via protection layer, remaining in the preliminary via hole, is removed to expose the etch stopping layer. A final via hole(63a) is formed by dry etching the exposed etching stopping layer to expose the lower interconnection.

Description

Method of forming a via contact structure using a dual damascene process}

TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a via contact structure using a dual damascene process.

Background Art With the high integration of semiconductor devices, the importance of metal wiring processes is increasing as a process for determining performance and reliability of semiconductor devices due to problems such as RC delay and electro-migration (EM). As a solution to this problem, copper wirings and low dielectric films are applied to semiconductor devices, and a damascene process is used to form copper wirings.

In the dual damascene process, vias and trenches are formed, metal materials such as copper are embedded, and chemical-mechanical polishing (CMP) processes are performed to form metal wires and via plugs together. Say fair. At this time, while forming the trench, etch damage may occur in the lower wiring.

The method of preventing the etching damage of the lower wiring is described in US Pat. It has been disclosed.

1A and 1B are cross-sectional views illustrating the dual damascene process disclosed in US Pat. No. 6,461,955.

Referring to FIG. 1A, an etch stop layer 5 is formed on the semiconductor substrate 1 on which the lower wiring 3 is formed. The etch stop film 5 typically comprises a silicon nitride film.

An interlayer insulating layer 7 and an intermetal dielectric layer 9 are formed on the etch stop layer 5. The interlayer insulating film 7 and the intermetallic insulating film 9 may be formed as a single film, as shown in FIG. 1A. In addition, a trench etch stop film (not shown) may be formed between the interlayer insulating film 7 and the intermetallic insulating film 9.

A hard mask layer 11 may be formed on the intermetallic insulating layer 9. The hard mask layer 11 protects the corners of the via holes.

The preliminary via hole 13 exposing the etch stop layer 5 on the lower interconnection 3 is patterned by sequentially patterning the hard mask layer 11, the intermetallic insulating layer 9, and the interlayer insulating layer 5. Form.

After the preliminary via hole 13 is formed, a via protect layer 15 filling the preliminary via hole 13 is formed. The via protective layer 15 is formed of a film having a wet etching selectivity with respect to the interlayer insulating film 5. The via protective layer 15 on the hard mask layer 11 is selectively etched and removed. As a result, the via protection layer 15 remains only inside the preliminary via hole 13.

After forming the via protective layer 15 remaining in the preliminary via hole 13, the hard mask layer 11 and the intermetallic insulating layer 9 are patterned to cross the preliminary via hole 13. The trench region 17 located in the intermetallic insulating film is defined. When the trench etch stop film (not shown) is formed between the interlayer insulating film 7 and the intermetallic insulating film 9, the intermetallic insulating film 9 is exposed to expose an upper surface of the trench etch stop film. Etch it. The via protection layer 15 prevents etch damage of the lower interconnection 3 while the trench region 17 is formed.

Referring to FIG. 1B, the via protection layer 15 remaining in the preliminary via hole 13 is removed by wet etching. In addition, the hard mask layer 11 and the exposed etch stop layer 5 are removed. As a result, the final via hole 13a exposing the lower wiring 3 is formed.

The via protection layer 15 has a high wet etching selectivity with respect to the interlayer insulating film 7. Therefore, the sidewalls of the interlayer insulating film 7 are protected while the via protection layer 15 is removed.

However, an interface between the interlayer insulating layer 7 and the etch stop layer 5 may exhibit a high etching rate. Therefore, when the wet etching is performed for a long time, an undercut 19 may occur at the interface. The undercut 19 may also occur at an interface between the interlayer insulating film 7 and the intermetallic insulating film 9. When the trench etch stop layer is formed, the trench etch stop layer may also occur at an interface between the trench etch stop layer and the interlayer insulating layer 7 or at an interface between the trench etch stop layer and the intermetallic insulating layer 9.

After the final via hole 13a is formed, a barrier metal layer and a copper seed layer are formed, and a copper film is formed.

However, when the undercut 19 is present in the final via hole 13a and the trench region 17, the diffusion preventing metal film and the copper seed film are discontinuously formed, and as a result, the final via hole 13a is formed. And it is difficult to embed copper in the trench region 17.

Meanwhile, if the wet etching is not sufficiently performed to prevent the undercut 19 from occurring, the via protection layer 13 inside the via hole 13 may not be completely removed.

As a result, with conventional methods, it is difficult to ensure sidewall profiles of via holes and trench regions for copper embedding while having sufficient process margins.

An object of the present invention is to provide a method for forming a via contact structure capable of securing sidewall profiles of via holes and trench regions for embedding copper while ensuring sufficient process margin.

In order to achieve the above object, the present invention provides a method for forming a via contact structure using a dual damascene process.

According to one aspect of the present invention, the method includes forming a lower wiring on a semiconductor substrate. An etch stop film and an interlayer insulating film are sequentially formed on the entire surface of the semiconductor substrate having the lower wiring. The interlayer insulating film is formed using an in-situ process. Thereafter, the interlayer insulating layer is patterned to form a preliminary via hole exposing the etch stop layer on the lower interconnection, and a via protection layer filling the preliminary via hole. Thereafter, the interlayer insulating layer is patterned to cross the upper portion of the preliminary via hole, to form a trench region located in the interlayer insulating layer, and to remove the via protection layer remaining in the preliminary via hole to expose the etch stop layer. The exposed etch stop layer is dry etched to form a final via hole exposing the lower wiring.

Preferably, a diffusion barrier layer may be further formed before forming the etch stop layer. The diffusion barrier prevents the metal atoms of the lower wiring from diffusing into the interlayer insulating layer.

The interlayer insulating film may be formed using an ex-situ process, unlike the in-situ process. In this case, however, the etch stop layer is surface treated to form the interlayer insulating layer. The surface treatment may be performed using a plasma gas. The surface treatment reduces the interface etch rate by densifying the interface between the etch stop layer and the interlayer insulating layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 is a process flow chart illustrating a method of forming a via contact structure according to embodiments of the present invention, and FIGS. 3A to 3F illustrate a via contact structure according to embodiments of the present invention. It is sectional drawing for demonstrating the method.

2 and 3A, a lower insulating layer 53 is formed on the semiconductor substrate 51. A lower wiring 55 is formed in the lower insulating film 53 using a conventional damascene technique (step 21 of FIG. 2). The lower wiring 55 may be formed of a copper film or a tungsten film.

An etch stop film 59 and an interlayer insulating film 61 are sequentially formed on the entire surface of the semiconductor substrate having the lower wiring 55 (step 23 of FIG. 2). The etch stop layer 59 may be formed of an insulating layer having an etch selectivity with respect to the interlayer insulating layer 61. Preferably, the etch stop layer 59 is at least one film selected from the group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and benzenecyclobutene (BCB). It can be formed as.

The interlayer insulating layer 61 may be formed of a single low-k dielectric layer to improve the operation speed of the semiconductor device and to prevent the formation of an interface in the interlayer insulating layer 61. The single low dielectric film may be formed of a silicon oxide film containing carbon, fluorine or hydrogen, such as a SiOC film, SiOCH film or SiOF film.

After the etching stop layer 59 is formed, the interlayer insulating layer 61 is formed using an in-situ process so that the interface between the etching stop layer 59 and the interlayer insulating layer 61 is dense. That is, after the etch stop layer 59 is formed, the interlayer insulating layer 61 is formed without vacuum breaking. Since the interlayer insulating layer 61 is formed using an in-situ process, the interface between the etch stop layer 59 and the interlayer insulating layer 61 is dense.

Alternatively, after the etch stop layer 59 is formed, a method of surface treating the etch stop layer 59 using plasma gas may be used. As the plasma gas, at least one gas selected from the group consisting of NH ₃ , O ₂ , O ₃ , CO ₂ , N ₂ O, and Ar may be used. After the gas is excited to bring it into a plasma state, these gases are used to treat the surface of the etch stop layer 59. Even when the interlayer insulating layer 61 is formed using an ex-situ process, the interface between the etch stop layer 59 and the interlayer insulating layer 61 is dense by surface treatment of the etch stop layer 59. Can be done.

Meanwhile, before forming the etch stop layer 59, a diffusion barrier layer 57 may be formed. The diffusion barrier 57 prevents the diffusion of metal atoms from the lower interconnection 55 into the interlayer insulating layer 61. Preferably, the diffusion barrier 57 is at least one film selected from the group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), or benzocyclobutene (BCB). Can be formed.

The interlayer insulating layer 61 is patterned by photolithography and etching to form a preliminary via hole 63 exposing the etch stop layer 59 (step 25 of FIG. 2). Since the etch stop layer 59 has an etch selectivity with respect to the interlayer insulating layer 61, an etchant having a higher etch rate of the interlayer insulating layer 61 than that of the etch stop layer 59 is used. Etching is performed.

Preferably, after forming a hard mask layer (not shown) on the interlayer insulating layer 61, the preliminary via hole 63 may be formed by patterning the hard mask layer and the interlayer insulating layer 61. . The hard mask layer is formed of a material layer having an etching selectivity with respect to the interlayer insulating layer 61. The hard mask layer protects a corner of the preliminary via hole 63.

2 and 3B, a via protection layer 65 filling the preliminary via hole is formed on the entire surface of the semiconductor substrate on which the preliminary via hole 63 is formed (step 27 of FIG. 2). The via protection layer 65 is formed of a material film having a wet etching selectivity with respect to the interlayer insulating layer 61 and the etch stop layer 59. The via protective layer 65 may be formed of a material film having a dry etching selectivity of 1 to 2 times faster than the interlayer insulating layer 61. Preferably, the material layer may be formed of a hydro-silses-quioxane layer (HSQ layer) using spin coating. Accordingly, the preliminary via hole 63 may be completely filled with the via protection layer 65, and the via protection layer 65 may have a flat surface.

2 and 3C, the via protective layer 65 and the interlayer insulating layer 61 are sequentially patterned by photo and etching processes to cross the upper portion of the preliminary via hole 63, and the interlayer insulating layer 61 and Define trench region 67 located within via protection layer 65 (step 29 of FIG. 2). When the interlayer insulating layer 61 is formed of a single low dielectric film, the trench region 67 is formed by partially etching the interlayer insulating layer 61. When a hard mask film is formed on the interlayer insulating film 61, the hard mask film is also patterned.

The via protection layer 65 has a faster dry etching selectivity than the interlayer insulating layer 61. Accordingly, the via protection layer 65 may remain in the preliminary via hole 63, but does not remain in the trench region 67. Meanwhile, the via protection layer 65 has a dry etching selectivity of 2 times or less than that of the preliminary via hole 63. Therefore, the via protection layer 65a remaining in the preliminary via hole 63 prevents etching damage of the lower interconnection 55.

2 and 3D, the via protection layer 65a and the via protection layer 65 on the interlayer insulating layer 61 in the preliminary via hole 63 are removed (step 31 of FIG. 2). The via protection layers 65 and 65a are removed using wet etching. As a result, the etch stop layer 59 is exposed.

Since the via protective layer 65a has a wet etching selectivity with respect to the interlayer insulating layer 61 and the etch stop layer 59, surface etch damage of the interlayer insulating layer 61 and the etch stop layer 59 is performed. This is avoided.

Meanwhile, an interface exposed in the preliminary via hole 63, that is, an interface between the etch stop layer 59 and the interlayer insulating layer 61 may be an in-situ process or surface, as described with reference to FIG. 3A. Dense by treatment Therefore, during the removal of the via protection layer 65a, undercut may be prevented from occurring at the interface between the interlayer insulating layer 61 and the etch stop layer 59. Accordingly, the wet etching process time for removing the via protection layer 65a may be further increased.

2 and 3E, the exposed etch stop layer 59 is removed to expose the lower interconnection 55 (step 33 of FIG. 2). The etch stop layer 59 may be removed using dry etching. Meanwhile, when the diffusion barrier layer 57 is formed below the etch stop layer 59, the diffusion barrier layer 67 is also removed using a dry etching process.

As a result, the final via hole 63a exposing the lower wiring 55 is formed.

2 and 3F, an upper metal film is formed on the entire surface of the semiconductor substrate on which the final via hole 63a is formed. The upper metal layer may be formed by sequentially stacking a barrier metal layer 69 and a metal layer 71. The diffusion barrier metal film 69 may be formed of a tantalum nitride film (TaN) or a titanium nitride film (TiN). The metal film 71 is formed of a copper film. The copper layer 71 may be formed by first forming a copper seed layer on the diffusion barrier metal layer 69 and then using chemical vapor deposition (CVD) or plating. .

Since the undercut is prevented at the interface between the interlayer insulating layer 61 and the etch stop layer 59, the diffusion barrier metal layer 69 and the copper seed layer are continuously formed. Accordingly, the copper layer 71 may also fill the final via hole 63a and the trench region 67 well.

The diffusion barrier metal film 69 and the metal film 71 are planarized to form upper interconnections in the trench region 67 and the final via hole 63a (step 35 of FIG. 2). The planarization process may be carried out using a chemical mechanical polishing process.

As described above, according to the embodiment of the present invention, the sidewall profile of the via hole and the trench region for embedding the copper may be secured while securing the process margin for removing the via protection layer. As a result, poor copper embedding can be prevented.

1A and 1B are cross-sectional views illustrating a method of forming a via contact structure using a dual damascene process according to the prior art.

2 is a process flowchart illustrating a method of forming a via contact structure using a dual damascene process according to an embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of forming a via contact structure using a dual damascene process according to an embodiment of the present invention.

Claims (6)

A lower wiring is formed on the semiconductor substrate, An etch stop layer and an interlayer dielectric layer are sequentially formed on the semiconductor substrate, and the interlayer dielectric layer is formed using an in-situ process. Patterning the interlayer insulating layer to form a preliminary via hole exposing the etch stop layer on the lower interconnection; Forming a via protection layer filling the preliminary via hole, Patterning the interlayer insulating film to form a trench region crossing the upper portion of the preliminary via hole and positioned in the interlayer insulating film; Exposing the etch stop layer by removing the via protection layer remaining in the preliminary via hole, And etching the exposed etch stop layer to form a final via hole exposing the lower interconnection. The method of claim 1, And forming a diffusion barrier layer before forming the etch stop layer, wherein the diffusion barrier layer below the exposed etch stop layer is removed together with the exposed etch stop layer. The method of claim 1, The etch stop layer is a via contact structure forming method, characterized in that formed with at least one film selected from the group consisting of SiN, SiC, SiCN or BCB. The method of claim 1, And the interlayer insulating film is formed of a single low-k dielectric layer. The method of claim 4, wherein And the single low dielectric film is formed of any one film selected from the group consisting of SiOC film, SiOCH film or SiOF film. A lower wiring is formed on the semiconductor substrate, An etch stop layer and an interlayer dielectric layer are sequentially formed on the entire surface of the semiconductor substrate having the lower wiring, wherein the interlayer dielectric layer is formed after surface treatment of the etch barrier layer. Patterning the interlayer insulating layer to form a preliminary via hole exposing the etch stop layer on the lower interconnection; Forming a via protection layer filling the preliminary via hole, Patterning the interlayer insulating film to form a trench region crossing the upper portion of the preliminary via hole and positioned in the interlayer insulating film; Exposing the etch stop layer by removing the via protective layer remaining in the preliminary via hole, And etching the exposed etch stop layer to form a final via hole exposing the lower interconnection.