KR20050010700A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

PURPOSE: A method of manufacturing a semiconductor memory device is provided to cover an exposed part of a bit line and a second contact plug by forming a single nitride layer capable of adjusting a step coverage. CONSTITUTION: A bit line(110) having a conductive layer and an insulating layer is formed on a semiconductor substrate(100) having a contact pad. A first interlayer dielectric is formed on the semiconductor substrate. A first storage node contact hole is formed to expose the contact pad. A first contact plug(125) is formed within the first storage node contact hole. A second interlayer dielectric(130) is formed thereon. A second storage node contact hole is formed by etching the second interlayer dielectric. A nitride layer(135) is formed on the second interlayer dielectric and the second storage node contact hole. The first contact plug is exposed by etching the nitride layer. A second contact plug(140) is formed within the second storage node contact hole.

Description

Method for manufacturing semiconductor memory device

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a semiconductor memory device for preventing an electrical short between the bit line and the storage node contact plug.

As the degree of integration of semiconductor devices has gradually decreased, it has become very difficult to form capacitors having a large surface area in a narrow space. Recently, in order to secure sufficient capacitance, a storage node electrode of a capacitor is implemented in a cylinder shape, and a storage node contact plug which electrically connects the storage node electrode and a contact pad connected to the source is formed in two stages. The method is being introduced.

1A and 1B are cross-sectional views of a semiconductor memory device illustrating a method of forming a storage node contact plug having a two-stage structure. FIG. 1A illustrates a region in which a first storage node contact plug is formed between bit lines, and FIG. 1B. Shows an area where a first interlayer insulating film is formed between bit lines.

1A and 1B, a bit line conductive layer 12 and a hard mask layer 14 are sequentially stacked on a semiconductor substrate 10, and then predetermined portions are patterned. Thereafter, the spacers 16 are formed on the opposite sidewalls of the patterned structure with the same material as the hard mask layer 14 to complete the bit lines 20. Thereafter, the first interlayer insulating layer 22 is deposited on the resultant bit line 20, and then a portion of the first interlayer insulating layer 22 is etched to expose a contact pad (not shown) in contact with the source. Thus, a first storage node contact hole is formed. The first storage node contact hole is formed in a self-aligned manner by the bit line 20 having the hard mask layer 14 and the spacer 16.

Thereafter, the conductive layer is deposited so that the first storage node contact hole is sufficiently filled, and then the conductive layer and the first interlayer insulating layer 22 are chemically mechanically polished to form the first contact plug 25. After depositing the second interlayer insulating film 28 on the resultant, the second interlayer insulating film is etched to expose the first contact plug 25 to form a second storage node contact hole, and then into the second storage node contact hole. The second contact plug 30 is formed in a known manner. Subsequently, an etch stopper 32 is formed on the second interlayer insulating film 28 and the second contact plug 30.

However, during the etching process for forming the second storage node contact hole, the first interlayer insulating layer 22 and the bit line spacers between the bit lines 20 are etched to match the excessive etching and the etching uniformity, as shown in FIG. 1B. Part 16 may be lost. Due to the loss of the first interlayer insulating layer 22 and the bit line spacer 16, the bit line 20, that is, the conductive layer 12 may be partially exposed, and thus, the exposed conductive layer 12 and then Short may occur between the second contact plugs 30 to be formed. This short problem can be solved by increasing the thickness of the hard mask layer 14 of the bit line 20. However, it is currently impossible to increase the thickness of the hard mask layer 14 in a semiconductor process. In FIG. 1B, a portion “A” represents a portion in which a short is generated, and FIG. 2 is a SEM photograph showing a state in which the bit line 20 and the second contact plug 30 are short.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of preventing a short between a bit line and a storage node contact plug.

1A and 1B are cross-sectional views of a semiconductor memory device showing a method of forming a two-stage storage node contact plug.

2 is a SEM photograph showing a state in which a short is generated between a bit line and a second contact plug.

3 is a plan view of a semiconductor memory device formed up to a first storage node contact plug;

4A and 4B, 5A and 5B, 6A and 6B are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor memory device according to the present invention.

Explanation of symbols on main parts of drawing

100 semiconductor substrate 110 bit line

120: first interlayer insulating film 125: first contact plug

130: second interlayer insulating film 135: single nitride film

140: second contact plug

In order to achieve the above object of the present invention, the present invention, forming a bit line consisting of a conductive layer and an insulating film surrounding the conductive layer on a semiconductor substrate having a contact pad, the semiconductor substrate on which the bit line is formed Forming a first storage node contact hole along the bit line with the first interlayer insulating layer to form a first interlayer insulating layer thereon, and exposing the contact pads; Forming a first contact plug, forming a second interlayer insulating film on the resultant, etching a second interlayer insulating film to expose the first contact plug, and forming a second storage node contact hole; Depositing a nitride film on the upper surface of the interlayer insulating layer and the second storage node contact hole at a higher deposition rate than the sidewalls; A nitride film by anisotropic etching, and a step of exposing the first contact plug, and within the second storage node contact holes to form the second contact plug.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a plan view of a semiconductor memory device formed up to a first storage node contact plug, and FIGS. 4A and 4B, 5A and 5B, and 6A and 6B illustrate a method of manufacturing a semiconductor memory device according to the present invention. It is sectional drawing by each process. 4A, 5A, and 6A are cross-sectional views taken along the line AA ′ of FIG. 3, and FIGS. 4B, 5B, and 6B are cross-sectional views taken along the line BB ′ of FIG. 3. to be.

3, 4A, and 4B, the conductive layer 102 and the hard mask film 104 are disposed on the semiconductor substrate 100, for example, a silicon substrate on which a MOS transistor, a contact pad, an insulating film, and the like are formed. Laminate sequentially. As the conductive layer 102, a film in which only tungsten, a doped polysilicon film, and a tungsten silicide film are stacked alone or in at least one layer may be used. The hard mask film 104 may be, for example, a silicon nitride film. After the hard mask film 104 and the conductive layer 102 are partially patterned, spacers 106 are formed on the sidewalls of the patterned structure in a known manner to form bit lines 110, or bit line structures. The first interlayer insulating layer 120 is deposited to sufficiently fill the space between the bit lines 110. The first interlayer insulating layer 120 may be an undoped silicate glass (USG), a high temperature oxide (HTO), a medium temperature oxide (MTO), a tetraethoxysilane (TEOS), a high density plasma (HDP) oxide film, or a BPSG ( A doped oxide film such as borophosphosilicate glass (PSG) or phosphosilicate glass (PSG) may be used alone or in a stack. Thereafter, the first interlayer insulating layer 120 is etched to expose a contact pad (not shown) in contact with the source of the MOS transistor, thereby forming a first storage node contact hole 121. The first storage node contact hole 121 is formed in a self-aligned manner by the hard mask layer 104 and the spacer 106 of the bit line 110. Thereafter, the conductive layer is deposited to fill the first storage node contact hole 121, and then the first contact plug 125 is formed by chemical mechanical polishing of the conductive layer and the first interlayer insulating layer 120.

As shown in FIGS. 5A and 5B, a second interlayer insulating layer 130 is deposited on the bit line 110, the first interlayer insulating layer 120, and the first contact plug 125, and then the first contact plug. The second interlayer insulating layer 130 is etched to expose the 125, thereby forming a second storage node contact hole 132. The excessive etching is performed so that the first contact plug 125 may be completely exposed. In this case, in the excessive etching process, the first interlayer insulating layer 120 and the hard mask layer 106 may be partially lost, and thus the conductive layer 102 of the bit line may be exposed. In addition, as an etching gas for forming the second storage node contact hole 132, C4F8, C5F8, or C4F6, in which a large amount of polymer is generated for the purpose of increasing the selectivity between the hard mask layer and the interlayer insulating layer, is used as the main etching gas. In order to enable highly selective etching and reproducible etching of the hard mask film, CHF3, C2HF5, CH2F2, CHF3, CH2, CH4, C2H4, or H2 is used as an auxiliary etching gas. Moreover, you may further add an inert gas. Thereafter, an O 2 plasma process is performed to remove polymer that may be generated on the exposed surface of the first contact plug 125. In this case, the process of forming the second storage node contact hole and the O2 plasma process may be performed in situ.

Thereafter, in order to prevent contact between the exposed bit line conductive layer 102 and the second contact plug to be formed later, a nitride film 135 having step coverage control is deposited on the resultant. The nitride film 135 may be deposited relatively thickly on the second interlayer insulating film 130 and thinly deposited on the exposed surface of the first contact plug 125. The nitride film 135 may have a ratio of gas in the chamber. And step coverage is changed through temperature control, which is referred to as a single nitride film in this embodiment.

Next, as shown in FIGS. 6A and 6B, the single nitride film 135 is anisotropically etched to expose the surface of the first contact plug 125. Accordingly, the second interlayer insulating layer 130 and the exposed bit line 110 are surrounded by the single nitride layer 135. Then, a conductive layer is deposited to fill the second storage node contact hole 132, and the second contact plug 140 is formed by chemically mechanical polishing or etching back to expose the single nitride layer 135. .

As described above in detail, according to the present invention, a second storage node contact hole is formed, and then a single nitride film having a step coverage adjustment is formed to surround the second interlayer insulating layer defining the second storage node contact hole. By forming a single nitride film, an exposed bit line can be covered to prevent a short with a second contact plug formed in a subsequent process.

Other changes can be made without departing from the spirit of the invention.

Claims (6)

Forming a bit line comprising a conductive layer and an insulating film surrounding the conductive layer on a semiconductor substrate having a contact pad; Forming a first interlayer insulating layer on the semiconductor substrate on which the bit lines are formed; Forming a first storage node contact hole along the bit line with the first interlayer insulating layer to expose the contact pads; Forming a first contact plug in the first storage node contact hole; Forming a second interlayer insulating film on the resultant material; Etching a second interlayer insulating layer to expose the first contact plug to form a second storage node contact hole; Depositing a nitride film on the surface of the second interlayer insulating layer and the second storage node contact hole at an upper deposition rate than a sidewall; Anisotropically etching the nitride film to expose the first contact plug; And And forming a second contact plug in the second storage node contact hole. The method of claim 1, wherein the forming of the bit line comprises: Forming a conductive layer on the semiconductor substrate; Forming a hard mask layer on the conductive layer; Patterning the hard mask layer and the conductive layer; And Forming a spacer on sidewalls of the patterned conductive layer and the hard mask layer. The non-doped oxide film of claim 1, wherein the first interlayer insulating film is an undoped silicate glass (USG), a high temperature oxide (HTO), a medium temperature oxide (MTO), a tetraethoxysilane (TEOS), and a high density plasma (HDP) oxide film. Or a doped oxide film such as borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG) is a single or laminated film. The method of claim 1, wherein the etching process for forming the second storage node contact hole comprises C4F8, C5F8, or C4F6 as the main etching gas, and CHF3, C2HF5, CH2F2, CHF3, CH2, CH4, C2H4, or H2 as secondary etching. A method of manufacturing a semiconductor memory device comprising etching with gas. The method of claim 1, wherein an inert gas is additionally supplied when the second storage node contact hole is formed. The method of claim 1, wherein the step of forming the second storage node contact hole and forming the second contact plug removes a polymer that may be generated on the surface of the first contact plug. The method of manufacturing a semiconductor memory device, characterized in that to proceed in-situ.