KR20050008259A - Light Emitting Diode Chip of High Absolute Maximum Ratings for High Brightness - Google Patents

Light Emitting Diode Chip of High Absolute Maximum Ratings for High Brightness Download PDF

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KR20050008259A
KR20050008259A KR20030048145A KR20030048145A KR20050008259A KR 20050008259 A KR20050008259 A KR 20050008259A KR 20030048145 A KR20030048145 A KR 20030048145A KR 20030048145 A KR20030048145 A KR 20030048145A KR 20050008259 A KR20050008259 A KR 20050008259A
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chip
electrode
light emitting
emitting diode
increase
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KR20030048145A
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Korean (ko)
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표진구
김영희
조은영
임근영
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(주)아트세미텍
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Publication of KR20050008259A publication Critical patent/KR20050008259A/en

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Abstract

PURPOSE: A high absolute rated LED chip having high brightness is provided to maximize the optical output efficiency by increasing the size of the LED chip and installing a wire bonding electrode at an edge of the LED chip. CONSTITUTION: A size(1) of an LED chip is defined to increase an absolute rated current of an LED. The LED chip is formed with a shape of regular square or a shape of rectangle. Each side of the regular square or the rectangle has a length of 0.5 to 2.0mm. A bonding electrode(2) is formed at an edge within the LED chip. The bonding electrode is formed with a shape of circle or a shape of rectangle. An electrode area ratio belongs to a range of 20 to 30 percent in order to increase brightness of the LED.

Description

고휘도 고절대정격 발광 다이오드 칩{Light Emitting Diode Chip of High Absolute Maximum Ratings for High Brightness}Light Emitting Diode Chip of High Absolute Maximum Ratings for High Brightness}

본 발명의 목적은 발광 다이오드의 칩 크기An object of the present invention is the chip size of a light emitting diode

(Chip Size)를 키우고 전극의 모양 및 본딩 전극Increase (Chip Size), shape of electrode and bonding electrode

(Bonding Electrode)의 위치, 전극 면적비 최적화 설계, 에피(Epi)표면의 식각(Etch)을 통해 발광 다이오드의 P/N 접합부(Junction)의 전류 밀도(Current Density) 형성을 균일하게 하고 전류 밀도 분포가 포화되는 최대정격 전류를 높이는데 목적이 있다.(Bonding Electrode) location, electrode area ratio optimization design, and the epitaxial etch to make the current density of P / N junction of light emitting diode uniform and The purpose is to increase the maximum rated current to be saturated.

절대정격을 높일 경우 고전류(High Current)를 인가하여 발광 다이오드를 구동할 수 있으므로 발광 다이오드의 전류 대 광출력의 비례 특성에 의해If the absolute rating is increased, the light emitting diode can be driven by applying a high current.

고휘도화를 구현할 수 있다.High brightness can be achieved.

종래의 발광 다이오드의 칩 크기(Chip Size)는0.2~0.4mm로 제조되어지고 있고, 이때 가시광선 발광 다이오드의 절대정격은 30~50mA, 적외선 발광 다이오드가 80~100mA이다.Chip size of the conventional light emitting diode (Chip Size) is manufactured in 0.2 ~ 0.4mm, the absolute rating of the visible light emitting diode is 30 ~ 50mA, the infrared light emitting diode is 80 ~ 100mA.

본 발명의 발광 다이오드는 칩 크기(Chip Size)를 0.5~2.0mm로 키우고 전극 면적비를 최소화하면서 전류의 밀도의 분포를 균일하게 하여 절대정격을 3~6배 향상시키고 광출력 또한 절대정격의 향상 대비 증가시켜 발광 다이오드를 고휘도화 이루도록 하였다.In the light emitting diode of the present invention, the chip size is increased to 0.5 to 2.0 mm, the electrode area ratio is minimized, the current density is uniform, and the absolute rating is improved 3 to 6 times, and the light output is also improved. Increasing the brightness of the light emitting diode was achieved.

이는 조명용 광원으로 사용되는 고휘도 발광 다이오드로 사용될 수 있다.It can be used as a high brightness light emitting diode used as a light source for illumination.

종래의 발광 다이오드는 와이어 본딩(Wire Bonding) 전극이 중앙에 배치되어져 있고 전류 밀도의 분포를 위해 배선이 0~4개로 구성되어져 있다.In the conventional light emitting diode, a wire bonding electrode is disposed at the center, and the wiring is composed of 0 to 4 wires for distribution of current density.

이 경우 에피(Epi) 표면의 캐리어 농도In this case, the carrier concentration on the epi surface

(Carrier Concentration)가 높을 경우 전극으로 주입된 전류가 표면을 타고 측면으로 보내지는 양이 많아져 칩(Chip)의 외주부분에 전류가 포화된다.If the carrier concentration is high, the current injected into the electrode is increased to the side by riding the surface, so that the current is saturated in the outer peripheral part of the chip.

이 경우 만일 다이싱(Dicing)시 발생되는 크랙(Crack) 및 전도 물질의 오염(Contamination)이 있으면 외주부로의 누설전류(Leakage Current) 발생이 유발되어 휘도 저하 및 수명에 치명적인 이상 요인이 된다.In this case, if cracks and contamination of conductive materials generated during dicing occur, leakage current to the outer circumference is generated, which is a fatal abnormality factor for luminance deterioration and lifespan.

본 발명은 와이어 본딩(Wire Bonding) 전극을 칩의 가장자리에 배치시켜 본딩 와이어(Bonding Wire)로 가려져 휘도가 낮아지는 요인을 해소하였고 전극을 5~30um 배선으로 하여 칩(Chip)표면에 균일하게 배치 시켰다.In the present invention, the wire bonding electrode is placed on the edge of the chip to obscure the factor of lowering the brightness due to the bonding wire, and the electrode is evenly arranged on the surface of the chip with 5-30 μm wiring. I was.

또한 에피(Epi) 표면의 캐리어 농도(Carrier Concentration)가 높을 경우 메탈증착(Metalization) 및 얼로이(Alloy)공정을 통한 오믹 컨텍(Ohmic Contact)이후에 표면 전극 이외 부분을 화공물질In addition, when the carrier concentration on the epi surface is high, chemicals other than the surface electrode may be removed after ohmic contact through metallization and alloy processes.

(Chemical)로 식각(Etch)처리하여 제거하고 산화막 처리(Passivation)를 하여 표면을 타고 측면으로 강하게 보내지는 전류 밀도의 양을 조절하였다.(Chemical) was removed by etching and the oxide film treatment (Passivation) to control the amount of current density that is strongly sent to the side on the surface.

이로써 본 발명은 절대 정격을 향상시키면서 광출력을 극대화함으로써 발광 다이오드의 고휘도화 구현하여 조명용 광원으로 사용 가능할 수 있게 하는데 그 목적이 있다.As a result, the present invention aims to be able to be used as a light source for lighting by realizing high brightness of the light emitting diode by maximizing the light output while improving the absolute rating.

본 발명이 이루고자하는 기술적 과제는 발광 다이오드의 절대정격을 높이고 고휘도화를 이루는데있다.The technical problem to be achieved by the present invention is to increase the absolute rating of the light emitting diode and to achieve high brightness.

본 발명의 기술적 과제를 수행하기 위해 발광 다이오드의 칩 크기(Chip Size)를 키우고 와이어 본딩(Wire Bonding)전극의 배치를 칩의 한 모서리 가장자리에 하였고 전극 면적비를 20~30%로 하여 광출력의 효율 값을 극대화하였다.In order to carry out the technical problem of the present invention, the chip size of the light emitting diode was increased, and the wire bonding electrode was disposed at one edge of the chip, and the electrode area ratio was 20 to 30%, resulting in light output efficiency. The value was maximized.

또한 양호한 오믹컨텍(Ohmic Contact)을 위해 GaAs , GaP , GaAsP ,GaAlAs, InGaAlP, InP , GaN등 에피(Epi)표면의 캐리어 농도(Carrier Concentration)을 높인 것을 전극 형성 후 식각(Etch)을 통해 제거하여 발광 다이오드의 P/N 접합부(Junction)의 전류 밀도(Current Density) 형성을 균일하게 하고 전류 밀도 분포가 포화되는 최대정격 전류를 높이는 것을 구현하였다.In addition, for good ohmic contact, the carrier concentration of the epi surface such as GaAs, GaP, GaAsP, GaAlAs, InGaAlP, InP, GaN, etc. The current density of the P / N junction of the light emitting diode is uniformed and the maximum rated current at which the current density distribution is saturated is increased.

도1은 본 발명의 표면 캐리어 농도가 낮은 발광 다이오드 정면도1 is a front view of a light emitting diode having a low surface carrier concentration according to the present invention.

도2는 본 발명의 표면 캐리어 농도가 높은 발광 다이오드 정면도2 is a front view of a light emitting diode having a high surface carrier concentration according to the present invention;

도3은 본 발명의 발광 다이오드 측면도Figure 3 is a side view of the light emitting diode of the present invention

도4는 본 발명 발광 다이오드로 조립된 램프(Lamp) 측면도4 is a side view of a lamp assembled with the light emitting diode of the present invention.

본 발명을 첨부도면에 따라서 상세하게 설명하면 다음과 같다.The present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 표면 캐리어 농도가 낮은 발광 다이오드 정면도이다.1 is a front view of a light emitting diode having a low surface carrier concentration according to the present invention.

칩 크기(Chip Size)(1)는 절대 정격을 고려하여 0.5mm~2.0mm로 하였다.Chip Size (1) was 0.5mm to 2.0mm in consideration of absolute rating.

칩(Chip) 표면 전극의 와이어 본딩(Wire Bonding) 전극부(2)는 전류 밀도(Current Density) 분포의 균일성 및 Bonding된 Al , Au Wire가 칩의 발광부를 가리지 않도록 하기 위해 4각형의 네 꼭지점중 한 모서리에 배열 시켰다.The wire bonding electrode portion 2 of the chip surface electrode has four corners of four corners for uniformity of current density distribution and to prevent the bonded Al and Au wire from covering the light emitting portion of the chip. It was arranged in one corner.

배선부(3)는 반도체와 금속(Metal)간의 낮은 오믹컨텍(Ohmic Contact) 저항을 유지하고 칩(Chip)발광 면적비의 극대화를 위해 5~30um의 배선 폭으로 구성했다.The wiring part 3 is configured with a wiring width of 5 to 30um to maintain low ohmic contact resistance between the semiconductor and metal and maximize the chip light emitting area ratio.

배선부(3)의 위치는 칩(Chip) 표면의 원형전극에서부터 칩(Chip)의 대각 방향으로 방사형의 모양으로 배치하였고 배선간의 간격(Pitch)은 전극과 칩 전체의 면적을 고려한 면적비가 20~30%가 되도록 배치시켰다.The position of the wiring part 3 is arranged in a radial shape from the circular electrode on the surface of the chip to the diagonal direction of the chip, and the pitch between the wirings has an area ratio of 20 ~ considering the area of the electrode and the whole chip. Placed to 30%.

도 2는 본 발명의 표면 캐리어 농도가 높은 발광 다이오드 정면도이다.2 is a front view of a light emitting diode having a high surface carrier concentration according to the present invention.

칩 크기(Chip Size)(4)는 절대 정격을 고려하여 0.5mm~2.0mm로 하였다.Chip size (4) was 0.5mm ~ 2.0mm in consideration of the absolute rating.

칩(Chip) 표면 전극의 와이어 본딩(Wire Bonding) 전극부(5)는 전류 밀도(Current Density) 분포의 균일성 및 Bonding된 Al , Au Wire가 칩의 발광부를 가리지 않도록 하기 위해 4각형의 네 꼭지점중 한 모서리에 배열 시켰다.The wire bonding electrode portion 5 of the chip surface electrode is a quadrilateral of four corners for uniformity of current density distribution and to prevent the bonded Al and Au wire from covering the light emitting portion of the chip. It was arranged in one corner.

배선부(6)는 반도체와 금속(Metal)간의 낮은 오믹컨텍(Ohmic Contact) 저항을 유지하고 칩(Chip) 발광 면적비의 극대화를 위해 5~30um의 배선 폭으로 구성했다.The wiring part 6 is configured to have a wiring width of 5 to 30 μm to maintain low ohmic contact resistance between the semiconductor and metal and to maximize the chip emitting area ratio.

배선부(6)의 위치는 칩(Chip) 표면의 원형전극에서부터 칩(Chip)의 대각 방향으로 방사형의 모양으로 배치하였고, 배선간의 간격(Pitch)은 전극과 칩 전체의 면적을 고려한 면적비가 20~30%가 되도록 배치시켰다.The position of the wiring part 6 was arranged in a radial shape from the circular electrode on the surface of the chip to the diagonal direction of the chip, and the pitch between the wirings was 20 in consideration of the area of the electrode and the entire chip. Placed at ˜30%.

GaAs , GaP , GaAsP ,GaAlAs,InGaAlP, InP , GaN등 에피(Epi)표면(7)의 높은 캐리어 농도(Carrier Concentration) 층(Layer)을 전극 형성 후 화공물질Chemical material after electrode formation of high Carrier Concentration Layer of Epi surface 7 such as GaAs, GaP, GaAsP, GaAlAs, InGaAlP, InP, GaN

(Chemical) 및 건식식각(Dry Etch)장비를 활용하여(Chemical) and Dry Etch Equipment

식각(Etch)하여 발광 다이오드의 P/N 접합부Etch P / N junction of light emitting diode

(Junction)의 전류 밀도(Current Density) 형성을 균일하게 하고 전류 밀도 분포가 포화되는 최대정격 전류를 높이는 것을 구현하였다.The current density of the junction is made uniform and the maximum rated current at which the current density distribution is saturated is increased.

도 3은 본 발명의 발광 다이오드 측면도이다.3 is a side view of the light emitting diode of the present invention.

발광 다이오드의 칩(Chip)구조는 간략하게 표현하여 N 또는 P 의 기판(Substrate)(8), N 또는 P 의 Epi 층(Layer)(9), P 또는 N Epi 층(Layer)(10)로 구성되어 진다.The chip structure of the light emitting diode is briefly described as N or P substrate (8), N or P Epi layer (9), or P or N Epi layer (10). It is constructed.

Epi층의 계면에 P/N 접합면(Junction)(11)이 형성되어져 있다P / N junction 11 is formed in the interface of Epi layer.

에피(Epi)표면의 높은 캐리어 농도(Carrier Concentration) 층(Layer)은 전극 형성 후 화공물질High Carrier Concentration Layers on the Epi Surface

(Chemical) 및 건식식각(Dry Etch)장비를 활용하여(Chemical) and Dry Etch Equipment

식각(Etch)하고 산화막(11)을 Deposition 공정이나 화학 처리 공정을 이용하여 도포한다.Etch and the oxide film 11 is applied using a deposition process or a chemical treatment process.

발광 다이오드의 P/N 접합부(Junction)의 전류 밀도(Current Density) 형성을 균일하게(12) 하고 전류 밀도 분포가 포화되는 최대정격 전류를 높이는 것을 구현할 수 있다.It is possible to implement the current density (Current Density) formation of the P / N junction (12) of the light emitting diode uniformly (12) and to increase the maximum rated current at which the current density distribution is saturated.

도 4는 본 발명 발광 다이오드로 조립된 램프(Lamp) 측면도이다.4 is a side view of a lamp assembled with the light emitting diode of the present invention.

리드프레임(13)과 본딩전극(14)에 연결되는 본딩(Bonding Wire)(15)의 각기 방향은 칩(Chip)의 발광부를 가로지르지 않도록 리드프레임(13)이 칩 가장자리에 위치되어져 있다.The lead frame 13 is positioned at the edge of the chip so that the respective directions of the bonding wires 15 connected to the lead frame 13 and the bonding electrode 14 do not cross the light emitting part of the chip.

이는 본딩와이어(Bonding Wire)로 가려지는 발광 면적을 줄일 수 있어 휘도의 향상을 이룰 수 있다.This can reduce the light emitting area covered by the bonding wires, thereby improving the luminance.

이상에서 살펴본 바와 같이 본 발명의 효과는 종래의 발광 다이오드에 비해 3~6배 높은 절대정격의 칩을 구현 할 수 있어 조명용과 같은 고휘도 발광 다이오드에 사용 가능하다.As described above, the effect of the present invention can implement a chip having an absolute rating 3 to 6 times higher than that of a conventional light emitting diode, and thus it can be used for a high brightness light emitting diode such as lighting.

Claims (6)

발광 다이오드의 절대정격 전류를 높이기 위한 칩 크기(Chip Size)(1)Chip Size to Increase the Absolute Rated Current of Light-Emitting Diodes (1) :칩 모양이 정사각형 또는 직사각형이고 사각형 각각 면의 길이가 0.5mm~2.0mm인 발광 다이오드Light-emitting diodes with square or rectangular chips and 0.5 mm to 2.0 mm 칩(Chip)내에 본딩 전극(Bonding Electrode)Bonding Electrode in Chip (2)의 위치2 positions :사각형의 네 꼭지점중 원형 또는 사각형의 본딩전극을 한 모서리에 배열시켰다.The round or square bonding electrodes of the four corners of the rectangle were arranged at one corner. 발광 다이오드의 휘도를 높이기 위한 전극 면적비(표면 전극 / 칩(Chip) 표면적): 20~30%Electrode area ratio (surface electrode / chip surface area) to increase the brightness of light emitting diodes: 20 ~ 30% 발광 다이오드의 휘도를 높이기 위한 에피Epi to increase the brightness of light emitting diodes (Epi) 표면의 높은 캐리어 농도(Carrier Concentration) 층(Layer) 식각(Etch)(Epi) Surface Carrier Concentration Layer Etch :에피(Epi)표면의 캐리어 농도(Carrier ConcenCarrier Concen on the Epi Surface tration)가 1018cm-3이상 일 경우 전극 형성 후 화공물질(Chemical) 및 건식식각 (Dry Etch)장비를 활용하여 식각(Etch)하고, 산화막(11)을 Deposition 공정이나 화학처리 공정을 이용하여 1018cm-3미만으로 낮춘다.If the tration is 10 18 cm -3 or more, the electrode is formed and then etched using chemical and dry etching equipment, and the oxide film 11 is deposited using a deposition process or a chemical treatment process. Lower to 10 18 cm -3 . 칩(Chip)내의 배선 위치Wiring location in the chip :배선부(3)의 위치는 칩(Chip) 표면의 원형전극에서부터 칩(Chip)의 사각면을 향한 방사형의 모양으로The position of the wiring part 3 is in a radial shape from the circular electrode on the surface of the chip toward the square surface of the chip. 배치arrangement 표면 전극에 배치되는 배선부(3)(6)폭 길이:Wiring section (3) (6) width length arranged in surface electrode: 반도체와 금속(Metal)간의 낮은 오믹컨텍(Ohmic Contact) 저항을 유지하고 칩(Chip) 발광 면적비의 극대화를 위해 5~30um의 배선 폭 배치5 ~ 30um wiring width for maintaining low ohmic contact resistance between semiconductor and metal and maximizing chip emitting area ratio
KR20030048145A 2003-07-15 2003-07-15 Light Emitting Diode Chip of High Absolute Maximum Ratings for High Brightness KR20050008259A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100665120B1 (en) * 2005-02-28 2007-01-09 삼성전기주식회사 Vertical structure nitride semiconductor light emitting device
KR101103892B1 (en) * 2009-12-08 2012-01-12 엘지이노텍 주식회사 Light emitting device and light emitting device package
KR101123012B1 (en) * 2009-10-23 2012-03-19 삼성엘이디 주식회사 Light emitting devices
KR101427877B1 (en) * 2008-01-30 2014-08-08 엘지이노텍 주식회사 Nitride light emitting device
US9130123B2 (en) 2009-09-23 2015-09-08 Lg Innotek Co., Ltd. Light emitting device and light emitting device package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100665120B1 (en) * 2005-02-28 2007-01-09 삼성전기주식회사 Vertical structure nitride semiconductor light emitting device
US7282741B2 (en) 2005-02-28 2007-10-16 Samsung Electro-Mechanics Co., Ltd. Vertical type nitride semiconductor light emitting diode
KR101427877B1 (en) * 2008-01-30 2014-08-08 엘지이노텍 주식회사 Nitride light emitting device
US9130123B2 (en) 2009-09-23 2015-09-08 Lg Innotek Co., Ltd. Light emitting device and light emitting device package
KR101123012B1 (en) * 2009-10-23 2012-03-19 삼성엘이디 주식회사 Light emitting devices
KR101103892B1 (en) * 2009-12-08 2012-01-12 엘지이노텍 주식회사 Light emitting device and light emitting device package
US8530882B2 (en) 2009-12-08 2013-09-10 Lg Innotek Co., Ltd. Light emitting device, light emitting device package and lighting system

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