KR20050006850A - Method for forming contact hole of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to guarantee a process margin in a subsequent process for forming a bitline contact hole by forming a landing plug by a single process instead of a SAC(self-aligned contact hole) process such that the landing plug is formed of a T type in which the upper width is greater than the lower width. CONSTITUTION: A gate(25) including a hard mask is formed in a cell area and a peripheral circuit area on a substrate(21). The first interlayer dielectric(26) is formed on the substrate to cover the gate. An etch stop layer(27) is formed on the first interlayer dielectric. The etch stop layer is exposed to the first interlayer dielectric between the gates formed in the cell area and the first interlayer adjacent to the gates formed in the cell area. The first interlayer dielectric is etched to form the first contact hole of a T type. The first contact hole of a T type is filled with a conductive layer to form a T-type landing plug(29). Predetermined portions of the second interlayer dielectric(30) is etched to form the second contact hole(31) exposing the landing plug and to simultaneously form the third and fourth contact holes(32,33) exposing the gate in the peripheral circuit area and the substrate, respectively.

Description

Method for forming contact hole of semiconductor device

The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for obtaining a process simplification.

In recent years, as the integration of devices increases, the size of memory cells decreases gradually, so that margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller, and thus, capacitor contacts must be made smaller.

Also, as semiconductor integrated circuits are highly integrated, alignment margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no margin in the design rule and the same pattern is repeated like a semiconductor memory cell, a method of reducing the area of the memory cell by forming contact holes in a self-aligned manner has been developed. This is to form a contact hole by using the step of the surrounding structure, because the contact hole of various sizes can be obtained without using a mask by the height of the surrounding structure, the thickness of the insulating material to be formed and the etching method, etc. It is used in a method suitable for the implementation of the semiconductor device to be miniaturized.

However, since the connection portions of the bit line contact holes in the cell region and the peripheral circuit region are different from each other, the degree of etching must also be different.

As illustrated in FIG. 1, in the cell region, the nitride film 14, which is a hard mask material of the gate, is not etched at all in the process of connecting the first contact hole 18 with the landing plug at the bottom by using a self-aligned method. Should not. On the other hand, in the peripheral circuit region, the second contact hole 19 must be etched to connect the nitride film 14, which is a hard mask material, with the tungsten silicide 13 below. In addition, the third contact hole 20 should etch the second interlayer insulating layer 17 and the first interlayer insulating layer 15 to connect the lower substrate 11 to the lower substrate 11.

As a result, unlike the peripheral circuit region, since the cell region uses a self-aligned method, alignment trenches may not be secured when the bit line contact hole is etched, which may cause unwanted trenches.

As a result, the formation of the bit line contact hole has to be performed by dividing the bit line contact hole in the cell region and the peripheral circuit region in order to secure the alignment margin, resulting in a cost increase due to an increase in the number of processes such as an increase in the number of mask steps. .

Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of simplifying a process for forming a contact hole, which has been made to solve the conventional problems as described above.

1 is a cross-sectional view illustrating a conventional method for forming a contact hole in a semiconductor device.

2A to 2E are cross-sectional views of processes for explaining a method of forming a contact hole in a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

21: semiconductor substrate 22: gate poly film

23 tungsten silicide 24 nitride film

25: gate 26: first interlayer insulating film

27: etch stop 28: first contact hole

29: landing plug 30: second interlayer insulating film

31: second contact hole 32: third contact hole

33: 4th contact hole

In order to achieve the above object, the present invention, forming a gate having a hard mask in each of the cell region and the peripheral circuit region on the substrate; Forming a first interlayer insulating film on the substrate to cover the gate; Forming an etch stop film on the first interlayer insulating film; Etching the etch stop layer to expose a portion of the first interlayer insulating layer between the gates formed in the cell region and a portion of the first interlayer insulating layer adjacent thereto; Etching the portion of the first interlayer insulating film to form a T-shaped first contact hole; Forming a T-shaped landing plug by embedding a conductive film in the T-shaped first contact hole; Forming a second interlayer dielectric layer on the etch stop layer including the landing plug; And simultaneously forming second contact holes exposing the landing plugs by etching certain portions of the second interlayer dielectric layer and third and fourth contact holes exposing gates and substrates of the peripheral circuit area, respectively. It provides a method for forming a contact hole.

Here, the etch stop layer performs slope etching. In addition, the landing plug is formed by etching back the conductive layer.

According to the present invention, by forming a T-shaped landing plug having good alignment margin and CD margin, it is possible to simultaneously form a bit line contact hole in a cell and a peripheral circuit area in one step without using a self-aligning method.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention. This is described as follows.

Referring to FIG. 2A, the gate poly layer 22, the tungsten silicide 23, and the hard mask 24 are sequentially deposited on the substrate 21 and then etched to form the gate 25. Thereafter, a first interlayer insulating film 26 is formed on the substrate to cover the gate 25, and then an etch stop layer 27 is formed on the first interlayer insulating film 26.

Referring to FIG. 2B, the etch stop layer 27 is etched to expose portions of the first interlayer insulating layer 26 between the gates 25 formed in the cell region. The exposed portion of the first interlayer insulating layer 26 is formed to be wider than the gap between the lower gate and the gate.

Referring to FIG. 2C, a portion of the first interlayer insulating layer 26 is etched to form a first contact hole 28. In this case, the etching of the first interlayer insulating layer 26 is performed by a slope etching method by making the line width narrower than the width of the etching stop layer 27 to form a shape of the first contact hole 28. It is shaped like a child.

Referring to FIG. 2D, a conductive film, for example, a polysilicon film is deposited on the etch stop layer to fill the T-shaped first contact hole 28, and then etched back to the first contact hole. A T-shaped landing plug 29 is formed therein.

Here, the T-shaped landing plug is to secure the alignment margin when forming the falling hole of the subsequent process.

Referring to FIG. 2E, a second interlayer insulating film 30 is formed on the etch stop film 27 including the T-shaped landing plug 29. Then, a portion of the second interlayer insulating film 30 is etched to remove the second contact hole 31 exposing the T-shaped landing plug 29 and the tungsten silicide 23 and the substrate 21 in the peripheral circuit area. The third contact hole 32 and the fourth contact hole 33 are respectively formed at the same time, thereby providing a method for forming a contact hole in a semiconductor device according to the present invention.

Up to this point, a T-shaped landing plug was formed by widening the CD of the landing plug top portion as wide as possible without using a self aligned contact hole (SAC) method when forming the landing plug. Therefore, it is possible to secure an overlay margin with the bit line contact hole.

Accordingly, bit line etching of the cell region and the peripheral circuit region may be simultaneously performed.

As described above, the present invention forms the landing plug in a single process instead of the SAC process and simultaneously forms the landing plug in a T-shape whose upper width is larger than the lower width. Accordingly, the T-shaped landing plug can secure a process margin when forming a subsequent bit line contact hole, and thus, when forming bit line contact holes in each of the cell region and peripheral circuit regions, the cell region Both the and the corresponding areas of the peripheral circuit area can be etched at the same time, thereby simplifying the bitline contact process and improving productivity.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (3)

Forming a gate having a hard mask in each of the cell region and the peripheral circuit region on the substrate; Forming a first interlayer insulating film on the substrate to cover the gate; Forming an etch stop film on the first interlayer insulating film; Etching the etch stop layer to expose a portion of the first interlayer insulating layer between the gates formed in the cell region and a portion of the first interlayer insulating layer adjacent thereto; Etching the portion of the first interlayer insulating film to form a T-shaped first contact hole; Forming a T-shaped landing plug by embedding a conductive film in the T-shaped first contact hole; Forming a second interlayer dielectric layer on the etch stop layer including the landing plug; And Etching the predetermined portions of the second interlayer dielectric layer to simultaneously form second contact holes exposing the landing plugs and third and fourth contact holes exposing gates and substrates in the peripheral circuit area, respectively. A method for forming a contact hole in a semiconductor device. The method of claim 1, wherein the etch stop layer performs a slope etch. The method of claim 1, wherein the landing plug is formed by etching back a conductive film.