KR20050003523A - Method for forming a metal contact in semiconductor device - Google Patents
Method for forming a metal contact in semiconductor device Download PDFInfo
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- KR20050003523A KR20050003523A KR1020030042418A KR20030042418A KR20050003523A KR 20050003523 A KR20050003523 A KR 20050003523A KR 1020030042418 A KR1020030042418 A KR 1020030042418A KR 20030042418 A KR20030042418 A KR 20030042418A KR 20050003523 A KR20050003523 A KR 20050003523A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
Description
본 발명은 반도체 소자의 메탈콘택 형성방법에 관한 것으로, 특히 우수한 콘택저항과 스텝 커버리지(step coverage)를 확보할 수 있는 메탈콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal contact forming method of a semiconductor device, and more particularly, to a metal contact forming method capable of securing excellent contact resistance and step coverage.
최근, 반도체 소자가 고집적화 되어감에 따라 캐패시턴스(capacitance) 확보를 위하여 캐패시터의 높이가 높아지는 추세이다. 이로 인하여, 메탈 콘택(metal contact)의 높이 또한 증가된다. 현재, 메탈 콘택은 35000Å 정도의 높이로 형성된다. 이와 같이 메탈 콘택의 높이가 증가함에 따라 베리어 메탈층(barrier metal layer)을 형성하는데에도 많은 어려움이 있으며, 이에 따라, 콘택저항을 확보하는데 많은 어려움이 발생되고 있다.In recent years, as semiconductor devices have been highly integrated, the height of capacitors has increased in order to secure capacitance. Due to this, the height of the metal contact is also increased. Currently, metal contacts are formed at a height of about 35000 kPa. As the height of the metal contact increases, there are many difficulties in forming a barrier metal layer. Accordingly, many difficulties arise in securing a contact resistance.
따라서, 본 발명의 바람직한 실시예에서는 베리어 메탈층 형성공정을 최적화하고, 스텝 커버리지(step coverage)가 우수한 H2가스를 환원 가스로 이용한 CVD(Chemical Vapor Deposition) 방법을 이용하여 텅스텐(W)의 핵생성층(nucleation layer)을 성장시키는 방법으로 우수한 콘택저항과 스텝 커버리지를 확보하는데 그 목적이 있다.Therefore, in a preferred embodiment of the present invention, the core of tungsten (W) is optimized by CVD (Chemical Vapor Deposition) method of optimizing a barrier metal layer forming process and using H 2 gas having excellent step coverage as a reducing gas. Its purpose is to ensure excellent contact resistance and step coverage by growing a nucleation layer.
도 1 내지 도 3은 본 발명의 바람직한 실시예에 따른 반도체 소자의 메탈콘택 형성방법을 설명하기 위하여 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a method for forming a metal contact of a semiconductor device according to an exemplary embodiment of the present invention.
도 4는 핵생성층 증착후 베리어 메탈층에 폭발성 페일이 발생된 모습을 도시한 SEM 사진이다.FIG. 4 is an SEM photograph showing the appearance of an explosive fail on the barrier metal layer after deposition of the nucleation layer.
도 5는 안정된 핵생성층이 증착된 모습을 도시한 SEM 사진이다.FIG. 5 is an SEM photograph showing a state in which a stable nucleation layer is deposited.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
10 : 반도체 기판 12 : 하부층10 semiconductor substrate 12 lower layer
14 : 층간 절연막 16 : 콘택홀14 interlayer insulating film 16 contact hole
18 : 베리어 메탈층 20 : 콘택 플러그18: barrier metal layer 20: contact plug
본 발명의 일측면에 따르면, 소정 깊이로 콘택홀이 형성된 반도체 기판이 제공되는 단계와, 상기 콘택홀의 내부면에는 Ti막이 증착되는 단계와, 증착공정과 플라즈마 처리를 적어도 2회 반복적으로 실시하여 상기 Ti막 상에는 TiN막이 증착되어 상기 Ti막과 상기 TiN막으로 이루어진 베리어 메탈층이 형성되는 단계와, 상기 베리어 메탈층 상에 핵생성층이 형성되는 단계와, 상기 콘택홀이 갭 필링되도록 콘택 플러그가 형성되는 단계를 포함하는 메탈콘택 형성방법을 제공한다.According to one aspect of the invention, the step of providing a semiconductor substrate having a contact hole formed to a predetermined depth, the step of depositing a Ti film on the inner surface of the contact hole, and repeatedly performing the deposition process and the plasma treatment at least twice Depositing a TiN film on the Ti film to form a barrier metal layer formed of the Ti film and the TiN film, forming a nucleation layer on the barrier metal layer, and contact plugs such that the contact holes are gap-filled. It provides a metal contact forming method comprising the step of forming.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.
도 1 내지 도 3은 본 발명의 바람직한 실시예에 따른 반도체 소자의 메탈콘택 형성방법을 설명하기 위하여 도시한 단면도들이다. 여기서, 도 1 내지 도 3에서 도시된 참조부호들 중 서로 동일한 참조부호는 동일한 기능을 하는 동일한 구성요소이다.1 to 3 are cross-sectional views illustrating a method for forming a metal contact of a semiconductor device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 3 are the same components having the same function.
도 1을 참조하면, 소정의 반도체 구조물층 상에 하부층(12)이 형성된 반도체 기판(10)이 제공된다. 여기서, 반도체 구조물층은 웰(well), 트랜지스터, 캐패시터, 배선층 및 절연층 등이 포함될 수 있다. 또한, 하부층(12)은 비트라인(bit line)으로서 텅스텐으로 형성된다. 그런 다음, 전체 구조 상부에 층간 절연막(inter layer dielectric; 14)이 형성된다. 여기서, 층간 절연막(14)은 스핀 온(spin-on) 방식으로 증착되는 저유전막 또는 CVD(Chemical Vapor Deposition) 방식으로 증착되는 저유전막으로 형성될 수 있다. 예컨대 저유전막으로는 SOG(Spin On Glass), SiOC, SiOF, 다공성 SiO2, USG(Un-doped Silicate Glass) 및 TEOS(TetraEthylOrtho Silicate Glass)가 있다. 이외에도, 경우에 따라서 층간 절연막(104)은 고유전막으로 형성될 수 있다. 고유전막으로는 BPSG(Bron Phosphorus Silicate Glass) 및 PSG(Phosphorus Silicate Glass)가 있다. 한편, 층간 절연막(14)은 상기의 물질들이 단층, 또는 적어도 2층으로 적층된 구조로 형성될 수 있으며, 상기 반도체 구조물층의 캐패시터의 높이를 고려하여 적어도 35000Å 정도의 높이를 갖도록 형성된다. 그런 다음, 리소그래피(lithography)공정에 의해 층간 절연막(14)이 식각되어 콘택홀(16)이 형성된다. 이로써, 콘택홀(16)을 통해 하부층(12)이 노출된다.Referring to FIG. 1, a semiconductor substrate 10 having a lower layer 12 formed on a predetermined semiconductor structure layer is provided. The semiconductor structure layer may include a well, a transistor, a capacitor, a wiring layer, an insulating layer, and the like. In addition, the lower layer 12 is formed of tungsten as a bit line. Then, an interlayer dielectric 14 is formed over the entire structure. Here, the interlayer insulating layer 14 may be formed of a low dielectric film deposited by a spin-on method or a low dielectric film deposited by a chemical vapor deposition (CVD) method. For example, low dielectric films include spin on glass (SOG), SiOC, SiOF, porous SiO 2 , Un-doped Silicate Glass (USG), and TetraEthylOrtho Silicate Glass (TEOS). In addition, in some cases, the interlayer insulating film 104 may be formed of a high dielectric film. High-k dielectric films include BPSG (Bron Phosphorus Silicate Glass) and PSG (Phosphorus Silicate Glass). Meanwhile, the interlayer insulating layer 14 may be formed in a structure in which the above materials are stacked in a single layer or at least two layers. The interlayer insulating layer 14 may be formed to have a height of at least 35000 고려 in consideration of the height of the capacitor of the semiconductor structure layer. Then, the interlayer insulating layer 14 is etched by a lithography process to form the contact hole 16. As a result, the lower layer 12 is exposed through the contact hole 16.
도 2를 참조하면, 도 1에서 콘택홀(16)이 형성된 후 콘택홀(16)의 내부면에는 베리어 메탈층(18)이 형성된다. 상기 베리어 메탈층(18)은 Ti막(미도시)과 TiN막(미도시)으로 형성된다. 상기 Ti막은 IMP(Ionized Metal Plasma) 방법을 이용하여 100Å 내지 300Å으로 증착되며, 바람직하게는 200Å으로 증착된다. 상기 TiN막은 MOCVD(Metal Organic CVD) 방법을 이용하여 40Å 내지 60Å으로 증착, 바람직하게는 50Å으로 증착된 후, 박막 내에 존재하는 불순물을 제거하기 위하여 N2/H2플라즈마로 25초 내지 40초, 바람직하게는 35초 동안 플라즈마 처리되어 형성된다. 이러한, MOCVD와 플라즈마 처리를 적어도 2회 이상 반복하여 상기 TiN막은 80Å 내지 120Å, 바람직하게는 100Å의 두께로 증착된다.Referring to FIG. 2, after the contact hole 16 is formed in FIG. 1, the barrier metal layer 18 is formed on the inner surface of the contact hole 16. The barrier metal layer 18 is formed of a Ti film (not shown) and a TiN film (not shown). The Ti film is deposited at 100 kPa to 300 kPa using an ionized metal plasma (IMP) method, and preferably at 200 kPa. The TiN film was deposited at 40 kPa to 60 kPa, preferably 50 kPa using a MOCVD (Metal Organic CVD) method, and then 25 to 40 sec with an N 2 / H 2 plasma to remove impurities present in the thin film. Preferably it is formed by plasma treatment for 35 seconds. The TiN film is deposited to a thickness of 80 kPa to 120 kPa, preferably 100 kPa by repeating MOCVD and plasma treatment at least twice.
그러나, 상기에서 설명한 TiN막 증착공정의 경우에는 메탈콘택의 크기가 0.17㎛에 높이가 35000Å(층간 절연막의 높이) 이상이 되어 종횡비(aspect ratio)가 20 이상이 되는 경우 콘택홀(16)의 저부(bottom)에 증착되는 TiN막의 두께가 감소될 수도 있다. 따라서, 메탈콘택의 높이가 35000Å 이상이 되는 경우에는 여러번 공정을 나누어 진행하는 것이 바람직하다. 예컨대, 상기 TiN막은 MOCVD 방법을 이용하여 20Å 내지 40Å으로 증착, 바람직하게는 30Å으로 증착된 후, 박막 내에 존재하는 불순물을 제거하기 위하여 N2/H2플라즈마로 40초 내지 50초, 바람직하게는 45초 동안 플라즈마 처리되어 형성된다. 이러한, MOCVD와 플라즈마 처리를 적어도 3회 반복하여 상기 TiN막은 60Å 내지 120Å, 바람직하게는 90Å의 두께로 증착된다.However, in the above-described TiN film deposition process, the bottom of the contact hole 16 when the metal contact has a size of 0.17 µm and a height of 35000 kPa (height of an interlayer insulating film) becomes an aspect ratio of 20 or more. The thickness of the TiN film deposited on the bottom may be reduced. Therefore, when the height of the metal contact is 35000 kPa or more, it is preferable to proceed by dividing the process several times. For example, the TiN film is deposited at 20 kPa to 40 kPa using MOCVD method, preferably at 30 kPa, and then 40 to 50 sec using N 2 / H 2 plasma to remove impurities present in the thin film. Formed by plasma treatment for 45 seconds. The TiN film is deposited to a thickness of 60 kPa to 120 kPa, preferably 90 kPa by repeating such MOCVD and plasma treatment at least three times.
이와 같이, 상기 TiN막의 증착공정을 적어도 3회에 걸쳐 여러번 나누어서 실시하고, 플라즈마 처리를 길게 가져가는 이유는 35초 동안 플라즈마 처리를 하는 경우 깊은 콘택홀(16)의 저부에서 거의 플라즈마 처리 효과가 없기 때문이다. 플라즈마 처리가 충분히 이루어지지 않는 경우, 베리어 메탈층(18)이 후속 콘택 플러그(20; 도 3참조) 형성공정시 사용되는 WF6가스의 공격(attact)을 견디지 못하게 된다. 이에 따라, 도 4에 도시된 바와 같이, 베리어 메탈층(18)에 폭발성 페일(fail)이 발생된다. 즉, 충분한 시간동안 플라즈마 처리가 이루어지지 않을 경우에는 후속 H2/WF6가스를 이용한 핵생성층 형성공정을 진행할 경우에 베리어 메탈층(18)에 폭발성 페일이 발생된다. 따라서, 상기에서 처럼 적어도 3번에 나누어서45초 동안 플라즈마 처리를 진행하면 콘택홀(18)의 내부에서 TiN막이 균등하게 플라즈마 처리되어 핵생성층 형성공정시 WF6가스의 공격을 충분히 견딜 수 있을 정도로 특성이 향상된다. 이러한 결과는 도 5에 도시된 SEM 사진을 통해서도 알 수 있다. 도 5는 TiN막을 충분히 플라즈마 처리시킨 후 증착된 핵생성층(미도시)을 도시한 도면으로서, 안정적으로 핵생성층이 베리어 메탈층(18) 상에 성장된 모습을 볼 수 있다.As described above, the deposition process of the TiN film is divided into several times at least three times, and the reason why the plasma treatment is long is that the plasma treatment for 35 seconds has almost no plasma treatment effect at the bottom of the deep contact hole 16. Because. If the plasma treatment is not sufficiently performed, the barrier metal layer 18 may not withstand the attack of the WF 6 gas used in the subsequent contact plug 20 (see FIG. 3) forming process. Accordingly, as illustrated in FIG. 4, an explosive fail is generated in the barrier metal layer 18. That is, when the plasma treatment is not performed for a sufficient time, an explosive fail occurs in the barrier metal layer 18 when the nucleation layer forming process using the subsequent H 2 / WF 6 gas is performed. Therefore, if the plasma treatment is performed for at least three times for 45 seconds as described above, the TiN film is evenly plasma-processed inside the contact hole 18 to sufficiently withstand the attack of the WF 6 gas during the nucleation layer formation process. Characteristics are improved. This result can also be seen through the SEM photograph shown in FIG. 5. FIG. 5 is a diagram illustrating a nucleation layer (not shown) deposited after the TiN film is sufficiently plasma treated, and it can be seen that the nucleation layer is stably grown on the barrier metal layer 18.
도 3을 참조하면, 도 2에서 베리어 메탈층(18)이 형성된 후, 상기 베리어 메탈층(18) 상부에 핵생성층(미도시)이 형성된다. 이러한 핵생성층은 환원가스로 SiH4를 20sccm 내지 40sccm, 바람직하게는 30sccm, WF6가스를 30sccm 내지 50sccm, 바람직하게는 40sccm로 공급하여 300Å 내지 500Å, 바람직하게는 400Å의 두께로 형성된다.Referring to FIG. 3, after the barrier metal layer 18 is formed in FIG. 2, a nucleation layer (not shown) is formed on the barrier metal layer 18. The nucleation layer is formed to a thickness of 300 kPa to 500 kPa, preferably 400 kPa by supplying SiH 4 to 20 sccm to 40 sccm, preferably 30 sccm, and WF 6 gas at 30 sccm to 50 sccm, preferably 40 sccm as a reducing gas.
핵생성층은 후속 콘택 플러그(20) 형성공정시 텅스텐층의 성장을 돕는 역할을 한다. 그리고, 핵생성층의 다른 중요한 역할은 SiH4가스가 WF6의 환원가스로 이용되는 경우가 H2가스가 WF6의 환원가스로 이용되는 경우보다 스텝 커버리지(step coverage) 특성은 열악하지만 반응속도는 훨씬 빠른 특성을 가지고 있다. 이러한 특성을 이용하면, 베리어 메탈층(18)이 WF6가스에 노출되는 시간을 감소시킬 수 있다. 따라서, 핵생성층의 역할은 빠른 성장속도를 이용한 WF6가스의 공격에서부터 베리어 메탈층(18)을 보호하는데 있다. 하지만, 핵생성층을 너무 두껍게 증착하면스텝 커버리지가 좋지 않은 핵생성층의 특성상 콘택홀(16)에 두꺼운 오버행(over hang)을 야기시켜 후속에서 이루어지는 필링(filling) 공정에서 WF6가스의 공급이 차단되어 우수한 스텝 커버리지를 얻을 수 없게 된다. 즉, 핵생성층의 가장 큰 공정 포인트(point)는 될 수 있으면 얇게, 그리고 저부에서 골고루 증착이 되도록 하여 후속에서 이루어지는 필링 공정에서 쉽게 저부에도 텅스텐층이 성장되도록 하고, 오버 행이 없이 우수한 스텝 커버리지를 확보할 수 있어야만 한다. 이러한 사항을 고려하여 볼때, 핵생성층을 형성하는 가장 좋은 방법은 베리어 메탈층(18)과 콘택 플러그(20)의 증착공정을 최적화하여 초기 반응속도는 느리지만 스텝 커버리지가 우수한 H2가스를 환원가스로 이용하여 핵생성층을 성장시키는 방법이 가장 우수한 필링 특성을 얻을 수 있다.The nucleation layer serves to help the growth of the tungsten layer during the subsequent contact plug 20 formation process. And, another important role of the nucleation layer SiH 4 gas has a step coverage (step coverage) characteristics than when used as a reducing gas of the H 2 gas is WF 6 when used as a reducing gas of WF 6 is poor, but the reaction rate Is much faster. Using this property, the time for the barrier metal layer 18 to be exposed to the WF 6 gas can be reduced. Therefore, the role of the nucleation layer is to protect the barrier metal layer 18 from the attack of the WF 6 gas using the rapid growth rate. However, depositing the nucleation layer too thick causes a thick overhang in the contact hole 16 due to the nature of the nucleation layer, which has poor step coverage, and thus the supply of the WF 6 gas in the subsequent filling process is prevented. It is blocked and no good step coverage is obtained. That is, the largest process point of the nucleation layer is as thin as possible and evenly deposited at the bottom so that tungsten layers can be easily grown at the bottom in the subsequent filling process, and have excellent step coverage without overhang. Must be able to secure In view of these considerations, the best way to form the nucleation layer is to optimize the deposition process of the barrier metal layer 18 and the contact plug 20 to reduce H 2 gas having a low initial reaction rate but excellent step coverage. The method of growing a nucleation layer using a gas can obtain the best peeling characteristics.
따라서, 본 발명의 또 다른 실시예에 따른 핵생성층 형성방법은 CVD 방법을 이용하여 환원가스로 H2가스를 350sccm 내지 450sccm, 바람직하게는 400sccm, WF6가스를 20sccm 내지 30sccm, 바람직하게는 25sccm로 공급하여 300Å 내지 500Å, 바람직하게는 400Å의 두께로 핵생성층이 형성되도록 실시된다. 이와 같은 방법은 초기 반응속도는 느리지만, 스텝 커버리지가 우수한 H2가스를 환원가스로 이용하여 핵생성층을 성장시키는 방법으로, 본 발명의 일실시예인 SiH4가스를 환원가스로 이용할 경우에 발생할 수 있는 상부(top)의 오버행 문제를 해결하여 가장 우수한 필링 특성을 얻을 수 있다.Therefore, the method for forming a nucleation layer according to another embodiment of the present invention is 350 sccm to 450 sccm of H 2 gas, preferably 400 sccm, and 20 sccm to 30 sccm, preferably 25 sccm of WF 6 gas as a reducing gas using a CVD method. It is carried out so that the nucleation layer is formed to a thickness of 300 kPa to 500 kPa, preferably 400 kPa. Such a method is a method of growing a nucleation layer using H 2 gas having excellent initial step coverage but excellent step coverage as a reducing gas, and is generated when SiH 4 gas, which is an embodiment of the present invention, is used as a reducing gas. It is possible to obtain the best peeling properties by solving the problem of the top overhang.
핵생성층이 형성된 후, 콘택홀(18)이 갭(gap) 필링되도록 콘택 플러그(20)가 형성된다. 콘택 플러그(20)는 환원가스로 H2가스를 35000sccm 내지 4500sccm, 바람직하게는 4000sccm, WF6가스를 200sccm 내지 300sccm, 바람직하게는 250sccm로 공급하여 3000Å 내지 4000Å, 바람직하게는 3600Å의 두께로 텅스텐층이 증착되어 형성된다.After the nucleation layer is formed, the contact plug 20 is formed so that the contact hole 18 is gap filled. The contact plug 20 is a tungsten layer having a thickness of 3000 kPa to 4000 kPa, preferably 3600 kPa by supplying H 2 gas as a reducing gas to 35000 sccm to 4500 sccm, preferably 4000 sccm, and WF 6 gas at 200 sccm to 300 sccm, preferably 250 sccm. Is deposited and formed.
상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같이, 본 발명에 의하면, 스텝 커버리지가 우수한 H2가스를 환원가스로 이용하여 핵생성층을 형성시킴으로써 우수한 저항특성과 스텝 커버리지를 확보할 수 있다.As described above, according to the present invention, an excellent resistance characteristic and step coverage can be secured by forming a nucleation layer using H 2 gas having excellent step coverage as a reducing gas.
또한, 본 발명에 의하면, 반응속도가 빠른 SiH4가스를 환원가스로 이용하여 핵생성층을 형성시킴으로써 베리어 메탈층이 WF6에 노출되는 시간을 최소화시켜 WF6 가스의 공격을 최소화시킬 수 있다.In addition, according to the present invention, by forming a nucleation layer using SiH 4 gas having a fast reaction rate as a reducing gas, the attack time of the WF 6 gas can be minimized by minimizing the time that the barrier metal layer is exposed to WF 6 .
또한, 본 발명에 의하면, 베리어 메탈층을 구성하는 TiN막을 적어도 3회로 나누어 증착하여 콘택홀 내에서 균등하게 상기 TiN막이 증착 및 플라즈마 처리되도록 함으로써 후속 핵생성층 형성공정시 베리어 메탈층의 폭발에 의한 페일을 방지할 수 있다.In addition, according to the present invention, the TiN film constituting the barrier metal layer is deposited at least three times so that the TiN film is deposited and plasma treated evenly in the contact hole, so that the barrier metal layer is exploded during the subsequent nucleation layer forming process. Fail can be prevented.
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| KR100919808B1 (en) * | 2008-01-02 | 2009-10-01 | 주식회사 하이닉스반도체 | Method of fabricating tungsten layer in semiconductor device |
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| KR100745066B1 (en) * | 2005-03-24 | 2007-08-01 | 주식회사 하이닉스반도체 | Method for fabricating metal plug of semiconductor device |
| KR100919808B1 (en) * | 2008-01-02 | 2009-10-01 | 주식회사 하이닉스반도체 | Method of fabricating tungsten layer in semiconductor device |
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